[LLVM] Fix Clang-tidy modernize-use-bool-literals in generated target code; other minor fixes; other minor fixes

[Eugene.Zelenko]

Summary

Make generated more readable.

Fix some Include What You Use warnings.

I checked this patch on my own build on RHEL 6. Regressions were OK.

[hans]

lgtm

llvm/trunk/utils/TableGen/RegisterInfoEmitter.cpp

 // register file for a code generator.  It uses instances of the Register,
 // RegisterAliases, and RegisterClass classes to gather this information.
 //
 //===----------------------------------------------------------------------===//
 
 #include "CodeGenRegisters.h"
 #include "CodeGenTarget.h"
 #include "SequenceToOffsetTable.h"
+#include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/BitVector.h"
+#include "llvm/ADT/SetVector.h"
+#include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/SparseBitVector.h"
 #include "llvm/ADT/STLExtras.h"
-#include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/Twine.h"
+#include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/Support/Casting.h"
 #include "llvm/Support/Format.h"
+#include "llvm/Support/raw_ostream.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
+#include "llvm/TableGen/SetTheory.h"
 #include "llvm/TableGen/TableGenBackend.h"
 #include <algorithm>
+#include <cassert>
+#include <cstddef>
+#include <cstdint>
+#include <deque>
+#include <iterator>
 #include <set>
+#include <string>
 #include <vector>
+
 using namespace llvm;
 
 namespace {
+
 class RegisterInfoEmitter {
   RecordKeeper &Records;
+
 public:
   RegisterInfoEmitter(RecordKeeper &R) : Records(R) {}
 
   // runEnums - Print out enum values for all of the registers.
   void runEnums(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
 
   // runMCDesc - Print out MC register descriptions.
   void runMCDesc(raw_ostream &o, CodeGenTarget &Target, CodeGenRegBank &Bank);
void EmitRegMappingTables(raw_ostream &o,
                             bool isCtor);
   void EmitRegUnitPressure(raw_ostream &OS, const CodeGenRegBank &RegBank,
                            const std::string &ClassName);
   void emitComposeSubRegIndices(raw_ostream &OS, CodeGenRegBank &RegBank,
                                 const std::string &ClassName);
   void emitComposeSubRegIndexLaneMask(raw_ostream &OS, CodeGenRegBank &RegBank,
                                       const std::string &ClassName);
 };
-} // End anonymous namespace
+
+} // end anonymous namespace
 
 // runEnums - Print out enum values for all of the registers.
 void RegisterInfoEmitter::runEnums(raw_ostream &OS,
                                    CodeGenTarget &Target, CodeGenRegBank &Bank) {
   const auto &Registers = Bank.getRegisters();
 
   // Register enums are stored as uint16_t in the tables. Make sure we'll fit.
   assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
 
   std::string Namespace =
       Registers.front().TheDef->getValueAsString("Namespace");
 
   emitSourceFileHeader("Target Register Enum Values", OS);
 
   OS << "\n#ifdef GET_REGINFO_ENUM\n";
-  OS << "#undef GET_REGINFO_ENUM\n";
+  OS << "#undef GET_REGINFO_ENUM\n\n";
 
   OS << "namespace llvm {\n\n";
 
   OS << "class MCRegisterClass;\n"
      << "extern const MCRegisterClass " << Namespace
      << "MCRegisterClasses[];\n\n";
 
   if (!Namespace.empty())
     OS << "namespace " << Namespace << " {\n";
   OS << "enum {\n  NoRegister,\n";
 
   for (const auto &Reg : Registers)
     OS << "  " << Reg.getName() << " = " << Reg.EnumValue << ",\n";
   assert(Registers.size() == Registers.back().EnumValue &&
          "Register enum value mismatch!");
   OS << "  NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
   OS << "};\n";
   if (!Namespace.empty())
-    OS << "}\n";
+    OS << "} // end namespace " << Namespace << "\n";
 
   const auto &RegisterClasses = Bank.getRegClasses();
   if (!RegisterClasses.empty()) {
 
     // RegisterClass enums are stored as uint16_t in the tables.
     assert(RegisterClasses.size() <= 0xffff &&
            "Too many register classes to fit in tables");
 
-    OS << "\n// Register classes\n";
+    OS << "\n// Register classes\n\n";
     if (!Namespace.empty())
       OS << "namespace " << Namespace << " {\n";
     OS << "enum {\n";
     for (const auto &RC : RegisterClasses)
       OS << "  " << RC.getName() << "RegClassID"
          << " = " << RC.EnumValue << ",\n";
     OS << "\n  };\n";
     if (!Namespace.empty())
-      OS << "}\n";
+      OS << "} // end namespace " << Namespace << "\n\n";
   }
 
   const std::vector<Record*> &RegAltNameIndices = Target.getRegAltNameIndices();
   // If the only definition is the default NoRegAltName, we don't need to
   // emit anything.
   if (RegAltNameIndices.size() > 1) {
-    OS << "\n// Register alternate name indices\n";
+    OS << "\n// Register alternate name indices\n\n";
     if (!Namespace.empty())
       OS << "namespace " << Namespace << " {\n";
     OS << "enum {\n";
     for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
       OS << "  " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
     OS << "  NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
     OS << "};\n";
     if (!Namespace.empty())
-      OS << "}\n";
+      OS << "} // end namespace " << Namespace << "\n\n";
   }
 
   auto &SubRegIndices = Bank.getSubRegIndices();
   if (!SubRegIndices.empty()) {
-    OS << "\n// Subregister indices\n";
+    OS << "\n// Subregister indices\n\n";
     std::string Namespace = SubRegIndices.front().getNamespace();
     if (!Namespace.empty())
       OS << "namespace " << Namespace << " {\n";
     OS << "enum {\n  NoSubRegister,\n";
     unsigned i = 0;
     for (const auto &Idx : SubRegIndices)
       OS << "  " << Idx.getName() << ",\t// " << ++i << "\n";
     OS << "  NUM_TARGET_SUBREGS\n};\n";
     if (!Namespace.empty())
-      OS << "}\n";
+      OS << "} // end namespace " << Namespace << "\n\n";
   }
 
-  OS << "} // End llvm namespace\n";
+  OS << "} // end namespace llvm\n\n";
   OS << "#endif // GET_REGINFO_ENUM\n\n";
 }
 
 static void printInt(raw_ostream &OS, int Val) {
   OS << Val;
 }
 
 static const char *getMinimalTypeForRange(uint64_t Range) {

 // runMCDesc - Print out MC register descriptions.
 //
 void
 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
                                CodeGenRegBank &RegBank) {
   emitSourceFileHeader("MC Register Information", OS);
 
   OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
-  OS << "#undef GET_REGINFO_MC_DESC\n";
+  OS << "#undef GET_REGINFO_MC_DESC\n\n";
 
   const auto &Regs = RegBank.getRegisters();
 
   auto &SubRegIndices = RegBank.getSubRegIndices();
   // The lists of sub-registers and super-registers go in the same array.  That
   // allows us to share suffixes.
   typedef std::vector<const CodeGenRegister*> RegVec;
 
for (const auto &RC : RegisterClasses) {
     for (unsigned i = 0, e = Order.size(); i != e; ++i) {
       Record *Reg = Order[i];
       BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
     }
     BVE.print(OS);
     OS << "\n  };\n\n";
 
   }
-  OS << "}\n\n";
+  OS << "} // end anonymous namespace\n\n";
 
   RegClassStrings.layout();
   OS << "extern const char " << TargetName << "RegClassStrings[] = {\n";
   RegClassStrings.emit(OS, printChar);
   OS << "};\n\n";
 
   OS << "extern const MCRegisterClass " << TargetName
      << "MCRegisterClasses[] = {\n";
 
   for (const auto &RC : RegisterClasses) {
     // Asserts to make sure values will fit in table assuming types from
     // MCRegisterInfo.h
     assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
     assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
     assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
 
     OS << "  { " << RC.getName() << ", " << RC.getName() << "Bits, "
        << RegClassStrings.get(RC.getName()) << ", "
        << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
        << RC.getQualifiedName() + "RegClassID" << ", "
        << RC.SpillSize/8 << ", "
        << RC.SpillAlignment/8 << ", "
        << RC.CopyCost << ", "
-       << RC.Allocatable << " },\n";
+       << ( RC.Allocatable ? "true" : "false" ) << " },\n";
   }
 
   OS << "};\n\n";
 
   EmitRegMappingTables(OS, Regs, false);
 
   // Emit Reg encoding table
   OS << "extern const uint16_t " << TargetName;
OS << "static inline void Init" << TargetName
      << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n"
      << TargetName << "SubRegIdxRanges, " << TargetName
      << "RegEncodingTable);\n\n";
 
   EmitRegMapping(OS, Regs, false);
 
   OS << "}\n\n";
 
-  OS << "} // End llvm namespace\n";
+  OS << "} // end namespace llvm\n\n";
   OS << "#endif // GET_REGINFO_MC_DESC\n\n";
 }
 
 void
 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
                                      CodeGenRegBank &RegBank) {
   emitSourceFileHeader("Register Information Header Fragment", OS);
 
   OS << "\n#ifdef GET_REGINFO_HEADER\n";
-  OS << "#undef GET_REGINFO_HEADER\n";
+  OS << "#undef GET_REGINFO_HEADER\n\n";
 
   const std::string &TargetName = Target.getName();
   std::string ClassName = TargetName + "GenRegisterInfo";
 
   OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
 
   OS << "namespace llvm {\n\n";
 
OS << "namespace " << RegisterClasses.front().Namespace
        << " { // Register classes\n";
 
     for (const auto &RC : RegisterClasses) {
       const std::string &Name = RC.getName();
 
       // Output the extern for the instance.
       OS << "  extern const TargetRegisterClass " << Name << "RegClass;\n";
     }
-    OS << "} // end of namespace " << TargetName << "\n\n";
+    OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n";
   }
-  OS << "} // End llvm namespace\n";
+  OS << "} // end namespace llvm\n\n";
   OS << "#endif // GET_REGINFO_HEADER\n\n";
 }
 
 //
 // runTargetDesc - Output the target register and register file descriptions.
 //
 void
 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
                                    CodeGenRegBank &RegBank){
   emitSourceFileHeader("Target Register and Register Classes Information", OS);
 
   OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
-  OS << "#undef GET_REGINFO_TARGET_DESC\n";
+  OS << "#undef GET_REGINFO_TARGET_DESC\n\n";
 
   OS << "namespace llvm {\n\n";
 
   // Get access to MCRegisterClass data.
   OS << "extern const MCRegisterClass " << Target.getName()
      << "MCRegisterClasses[];\n";
 
   // Start out by emitting each of the register classes.
for (const auto &RC : RegisterClasses) {
         OS << RC.getName() << "Superclasses,\n    ";
       if (RC.AltOrderSelect.empty())
         OS << "nullptr\n";
       else
         OS << RC.getName() << "GetRawAllocationOrder\n";
       OS << "  };\n\n";
     }
 
-    OS << "}\n";
+    OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n";
   }
 
   OS << "\nnamespace {\n";
   OS << "  const TargetRegisterClass* const RegisterClasses[] = {\n";
   for (const auto &RC : RegisterClasses)
     OS << "    &" << RC.getQualifiedName() << "RegClass,\n";
   OS << "  };\n";
-  OS << "}\n";       // End of anonymous namespace...
+  OS << "} // end anonymous namespace\n";
 
   // Emit extra information about registers.
   const std::string &TargetName = Target.getName();
   OS << "\nstatic const TargetRegisterInfoDesc "
      << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
-  OS << "  { 0, 0 },\n";
+  OS << "  { 0, false },\n";
 
   const auto &Regs = RegBank.getRegisters();
   for (const auto &Reg : Regs) {
     OS << "  { ";
     OS << Reg.CostPerUse << ", "
-       << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
+       << ( AllocatableRegs.count(Reg.TheDef) != 0 ? "true" : "false" )
+       << " },\n";
   }
   OS << "};\n";      // End of register descriptors...
 
 
   std::string ClassName = Target.getName() + "GenRegisterInfo";
 
   auto SubRegIndicesSize =
       std::distance(SubRegIndices.begin(), SubRegIndices.end());
OS << ") {\n"
      << "                     " << SubRegIndicesSize + 1 << ",\n"
      << "                     " << TargetName << "SubRegIdxRanges,\n"
      << "                     " << TargetName << "RegEncodingTable);\n\n";
 
   EmitRegMapping(OS, Regs, true);
 
   OS << "}\n\n";
 
-
   // Emit CalleeSavedRegs information.
   std::vector<Record*> CSRSets =
     Records.getAllDerivedDefinitions("CalleeSavedRegs");
   for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
     Record *CSRSet = CSRSets[i];
     const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
     assert(Regs && "Cannot expand CalleeSavedRegs instance");
 
RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
   OS << "}\n\n";
 
   OS << "const " << TargetName << "FrameLowering *\n" << TargetName
      << "GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {\n"
      << "  return static_cast<const " << TargetName << "FrameLowering *>(\n"
      << "      MF.getSubtarget().getFrameLowering());\n"
      << "}\n\n";
 
-  OS << "} // End llvm namespace\n";
+  OS << "} // end namespace llvm\n\n";
   OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
 }
 
 void RegisterInfoEmitter::run(raw_ostream &OS) {
   CodeGenTarget Target(Records);
   CodeGenRegBank &RegBank = Target.getRegBank();
   RegBank.computeDerivedInfo();
 
   runEnums(OS, Target, RegBank);
   runMCDesc(OS, Target, RegBank);
   runTargetHeader(OS, Target, RegBank);
   runTargetDesc(OS, Target, RegBank);
 }
 
 namespace llvm {
 
 void EmitRegisterInfo(RecordKeeper &RK, raw_ostream &OS) {
   RegisterInfoEmitter(RK).run(OS);
 }
 
-} // End llvm namespace
+} // end namespace llvm

llvm/trunk/utils/TableGen/SubtargetEmitter.cpp

 //===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This tablegen backend emits subtarget enumerations.
 //
 //===----------------------------------------------------------------------===//
 
 #include "CodeGenTarget.h"
 #include "CodeGenSchedule.h"
-#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/MC/MCInstrItineraries.h"
+#include "llvm/MC/MCSchedule.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/Format.h"
+#include "llvm/Support/raw_ostream.h"
 #include "llvm/TableGen/Error.h"
 #include "llvm/TableGen/Record.h"
 #include "llvm/TableGen/TableGenBackend.h"
 #include <algorithm>
+#include <cassert>
+#include <cstdint>
 #include <map>
 #include <string>
 #include <vector>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "subtarget-emitter"
 
 namespace {
+
 class SubtargetEmitter {
   // Each processor has a SchedClassDesc table with an entry for each SchedClass.
   // The SchedClassDesc table indexes into a global write resource table, write
   // latency table, and read advance table.
   struct SchedClassTables {
     std::vector<std::vector<MCSchedClassDesc> > ProcSchedClasses;
     std::vector<MCWriteProcResEntry> WriteProcResources;
     std::vector<MCWriteLatencyEntry> WriteLatencies;
void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
                              unsigned NumProcs);
 
 public:
   SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT):
     Records(R), SchedModels(TGT.getSchedModels()), Target(TGT.getName()) {}
 
   void run(raw_ostream &o);
 };
+
 } // end anonymous namespace
 
 //
 // Enumeration - Emit the specified class as an enumeration.
 //
 void SubtargetEmitter::Enumeration(raw_ostream &OS) {
   // Get all records of class and sort
   std::vector<Record*> DefList =
for (unsigned i = 0; i < N;) {
     // Get and emit name
     OS << "  " << Def->getName() << " = " << i;
     if (++i < N) OS << ",";
 
     OS << "\n";
   }
 
   // Close enumeration and namespace
-  OS << "};\n}\n";
+  OS << "};\n";
+  OS << "} // end namespace " << Target << "\n";
 }
 
 //
 // FeatureKeyValues - Emit data of all the subtarget features.  Used by the
 // command line.
 //
 unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) {
   // Gather and sort all the features
for (const CodeGenProcModel &ProcModel : SchedModels.procModels()) {
     const std::string &Name = ProcModel.ItinsDef->getName();
     OS << "\n// Functional units for \"" << Name << "\"\n"
        << "namespace " << Name << "FU {\n";
 
     for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j)
       OS << "  const unsigned " << FUs[j]->getName()
          << " = 1 << " << j << ";\n";
 
-    OS << "}\n";
+    OS << "} // end namespace " << Name << "FU\n";
 
     std::vector<Record*> BPs = ProcModel.ItinsDef->getValueAsListOfDefs("BP");
     if (!BPs.empty()) {
       OS << "\n// Pipeline forwarding pathes for itineraries \"" << Name
          << "\"\n" << "namespace " << Name << "Bypass {\n";
 
       OS << "  const unsigned NoBypass = 0;\n";
       for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j)
         OS << "  const unsigned " << BPs[j]->getName()
            << " = 1 << " << j << ";\n";
 
-      OS << "}\n";
+      OS << "} // end namespace " << Name << "Bypass\n";
     }
   }
 
   // Begin stages table
   std::string StageTable = "\nextern const llvm::InstrStage " + Target +
                            "Stages[] = {\n";
   StageTable += "  { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";
 
OS << "static const llvm::MCSchedClassDesc "
        << PI->ModelName << "SchedClasses[] = {\n";
 
     // The first class is always invalid. We no way to distinguish it except by
     // name and position.
     assert(SchedModels.getSchedClass(0).Name == "NoInstrModel"
            && "invalid class not first");
     OS << "  {DBGFIELD(\"InvalidSchedClass\")  "
        << MCSchedClassDesc::InvalidNumMicroOps
-       << ", 0, 0,  0, 0,  0, 0,  0, 0},\n";
+       << ", false, false,  0, 0,  0, 0,  0, 0},\n";
 
     for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) {
       MCSchedClassDesc &MCDesc = SCTab[SCIdx];
       const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx);
       OS << "  {DBGFIELD(\"" << SchedClass.Name << "\") ";
       if (SchedClass.Name.size() < 18)
         OS.indent(18 - SchedClass.Name.size());
       OS << MCDesc.NumMicroOps
-         << ", " << MCDesc.BeginGroup << ", " << MCDesc.EndGroup
+         << ", " << ( MCDesc.BeginGroup ? "true" : "false" )
+         << ", " << ( MCDesc.EndGroup ? "true" : "false" )
          << ", " << format("%2d", MCDesc.WriteProcResIdx)
          << ", " << MCDesc.NumWriteProcResEntries
          << ", " << format("%2d", MCDesc.WriteLatencyIdx)
          << ", " << MCDesc.NumWriteLatencyEntries
          << ", " << format("%2d", MCDesc.ReadAdvanceIdx)
          << ", " << MCDesc.NumReadAdvanceEntries << "}";
       if (SCIdx + 1 < SCEnd)
         OS << ',';
for (const CodeGenProcModel &PM : SchedModels.procModels()) {
     OS << "static const llvm::MCSchedModel " << PM.ModelName << " = {\n";
     EmitProcessorProp(OS, PM.ModelDef, "IssueWidth", ',');
     EmitProcessorProp(OS, PM.ModelDef, "MicroOpBufferSize", ',');
     EmitProcessorProp(OS, PM.ModelDef, "LoopMicroOpBufferSize", ',');
     EmitProcessorProp(OS, PM.ModelDef, "LoadLatency", ',');
     EmitProcessorProp(OS, PM.ModelDef, "HighLatency", ',');
     EmitProcessorProp(OS, PM.ModelDef, "MispredictPenalty", ',');
 
-    OS << "  " << (bool)(PM.ModelDef ?
-                         PM.ModelDef->getValueAsBit("PostRAScheduler") : 0)
-       << ", // " << "PostRAScheduler\n";
-
-    OS << "  " << (bool)(PM.ModelDef ?
-                         PM.ModelDef->getValueAsBit("CompleteModel") : 0)
-       << ", // " << "CompleteModel\n";
+    bool PostRAScheduler =
+      (PM.ModelDef ? PM.ModelDef->getValueAsBit("PostRAScheduler") : false);
+
+    OS << "  " << (PostRAScheduler ? "true" : "false")  << ", // "
+       << "PostRAScheduler\n";
+
+    bool CompleteModel =
+      (PM.ModelDef ? PM.ModelDef->getValueAsBit("CompleteModel") : false);
+
+    OS << "  " << (CompleteModel ? "true" : "false") << ", // "
+       << "CompleteModel\n";
 
     OS << "  " << PM.Index << ", // Processor ID\n";
     if (PM.hasInstrSchedModel())
       OS << "  " << PM.ModelName << "ProcResources" << ",\n"
          << "  " << PM.ModelName << "SchedClasses" << ",\n"
          << "  " << PM.ProcResourceDefs.size()+1 << ",\n"
          << "  " << (SchedModels.schedClassEnd()
                      - SchedModels.schedClassBegin()) << ",\n";

 
 //
 // SubtargetEmitter::run - Main subtarget enumeration emitter.
 //
 void SubtargetEmitter::run(raw_ostream &OS) {
   emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
 
   OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n";
-  OS << "#undef GET_SUBTARGETINFO_ENUM\n";
+  OS << "#undef GET_SUBTARGETINFO_ENUM\n\n";
 
   OS << "namespace llvm {\n";
   Enumeration(OS);
-  OS << "} // end llvm namespace\n";
+  OS << "} // end namespace llvm\n\n";
   OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
 
   OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
-  OS << "#undef GET_SUBTARGETINFO_MC_DESC\n";
+  OS << "#undef GET_SUBTARGETINFO_MC_DESC\n\n";
 
   OS << "namespace llvm {\n";
 #if 0
   OS << "namespace {\n";
 #endif
   unsigned NumFeatures = FeatureKeyValues(OS);
   OS << "\n";
   unsigned NumProcs = CPUKeyValues(OS);
   OS << "\n";
   EmitSchedModel(OS);
   OS << "\n";
 #if 0
-  OS << "}\n";
+  OS << "} // end anonymous namespace\n\n";
 #endif
 
   // MCInstrInfo initialization routine.
   OS << "static inline MCSubtargetInfo *create" << Target
      << "MCSubtargetInfoImpl("
      << "const Triple &TT, StringRef CPU, StringRef FS) {\n";
   OS << "  return new MCSubtargetInfo(TT, CPU, FS, ";
   if (NumFeatures)
if (SchedModels.hasItineraries()) {
     OS << '\n'; OS.indent(22);
     OS << Target << "Stages, "
        << Target << "OperandCycles, "
        << Target << "ForwardingPaths";
   } else
     OS << "0, 0, 0";
   OS << ");\n}\n\n";
 
-  OS << "} // end llvm namespace\n";
+  OS << "} // end namespace llvm\n\n";
 
   OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n";
 
   OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n";
-  OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n";
+  OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n\n";
 
   OS << "#include \"llvm/Support/Debug.h\"\n";
-  OS << "#include \"llvm/Support/raw_ostream.h\"\n";
+  OS << "#include \"llvm/Support/raw_ostream.h\"\n\n";
   ParseFeaturesFunction(OS, NumFeatures, NumProcs);
 
   OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
 
   // Create a TargetSubtargetInfo subclass to hide the MC layer initialization.
   OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";
-  OS << "#undef GET_SUBTARGETINFO_HEADER\n";
+  OS << "#undef GET_SUBTARGETINFO_HEADER\n\n";
 
   std::string ClassName = Target + "GenSubtargetInfo";
   OS << "namespace llvm {\n";
   OS << "class DFAPacketizer;\n";
   OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
      << "  explicit " << ClassName << "(const Triple &TT, StringRef CPU, "
      << "StringRef FS);\n"
      << "public:\n"
      << "  unsigned resolveSchedClass(unsigned SchedClass, "
      << " const MachineInstr *DefMI,"
      << " const TargetSchedModel *SchedModel) const override;\n"
      << "  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
      << " const;\n"
      << "};\n";
-  OS << "} // end llvm namespace\n";
+  OS << "} // end namespace llvm\n\n";
 
   OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n";
 
   OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n";
-  OS << "#undef GET_SUBTARGETINFO_CTOR\n";
+  OS << "#undef GET_SUBTARGETINFO_CTOR\n\n";
 
-  OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n";
+  OS << "#include \"llvm/CodeGen/TargetSchedule.h\"\n\n";
   OS << "namespace llvm {\n";
   OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
   OS << "extern const llvm::SubtargetFeatureKV " << Target << "SubTypeKV[];\n";
   OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n";
   OS << "extern const llvm::MCWriteProcResEntry "
      << Target << "WriteProcResTable[];\n";
   OS << "extern const llvm::MCWriteLatencyEntry "
      << Target << "WriteLatencyTable[];\n";
OS << Target << "Stages, "
        << Target << "OperandCycles, "
        << Target << "ForwardingPaths";
   } else
     OS << "0, 0, 0";
   OS << ") {}\n\n";
 
   EmitSchedModelHelpers(ClassName, OS);
 
-  OS << "} // end llvm namespace\n";
+  OS << "} // end namespace llvm\n\n";
 
   OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
 }
 
 namespace llvm {
 
 void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) {
   CodeGenTarget CGTarget(RK);
   SubtargetEmitter(RK, CGTarget).run(OS);
 }
 
-} // end llvm namespace
+} // end namespace llvm