AMDGPU: Make some instructions convergent

[nhaehnle]

LGTM

Out of curiosity, what does making v_readlane/v_writelane convergent fix? I thought they were independent of control flow...

[arsenm]

In D20071#424843, @nhaehnle wrote:

LGTM

Out of curiosity, what does making v_readlane/v_writelane convergent fix? I thought they were independent of control flow...

Now I'm not really sure about them. I was just thinking any of the instructions that do any kind of crosslane interactions would be convergent

[resistor]

In D20071#424886, @arsenm wrote:

In D20071#424843, @nhaehnle wrote:

LGTM

Out of curiosity, what does making v_readlane/v_writelane convergent fix? I thought they were independent of control flow...

Now I'm not really sure about them. I was just thinking any of the instructions that do any kind of crosslane interactions would be convergent

Assuming that they do what I imagine (read the corresponding register from a neighboring thread), they need to be convergent in order to ensure that the desired value hasn't been clobbered on the neighboring thread. Consider:

r0 = readlane(r0)
if ( ...) {

// r0 unused, gets reused as scratch register

} else {

// use r0

}

If we sink the readlane into the else block things break. Imagine the scenario where thread 0 in the wavefront takes the if branch, but thread 1 takes the else branch. Because they execute in lockstep, thread 0's code will execute first, and clobber the value in its r0. By the time thread 1 gets to run the sunken readlane, the proper value is no longer available in the neighbor's r0.

[arsenm]

r269147

lib/Target/AMDGPU/SIInstructions.td

 // FIXME: Specify SchedRW for READFIRSTLANE_B32
 
 def V_READFIRSTLANE_B32 : VOP1 <
   0x00000002,
   (outs SReg_32:$vdst),
   (ins VS_32:$src0),
   "v_readfirstlane_b32 $vdst, $src0",
   []
->;
+> {
+  let isConvergent = 1;
+}
 
 }
 
 let SchedRW = [WriteQuarterRate32] in {
 
 defm V_CVT_I32_F64 : VOP1Inst <vop1<0x3>, "v_cvt_i32_f64",
   VOP_I32_F64, fp_to_sint
 >;
defm V_SUBB_U32 : VOP2bInst <vop2<0x29, 0x1d>, "v_subb_u32",
   VOP2b_I32_I1_I32_I32_I1
 >;
 defm V_SUBBREV_U32 : VOP2bInst <vop2<0x2a, 0x1e>, "v_subbrev_u32",
   VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32"
 >;
 
 } // End isCommutable = 1
 
+let isConvergent = 1 in {
+
 defm V_READLANE_B32 : VOP2SI_3VI_m <
   vop3 <0x001, 0x289>,
   "v_readlane_b32",
   (outs SReg_32:$vdst),
   (ins VS_32:$src0, SCSrc_32:$src1),
   "v_readlane_b32 $vdst, $src0, $src1"
 >;
 
 defm V_WRITELANE_B32 : VOP2SI_3VI_m <
   vop3 <0x002, 0x28a>,
   "v_writelane_b32",
   (outs VGPR_32:$vdst),
   (ins SReg_32:$src0, SCSrc_32:$src1),
   "v_writelane_b32 $vdst, $src0, $src1"
 >;
 
+} // End isConvergent = 1
+
 // These instructions only exist on SI and CI
 let SubtargetPredicate = isSICI in {
 
 let isCommutable = 1 in {
 defm V_MAC_LEGACY_F32 : VOP2InstSI <vop2<0x6>, "v_mac_legacy_f32",
   VOP_F32_F32_F32
 >;
 } // End isCommutable = 1