[PPC] exploitation of new xscmp*, as well as xsmaxcdp and xsmincdp

[syzaara]

Summary

Some background on why this approach was chosen. This was discussed on Hall's Tuesday's call.

The choice of this approach for implementation is the result of how selectcc operation actions are handled. We first look at the operation action for condition code, and then based on that we look at operation action for selectcc. If we could have looked at both together, then we could have avoided expansion of selectcc, for data types that expansion is not needed, and do a simple pattern match in tablegen. Given that this is not what we currently do, we have some fairly complicated patterns reaching to instruction selection. Since these patterns has to be distinguished from the ones that we want to handle inside the PPCIselDAGtoDAG::Select, we practically need to do the full pattern matching in C++ code.

There are other approaches (for example, not expanding selectcc for floating point condition code during Operation Legalization and then adding a custom handler for vector and int data types). The reason that this approach was not taken is this: Selectcc handling is scattered in multiple places in the code. An approach like this, has the risk of breaking existing code for other data types and their corner cases and becoming a large project.

[amehsan]

I forgot to add tests for the -mattr=-power9-vector. Will add that.

[nemanjai]

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

533

Why the restriction to double precision values? The ISA document mentions this instruction can be used for both single and double precision operands.

lib/Target/PowerPC/PPCInstrVSX.td

2667

Patterns for f32?

test/CodeGen/PowerPC/vsx-p9.ll

3 ↗

(On Diff #56446)

And if you add f32 above, test cases for float as well.

[amehsan]

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

533

Thanks. I missed the foot note, and I had totally forgot the fact that single precisions are represented in double precision format when stored in a register (talking about scalar operations), so I didn't make the conclusion myself.

[amehsan]

I will post another review for exploitation of all instructions. That will subsume this one. The change is ready, I need to double check all cases are covered in the tests (there are more than 40 cases) and do some final clean up of the code.

[amehsan]

lib/Target/PowerPC/PPCInstrVSX.td

2447–2453

I will add f32 to here. For other opcodes, codegen is done from within C++ code, and that handles both data types.

[amehsan]

lib/Target/PowerPC/PPCISelLowering.cpp

6701–6704

There are advantage and disadvantages in using fsel when one of the operands is zero. Please let me know if you have any comment here.

[cycheng]

test/CodeGen/PowerPC/vsx-p9.ll

2 ↗

(On Diff #56980)

Need define:

target triple = "powerpc64-unknown-linux-gnu"

or:

llc -mtriple=powerpc64le-unknown-linux-gnu

[nemanjai]

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

534

Would it be appropriate to add an assert that N's opcode is correct (in case in the future this function is called from elsewhere)?

[amehsan]

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

534

Makes sense. Will do.

[nemanjai]

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

319

Perhaps a short comment describing what the purpose of this struct is.

559

Although the fall-through seems reasonable here, I think it's a good idea to add comments to that end. I'm not sure if everyone will agree with me though. So maybe others can chime in here as well.

589

Is it impossible that these operands do not exist? Namely, is it not possible that operand 1 of N does not have 3 operands thereby causing this call to assert for trying to get an invalid operand? Both here and below.

598

Same comment about fall-through.

test/CodeGen/PowerPC/vsx-p9.ll

2 ↗

(On Diff #56980)

Yes, the latter please. You should always specify the triple because I think other targets will get the "pwr9 is not a valid CPU for this target" message if you don't.

[amehsan]

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

559

Are you in doubt about functional correctness of fall-through or something else? functional correctness should be covered in the testcases. I will think about this again, to see if there are missing patterns in the testcases.

589

N has an opernad(0) because it is a select_cc. we have checked that N->getOperand(0).getOpcode() is and ISD::AND so it has operand (1). and we have checked that both N->getOperand(0).getOperand(0) and N->getOperand(0).getOperand(1) are SETCC so it has operand 0, 1 and 2.

[nemanjai]

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

559

No, the fall-through paths certainly seem fine. I'm only suggesting that fall-through occurrences in switch statements should be commented to inform the reader that this was intent rather than careless omission. I don't think it's even necessary to justify the fall-through (that should be left to the reader), just something as simple as

// fall-through

589

OK, excellent. I just didn't look through the early exit out of this conditional branch in detail. Although that brings me to a point I was initially going to post about the if statement above. I find that a descriptive comment for such involved conditional statements is invaluable.

Overall, it might be nice for this function to have a comment at the top describing all the kinds of DAGs it handles. I understand that we don't comment every possible DAG combine, but when the logic is not easy and straightforward to follow by reading the code, I find a descriptive comment goes a long way for readability.

[amehsan]

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

589

Sure, will add more comments to the code.

[cycheng]

Group1 Testcases:
define {double|float} @{max|min}_test{1|2}{_float}(%x, %y) #1
define {double|float} @{max|min}_test{1|2}{_float}_eq(%x, %y) #1
define {double|float} @fast_{max|min}_test{1|2}{_float}(%x, %y) #2
define {double|float} @fast_{max|min}_test{1|2}{_float}_eq(%x, %y) #2
Total: 8*4 = 32

Group2 Testcases:
define {double|float} @fast_{double|float}_{ugt|ult|ogt|olt|uge|ule|oge|ole}(%x, %y, %a, %b) #1
define {double|float} @nan_{double|float}_{ugt|ult|ogt|olt|uge|ule|oge|ole}(%x, %y, %a, %b) #2
Total: 16*2 = 32

Group3 Testcases:
define double @{one|oeq}_test{_fast}(%x, %y) {#1|#2}
Total: 4

• The prefix 'fast_' for functions is because of #1 {"no-nans-fp-math"="true"} or #2 {"no-nans-fp-math"="false"}? because the naming rule is a little bit different between Group1 and Group2.
• In Group2, how about unifying function naming when data type is double? I.e. omit "double" in function name when data type is double, as your 1st and 3rd test group naming rule.

Some other observations of test cases, just for reference

test cases for this statement:
  } else if (N->getOperand(0).getValueType() == MVT::i1) {
    ..
  }

define {float|double} @fast_{min|max}_test{1|2}{_float}_eq(%x, %y) #2
define {float|double} @nan_{float|double}_{ugt|ult|oge|ole}(%x, %y, %a, %b) #2
define double @one_test(double %x, double %y) #2

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

586

Looks like we want to handle this pattern:

t23: {f32|f64} = select_cc t20, Constant:i1<0>, t8, t6, setne:ch
  t20: i1 = and t17, t19
  t17: i1 = setcc t4, t2, setXXX:ch
  t19: i1 = setcc t4, t2, seto:ch

4396

I feel it is a little bit strange, if useP9VSXScalarComparisonInstr returns true, it should mean we can use p9vsx instructions for N, but actually even if the function returns true, we still have some cases that can't use p9vsx instructions.

Would it be better if:

if (useP9VSXScalarComparisonInstr(N, Summary)) {
  if (Summary.CC == ISD::CondCode::SETNE) { return ..; }
  if (Summary.Comp0 == Summary.Ret0 && ..) { return ..; }
  if (Summary.Comp0 == Summary.Ret1 && ..) { return ..; }
  if (CurDAG->getTarget().Options.NoNaNsFPMath) { return ..; }
  llvm_unreachable(..);
}

So useP9VSXScalarComparisonInstr might need additional arguments to help it judge if N is able to use p9vsx instructions.

test/CodeGen/PowerPC/vsx-p9.ll

492 ↗

(On Diff #56980)

Do we need the 'fast' flag when we have "no-nans-fp-math"="true" attribute?

537 ↗

(On Diff #56980)

ugt -> ogt?

658 ↗

(On Diff #56980)

ugt -> ogt?

778 ↗

(On Diff #56980)

uge -> oge?

899 ↗

(On Diff #56980)

uge -> oge ?

[amehsan]

Thanks CY for the comments on the test cases. I will review to make sure all right combinations are there and function names are consistent. The fast flag on fcmp IR instruction does not matter. We don't pay any attention to it when we construct Selection DAG. It is in my IR because they come from an example that was compiled with -ffast-math.

One of the outstanding issues in SelectionDAGs is that many ISD opcodes are not equipped with fast math flags. For a limited number of opcodes this issue has been fixed, but the work should be extended to all opcodes. While that is the better way of checking for fast math flags, it is a different issue than the what the current patch tries to achieve.

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

4396

Good point. I will rename the function. It makes more sense to check for non-nan outside the function. So even when the function return true, there is a possibility that we do not want to use the new instructions.

[amehsan]

lib/Target/PowerPC/PPC.td

177 ↗

(On Diff #58634)

I think a feature A should not imply feature B that is a superset of A. I had forgot this point and wrote this code incorrectly, but it seems that "implies" part of a SubtargetFeature has been used incorrectly in features around the new one as well. We probably need to discuss this, to make sure we are all on the same page. In the meantime I will change my code here.

[kbarton]

With the exception of a few minor comments, this LGTM.

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

321

Could you please add a brief comment indicating what each field is meant to represent?

533

Please add doxygen-style comments, with a \brief and also the parameters and return values documented.

535

spelling: vairations -> variations

543

Indentation here is off. Is that intentional?

553

Extra blank line here. Please remove.

585

Replace this break with return true, unless there is something else that needs to be done before the return at the end of the function.

593

Replace break with return true.

627

Replace break with return true.

4395

This is not initialized before passing to mayUseP9VSXScalarComparisonInstr.
Is the assumption that all fields will be set inside the mayUseP9VSXScalarComparisonInstr?

[echristo]

A couple of inline comments and one general question: With Nemanjai we've been saying that we didn't want to add subtarget features for every ISA addition of the default ISA, what's with this one? :)

Thanks!

-eric

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

4412–4441

Go ahead and document what's going on in each block here if you wouldn't mind.

lib/Target/PowerPC/PPCISelLowering.cpp

6702

Add a simple comment here would be nice.

[nemanjai]

We have neglected this for a very long time. Just adding a comment to trickle it up to the top of the review queue and I plan to review it very soon.

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

 #include <new>
 #include <tuple>
 #include <utility>
 
 using namespace llvm;
 
 #define DEBUG_TYPE "ppc-codegen"
 
+STATISTIC(NumMinMax, "Number select_cc changed to floating point min/max/cmp.");
 STATISTIC(NumSextSetcc,
           "Number of (sext(setcc)) nodes expanded into GPR sequence.");
 STATISTIC(NumZextSetcc,
           "Number of (zext(setcc)) nodes expanded into GPR sequence.");
 STATISTIC(SignExtensionsAdded,
           "Number of sign extensions for compare inputs added.");
 STATISTIC(ZeroExtensionsAdded,
           "Number of zero extensions for compare inputs added.");
private:
     void foldBoolExts(SDValue &Res, SDNode *&N);
 
     bool AllUsersSelectZero(SDNode *N);
     void SwapAllSelectUsers(SDNode *N);
 
     bool isOffsetMultipleOf(SDNode *N, unsigned Val) const;
     void transferMemOperands(SDNode *N, SDNode *Result);
   };
 
+// The struct below is used by mayUseP9VSXScalarComparisonInstr to summarize
+// information about the SELECT_CC node passed to it.
+struct SelectCCSummary {
+  SDValue Ret0;  // SELECT_CC value to select when condition matches
+  SDValue Ret1;  // SELECT_CC value to select when condition does not match
+  bool IsStrict; // Flag describing whether the condition code is strict
+  SDValue Comp0; // Set to the larger value of the select compare values
+  SDValue Comp1; // Set to the smaller value of the select compare values
+  EVT RetType;   // The return type of the SELECT_CC node
+  bool Leave;    // Flag to state whether this node will be expanded in TableGen
+  ISD::CondCode CC; // The condition code of this SELECT_CC node
+};
 } // end anonymous namespace
 
 /// InsertVRSaveCode - Once the entire function has been instruction selected,
 /// all virtual registers are created and all machine instructions are built,
 /// check to see if we need to save/restore VRSAVE.  If so, do it.
 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
   // Check to see if this function uses vector registers, which means we have to
   // save and restore the VRSAVE register and update it with the regs we use.

 // isOpcWithIntImmediate - This method tests to see if the node is a specific
 // opcode and that it has a immediate integer right operand.
 // If so Imm will receive the 32 bit value.
 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
   return N->getOpcode() == Opc
          && isInt32Immediate(N->getOperand(1).getNode(), Imm);
 }
 
+// This function looks for specific patterns that can be replaced by
+// ISA 3.0 instructions. There are two main pattern sets that we check for.
+// The first set is some vairations of
+// select_cc t5, t6, t2, t4, setogt:ch
+// The key property here is that all first four operands of select_cc are
+// float and double. So we compare FP numbers to select from FP numbers.
+// The second set are variations of
+// t17: i1 = setcc t4, t2, setge:ch
+// t19: i1 = setcc t4, t2, seto:ch
+// t20: i1 = and t17, t19
+// t23: f64 = select_cc t20, Constant:i1<0>, t4, t2, setne:ch
+// Here we also compare FPs to select from FPs, but the comparison is done
+// through a more complicated pattern which is a result of expansion of
+// some condition codes during operation legalization.
+static bool mayUseP9VSXScalarComparisonInstr(SDNode *N,
+                                             SelectCCSummary &Summary) {
+
+  assert((N->getOpcode() == ISD::SELECT_CC) && "Expected SELECT_CC node.");
+
+  if (N->getValueType(0) != MVT::f64 && N->getValueType(0) != MVT::f32)
+    return false;
+
+  Summary.RetType = N->getValueType(0);
+  Summary.Ret0 = N->getOperand(2);
+  Summary.Ret1 = N->getOperand(3);
+
+  ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
+
+  Summary.CC = ISD::CondCode::SETO;
+  Summary.Leave = false;
+  if (N->getOperand(0).getValueType() == MVT::f32 ||
+      N->getOperand(0).getValueType() == MVT::f64) {
+
+    if (CC == ISD::CondCode::SETOEQ || CC == ISD::CondCode::SETEQ) {
+      Summary.Leave = true; // Will handle this in tablegen.
+      return true;
+    }
+
+    Summary.IsStrict = true;
+
+    switch (CC) {
+    case ISD::CondCode::SETNE:
+      Summary.CC = ISD::CondCode::SETNE;
+      std::swap(Summary.Ret0, Summary.Ret1);
+      // fall-through
+    case ISD::CondCode::SETGE:
+      Summary.IsStrict = false;
+      // fall-through
+    case ISD::CondCode::SETOGT:
+    case ISD::CondCode::SETGT:
+      Summary.Comp0 = N->getOperand(0);
+      Summary.Comp1 = N->getOperand(1);
+      return true;
+    case ISD::CondCode::SETLE:
+      Summary.IsStrict = false;
+      // fall-through
+    case ISD::CondCode::SETOLT:
+    case ISD::CondCode::SETLT:
+      Summary.Comp0 = N->getOperand(1);
+      Summary.Comp1 = N->getOperand(0);
+      return true;
+    default:
+      return false;
+    }
+  } else if (N->getOperand(0).getValueType() == MVT::i1) {
+    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1));
+    if (!N1C || !N1C->getConstantIntValue()->isZero() ||
+        N->getOperand(0).getOpcode() != ISD::AND ||
+        N->getOperand(0).getOperand(0).getOpcode() != ISD::SETCC ||
+        N->getOperand(0).getOperand(1).getOpcode() != ISD::SETCC)
+      return false;
+
+    ISD::CondCode CC1 =
+        cast<CondCodeSDNode>(N->getOperand(0).getOperand(1).getOperand(2))
+            ->get();
+
+    if (CC1 != ISD::CondCode::SETO)
+      return false;
+
+    ISD::CondCode CC0 =
+        cast<CondCodeSDNode>(N->getOperand(0).getOperand(0).getOperand(2))
+            ->get();
+
+    Summary.IsStrict = false;
+    switch (CC0) {
+    case ISD::CondCode::SETNE:
+      Summary.CC = ISD::CondCode::SETNE;
+      std::swap(Summary.Ret0, Summary.Ret1);
+      // fall-through
+    case ISD::CondCode::SETGE:
+      Summary.Comp0 = N->getOperand(0).getOperand(0).getOperand(0);
+      Summary.Comp1 = N->getOperand(0).getOperand(0).getOperand(1);
+      return true;
+    case ISD::CondCode::SETLE:
+      Summary.Comp0 = N->getOperand(0).getOperand(0).getOperand(1);
+      Summary.Comp1 = N->getOperand(0).getOperand(0).getOperand(0);
+      return true;
+    default:
+      return false;
+    }
+  } else
+    return false;
+}
+
 void PPCDAGToDAGISel::selectFrameIndex(SDNode *SN, SDNode *N, unsigned Offset) {
   SDLoc dl(SN);
   int FI = cast<FrameIndexSDNode>(N)->getIndex();
   SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
   unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
   if (SN->hasOneUse())
     CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI,
                          getSmallIPtrImm(Offset, dl));
case PPCISD::ANDIo_1_GT_BIT: {
     SDValue SRIdxVal =
       CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
                                 PPC::sub_eq : PPC::sub_gt, dl, MVT::i32);
 
     CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1, CR0Reg,
                          SRIdxVal, SDValue(AndI.getNode(), 1) /* glue */);
     return;
   }
+
   case ISD::SELECT_CC: {
+    if (PPCSubTarget->hasP9Vector()) {
+      SelectCCSummary Summary;
+      if (mayUseP9VSXScalarComparisonInstr(N, Summary)) {
+        if (Summary.Leave)
+          break; // Will be handled in tablegen.
+
+        NumMinMax++;
+        unsigned SelectOpcode =
+            (Summary.RetType == MVT::f32) ? PPC::XXSEL_SP : PPC::XXSEL_DP;
+        // Check for selects which can be transformed to compare equal
+        if (Summary.CC == ISD::CondCode::SETNE) {
+          unsigned CmpOpcode = (Summary.Comp0->getValueType(0) == MVT::f32)
+                                   ? PPC::XSCMPEQDP_SP
+                                   : PPC::XSCMPEQDP;
+
+          SDNode *mask = CurDAG->getMachineNode(CmpOpcode, dl, MVT::v2i64,
+                                                Summary.Comp0, Summary.Comp1);
+          CurDAG->SelectNodeTo(N, SelectOpcode, Summary.RetType, Summary.Ret1,
+                               Summary.Ret0, SDValue(mask, 0));
+          return;
+        }
+        // Check for selects which can be transformed to MAX
+        if (Summary.Comp0 == Summary.Ret0 && Summary.Comp1 == Summary.Ret1) {
+          unsigned MaxOpcode =
+              (Summary.RetType == MVT::f32) ? PPC::XSMAXCDP_SP : PPC::XSMAXCDP;
+          CurDAG->SelectNodeTo(N, MaxOpcode, Summary.RetType, Summary.Ret0,
+                               Summary.Ret1);
+          return;
+        }
+        // Check for selects which can be transformed to MIN
+        else if (Summary.Comp0 == Summary.Ret1 &&
+                 Summary.Comp1 == Summary.Ret0) {
+          unsigned MinOpcode =
+              (Summary.RetType == MVT::f32) ? PPC::XSMINCDP_SP : PPC::XSMINCDP;
+          CurDAG->SelectNodeTo(N, MinOpcode, Summary.RetType, Summary.Ret0,
+                               Summary.Ret1);
+          return;
+        } else if (CurDAG->getTarget().Options.NoNaNsFPMath) {
+          // Check for select of 2 floating points based on comparison of 2
+          // different floating points.
+          SDNode *mask = nullptr;
+          if (Summary.IsStrict) {
+            unsigned CmpOpcode = (Summary.Comp0->getValueType(0) == MVT::f32)
+                                     ? PPC::XSCMPGTDP_SP
+                                     : PPC::XSCMPGTDP;
+            mask = CurDAG->getMachineNode(CmpOpcode, dl, MVT::v2i64,
+                                          Summary.Comp0, Summary.Comp1);
+          } else {
+            unsigned CmpOpcode = (Summary.Comp0->getValueType(0) == MVT::f32)
+                                     ? PPC::XSCMPGEDP_SP
+                                     : PPC::XSCMPGEDP;
+            mask = CurDAG->getMachineNode(CmpOpcode, dl, MVT::v2i64,
+                                          Summary.Comp0, Summary.Comp1);
+          }
+          CurDAG->SelectNodeTo(N, SelectOpcode, Summary.RetType, Summary.Ret1,
+                               Summary.Ret0, SDValue(mask, 0));
+          return;
+        }
+      }
+    }
     ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
     EVT PtrVT =
         CurDAG->getTargetLoweringInfo().getPointerTy(CurDAG->getDataLayout());
     bool isPPC64 = (PtrVT == MVT::i64);
 
     // If this is a select of i1 operands, we'll pattern match it.
     if (PPCSubTarget->useCRBits() &&
         N->getOperand(0).getValueType() == MVT::i1)

lib/Target/PowerPC/PPCISelLowering.cpp

SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
   SDLoc DL(Op);
   return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
                      Op.getOperand(0));
 }
 
 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
 /// possible.
 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
+  // We have floating point min/max and compare instructions that we can use for
+  // power9.
+  if (Subtarget.hasP9Vector())
+    return Op;
+
   // Not FP? Not a fsel.
   if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
       !Op.getOperand(2).getValueType().isFloatingPoint())
     return Op;
 
   // We might be able to do better than this under some circumstances, but in
   // general, fsel-based lowering of select is a finite-math-only optimization.
   // For more information, see section F.3 of the 2.06 ISA specification.

lib/Target/PowerPC/PPCInstrVSX.td

def XXPERMDI : XX3Form_2<60, 10,
                        [(set v2i64:$XT, (PPCxxpermdi v2i64:$XA, v2i64:$XB,
                          imm32SExt16:$DM))]>;
   let isCodeGenOnly = 1 in
   def XXPERMDIs : XX3Form_2s<60, 10, (outs vsrc:$XT), (ins vsfrc:$XA, u2imm:$DM),
                              "xxpermdi $XT, $XA, $XA, $DM", IIC_VecPerm, []>;
   def XXSEL : XX4Form<60, 3,
                       (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, vsrc:$XC),
                       "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>;
+  let isCodeGenOnly = 1 in {
+    def XXSEL_DP : XX4Form<60, 3,
+                           (outs vsfrc:$XT), (ins vsfrc:$XA, vsfrc:$XB, vsrc:$XC),
+                           "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>;
+    def XXSEL_SP : XX4Form<60, 3,
+                           (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB, vsrc:$XC),
+                           "xxsel $XT, $XA, $XB, $XC", IIC_VecPerm, []>;
+  }
 
   def XXSLDWI : XX3Form_2<60, 2,
                        (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB, u2imm:$SHW),
                        "xxsldwi $XT, $XA, $XB, $SHW", IIC_VecPerm,
                        [(set v4i32:$XT, (PPCvecshl v4i32:$XA, v4i32:$XB,
                                                   imm32SExt16:$SHW))]>;
   def XXSPLTW : XX2Form_2<60, 164,
                        (outs vsrc:$XT), (ins vsrc:$XB, u2imm:$UIM),
let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   def XSCMPEQDP : XX3_XT5_XA5_XB5<60,  3, "xscmpeqdp", vsrc, vsfrc, vsfrc,
                                   IIC_FPCompare, []>;
   def XSCMPGEDP : XX3_XT5_XA5_XB5<60, 19, "xscmpgedp", vsrc, vsfrc, vsfrc,
                                   IIC_FPCompare, []>;
   def XSCMPGTDP : XX3_XT5_XA5_XB5<60, 11, "xscmpgtdp", vsrc, vsfrc, vsfrc,
                                   IIC_FPCompare, []>;
   def XSCMPNEDP : XX3_XT5_XA5_XB5<60, 27, "xscmpnedp", vsrc, vsfrc, vsfrc,
                                   IIC_FPCompare, []>;
+
+  let isCodeGenOnly = 1 in {
+    def XSCMPEQDP_SP : XX3_XT5_XA5_XB5<60,  3, "xscmpeqdp", vsrc, vssrc, vssrc,
+                                       IIC_FPCompare, []>;
+    def XSCMPGEDP_SP : XX3_XT5_XA5_XB5<60, 19, "xscmpgedp", vsrc, vssrc, vssrc,
+                                       IIC_FPCompare, []>;
+    def XSCMPGTDP_SP : XX3_XT5_XA5_XB5<60, 11, "xscmpgtdp", vsrc, vssrc, vssrc,
+                                       IIC_FPCompare, []>;
+  }
+
+  def : Pat <(f64 (selectcc f64:$XC, f64:$XD, f64:$XA, f64:$XB, SETOEQ )),
+             (XXSEL_DP $XB, $XA, (XSCMPEQDP $XC, $XD))>;
+
+  def : Pat <(f64 (selectcc f64:$XC, f64:$XD, f64:$XA, f64:$XB, SETEQ )),
+             (XXSEL_DP $XB, $XA, (XSCMPEQDP $XC, $XD))>;
+
+  def : Pat <(f32 (selectcc f32:$XC, f32:$XD, f32:$XA, f32:$XB, SETOEQ )),
+             (XXSEL_SP $XB, $XA, (XSCMPEQDP_SP $XC, $XD))>;
+
+  def : Pat <(f32 (selectcc f32:$XC, f32:$XD, f32:$XA, f32:$XB, SETEQ )),
+             (XXSEL_SP $XB, $XA, (XSCMPEQDP_SP $XC, $XD))>;
+
+  def : Pat <(f64 (selectcc f32:$XC, f32:$XD, f64:$XA, f64:$XB, SETOEQ )),
+             (XXSEL_DP $XB, $XA, (XSCMPEQDP_SP $XC, $XD))>;
+
+  def : Pat <(f64 (selectcc f32:$XC, f32:$XD, f64:$XA, f64:$XB, SETEQ )),
+             (XXSEL_DP $XB, $XA, (XSCMPEQDP_SP $XC, $XD))>;
+
+  def : Pat <(f32 (selectcc f64:$XC, f64:$XD, f32:$XA, f32:$XB, SETOEQ )),
+             (XXSEL_SP $XB, $XA, (XSCMPEQDP $XC, $XD))>;
+
+  def : Pat <(f32 (selectcc f64:$XC, f64:$XD, f32:$XA, f32:$XB, SETEQ )),
+             (XXSEL_SP $XB, $XA, (XSCMPEQDP $XC, $XD))>;
+
   let UseVSXReg = 1 in {
   // Vector Compare Not Equal
   def XVCMPNEDP  : XX3Form_Rc<60, 123,
                               (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
                               "xvcmpnedp  $XT, $XA, $XB", IIC_VecFPCompare, []>;
   let Defs = [CR6] in
   def XVCMPNEDPo : XX3Form_Rc<60, 123,
                               (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
def XVTSTDCDP : XX2_RD6_DCMX7_RS6<60, 15, 5,
                               [(set v2i64: $XT,
                                (int_ppc_vsx_xvtstdcdp v2f64:$XB, imm:$DCMX))]>;
   } // UseVSXReg = 1
 
   //===--------------------------------------------------------------------===//
 
   // Maximum/Minimum Type-C/Type-J DP
   // XT.dword[1] = 0xUUUU_UUUU_UUUU_UUUU, so we use vsrc for XT
-  def XSMAXCDP : XX3_XT5_XA5_XB5<60, 128, "xsmaxcdp", vsrc, vsfrc, vsfrc,
+  def XSMAXCDP : XX3_XT5_XA5_XB5<60, 128, "xsmaxcdp", vsfrc, vsfrc, vsfrc,
                                  IIC_VecFP, []>;
   def XSMAXJDP : XX3_XT5_XA5_XB5<60, 144, "xsmaxjdp", vsrc, vsfrc, vsfrc,
                                  IIC_VecFP, []>;
-  def XSMINCDP : XX3_XT5_XA5_XB5<60, 136, "xsmincdp", vsrc, vsfrc, vsfrc,
+  def XSMINCDP : XX3_XT5_XA5_XB5<60, 136, "xsmincdp", vsfrc, vsfrc, vsfrc,
                                  IIC_VecFP, []>;
   def XSMINJDP : XX3_XT5_XA5_XB5<60, 152, "xsminjdp", vsrc, vsfrc, vsfrc,
                                  IIC_VecFP, []>;
 
+  let isCodeGenOnly = 1 in {
+    def XSMAXCDP_SP : XX3_XT5_XA5_XB5<60, 128, "xsmaxcdp", vssrc, vssrc, vssrc,
+                                   IIC_VecFP, []>;
+    def XSMAXJDP_SP : XX3_XT5_XA5_XB5<60, 144, "xsmaxjdp", vsrc, vssrc, vssrc,
+                                   IIC_VecFP, []>;
+    def XSMINCDP_SP : XX3_XT5_XA5_XB5<60, 136, "xsmincdp", vssrc, vssrc, vssrc,
+                                   IIC_VecFP, []>;
+    def XSMINJDP_SP : XX3_XT5_XA5_XB5<60, 152, "xsminjdp", vsrc, vssrc, vssrc,
+                                   IIC_VecFP, []>;
+  }
+
   //===--------------------------------------------------------------------===//
 
   // Vector Byte-Reverse H/W/D/Q Word
   def XXBRH : XX2_XT6_XO5_XB6<60,  7, 475, "xxbrh", vsrc, []>;
   def XXBRW : XX2_XT6_XO5_XB6<60, 15, 475, "xxbrw", vsrc, []>;
   def XXBRD : XX2_XT6_XO5_XB6<60, 23, 475, "xxbrd", vsrc, []>;
   def XXBRQ : XX2_XT6_XO5_XB6<60, 31, 475, "xxbrq", vsrc, []>;
 

test/CodeGen/PowerPC/vsx-p9-maxmin.ll

+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck --check-prefix DISABLED %s
+
+attributes #1 = {"no-nans-fp-math"="true"}
+
+attributes #2 = {"no-nans-fp-math"="false"}
+
+; This file contains a total of 104 tests in three different parts. Each part
+; starts with a comment describing combinations of tests covered. First part
+; has 64 tests. Second part has 32 tests. Last part includes 8 tests.
+; The second test for disabled case is done only once for each instruction
+
+; There are 64 testcases for max/min. 2 data types (float, double),
+; 8 condition codes, 2 operations (max, min), 2 no-nan status (#1, #2).
+
+define double @max_test1(double %x, double %y) #1 {
+
+; CHECK-LABEL: @max_test1
+; DISABLED-LABEL: @max_test1
+
+entry:
+  %cmp = fcmp ogt double %x, %y
+  %x.y = select i1 %cmp, double %x, double %y
+  ret double %x.y
+
+; CHECK: xsmaxcdp 1, 1, 2
+; DISABLED-NOT: xsmaxcdp
+; CHECK: blr
+; DISABLED: blr
+
+}
+
+define double @max_test2(double %x, double %y) #1 {
+
+; CHECK-LABEL: @max_test2
+
+entry:
+  %cmp = fcmp olt double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK: xsmaxcdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define double @min_test1(double %x, double %y) #1 {
+
+; CHECK-LABEL: @min_test1
+
+entry:
+  %cmp = fcmp ogt double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK: xsmincdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define double @min_test2(double %x, double %y) #1 {
+
+; CHECK-LABEL: @min_test2
+; DISABLED-LABEL: @min_test2
+
+entry:
+  %cmp = fcmp olt double %x, %y
+  %x.y = select i1 %cmp, double %x, double %y
+  ret double %x.y
+
+; CHECK: xsmincdp 1, 1, 2
+; DISABLED-NOT: xsmincdp
+; CHECK: blr
+; DISABLED: blr
+
+}
+
+define float @max_test1_float(float %x, float %y) #1 {
+
+; CHECK-LABEL: @max_test1_float
+
+entry:
+  %cmp = fcmp ogt float %x, %y
+  %x.y = select i1 %cmp, float %x, float %y
+  ret float %x.y
+
+; CHECK: xsmaxcdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define float @max_test2_float(float %x, float %y) #1 {
+
+; CHECK-LABEL: @max_test2_float
+
+entry:
+  %cmp = fcmp olt float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK: xsmaxcdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define float @min_test1_float(float %x, float %y) #1 {
+
+; CHECK-LABEL: @min_test1_float
+
+entry:
+  %cmp = fcmp ogt float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK: xsmincdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define float @min_test2_float(float %x, float %y) #1 {
+
+; CHECK-LABEL: @min_test2_float
+
+entry:
+  %cmp = fcmp olt float %x, %y
+  %x.y = select i1 %cmp, float %x, float %y
+  ret float %x.y
+
+; CHECK: xsmincdp 1, 1, 2
+; CHECK: blr
+
+}
+
+
+define double @max_test1_eq(double %x, double %y) #1 {
+
+; CHECK-LABEL: @max_test1_eq
+
+entry:
+  %cmp = fcmp oge double %x, %y
+  %x.y = select i1 %cmp, double %x, double %y
+  ret double %x.y
+
+; CHECK: xsmaxcdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define double @max_test2_eq(double %x, double %y) #1 {
+
+; CHECK-LABEL: @max_test2_eq
+
+entry:
+  %cmp = fcmp ole double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK: xsmaxcdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define double @min_test1_eq(double %x, double %y) #1 {
+
+; CHECK-LABEL: @min_test1_eq
+
+entry:
+  %cmp = fcmp oge double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK: xsmincdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define double @min_test2_eq(double %x, double %y) #1 {
+
+; CHECK-LABEL: @min_test2_eq
+
+entry:
+  %cmp = fcmp ole double %x, %y
+  %x.y = select i1 %cmp, double %x, double %y
+  ret double %x.y
+
+; CHECK: xsmincdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define float @max_test1_float_eq(float %x, float %y) #1 {
+
+; CHECK-LABEL: @max_test1_float_eq
+
+entry:
+  %cmp = fcmp oge float %x, %y
+  %x.y = select i1 %cmp, float %x, float %y
+  ret float %x.y
+
+; CHECK: xsmaxcdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define float @max_test2_float_eq(float %x, float %y) #1 {
+
+; CHECK-LABEL: @max_test2_float_eq
+
+entry:
+  %cmp = fcmp ole float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK: xsmaxcdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define float @min_test1_float_eq(float %x, float %y) #1 {
+
+; CHECK-LABEL: @min_test1_float_eq
+
+entry:
+  %cmp = fcmp oge float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK: xsmincdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define float @min_test2_float_eq(float %x, float %y) #1 {
+
+; CHECK-LABEL: @min_test2_float_eq
+
+entry:
+  %cmp = fcmp ole float %x, %y
+  %x.y = select i1 %cmp, float %x, float %y
+  ret float %x.y
+
+; CHECK: xsmincdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define double @nan_max_test1(double %x, double %y) #2 {
+
+; CHECK-LABEL: @nan_max_test1
+
+entry:
+  %cmp = fcmp ogt double %x, %y
+  %x.y = select i1 %cmp, double %x, double %y
+  ret double %x.y
+
+; CHECK: xsmaxcdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define double @nan_max_test2(double %x, double %y) #2 {
+
+; CHECK-LABEL: @nan_max_test2
+
+entry:
+  %cmp = fcmp olt double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK: xsmaxcdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define double @nan_min_test1(double %x, double %y) #2 {
+
+; CHECK-LABEL: @nan_min_test1
+
+entry:
+  %cmp = fcmp ogt double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK: xsmincdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define double @nan_min_test2(double %x, double %y) #2 {
+
+; CHECK-LABEL: @nan_min_test2
+
+entry:
+  %cmp = fcmp olt double %x, %y
+  %x.y = select i1 %cmp, double %x, double %y
+  ret double %x.y
+
+; CHECK: xsmincdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define float @nan_max_test1_float(float %x, float %y) #2 {
+
+; CHECK-LABEL: @nan_max_test1_float
+
+entry:
+  %cmp = fcmp ogt float %x, %y
+  %x.y = select i1 %cmp, float %x, float %y
+  ret float %x.y
+
+; CHECK: xsmaxcdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define float @nan_max_test2_float(float %x, float %y) #2 {
+
+; CHECK-LABEL: @nan_max_test2_float
+
+entry:
+  %cmp = fcmp olt float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK: xsmaxcdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define float @nan_min_test1_float(float %x, float %y) #2 {
+
+; CHECK-LABEL: @nan_min_test1_float
+
+entry:
+  %cmp = fcmp ogt float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK: xsmincdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define float @nan_min_test2_float(float %x, float %y) #2 {
+
+; CHECK-LABEL: @nan_min_test2_float
+
+entry:
+  %cmp = fcmp olt float %x, %y
+  %x.y = select i1 %cmp, float %x, float %y
+  ret float %x.y
+
+; CHECK: xsmincdp 1, 1, 2
+; CHECK: blr
+
+}
+
+
+define double @nan_max_test1_eq(double %x, double %y) #2 {
+
+; CHECK-LABEL: @nan_max_test1_eq
+
+entry:
+  %cmp = fcmp oge double %x, %y
+  %x.y = select i1 %cmp, double %x, double %y
+  ret double %x.y
+
+; CHECK: xsmaxcdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define double @nan_max_test2_eq(double %x, double %y) #2 {
+
+; CHECK-LABEL: @nan_max_test2_eq
+
+entry:
+  %cmp = fcmp ole double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK: xsmaxcdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define double @nan_min_test1_eq(double %x, double %y) #2 {
+
+; CHECK-LABEL: @nan_min_test1_eq
+
+entry:
+  %cmp = fcmp oge double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK: xsmincdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define double @nan_min_test2_eq(double %x, double %y) #2 {
+
+; CHECK-LABEL: @nan_min_test2_eq
+
+entry:
+  %cmp = fcmp ole double %x, %y
+  %x.y = select i1 %cmp, double %x, double %y
+  ret double %x.y
+
+; CHECK: xsmincdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define float @nan_max_test1_float_eq(float %x, float %y) #2 {
+
+; CHECK-LABEL: @nan_max_test1_float_eq
+
+entry:
+  %cmp = fcmp oge float %x, %y
+  %x.y = select i1 %cmp, float %x, float %y
+  ret float %x.y
+
+; CHECK: xsmaxcdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define float @nan_max_test2_float_eq(float %x, float %y) #2 {
+
+; CHECK-LABEL: @nan_max_test2_float_eq
+
+entry:
+  %cmp = fcmp ole float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK: xsmaxcdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define float @nan_min_test1_float_eq(float %x, float %y) #2 {
+
+; CHECK-LABEL: @nan_min_test1_float_eq
+
+entry:
+  %cmp = fcmp oge float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK: xsmincdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define float @nan_min_test2_float_eq(float %x, float %y) #2 {
+
+; CHECK-LABEL: @nan_min_test2_float_eq
+
+entry:
+  %cmp = fcmp ole float %x, %y
+  %x.y = select i1 %cmp, float %x, float %y
+  ret float %x.y
+
+; CHECK: xsmincdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define double @max_test1_unordered(double %x, double %y) #1 {
+
+; CHECK-LABEL: @max_test1_unordered
+
+entry:
+  %cmp = fcmp ugt double %x, %y
+  %x.y = select i1 %cmp, double %x, double %y
+  ret double %x.y
+
+; CHECK: xsmaxcdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define double @max_test2_unordered(double %x, double %y) #1 {
+
+; CHECK-LABEL: @max_test2_unordered
+
+entry:
+  %cmp = fcmp ult double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK: xsmaxcdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define double @min_test1_unordered(double %x, double %y) #1 {
+
+; CHECK-LABEL: @min_test1_unordered
+
+entry:
+  %cmp = fcmp ugt double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK: xsmincdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define double @min_test2_unordered(double %x, double %y) #1 {
+
+; CHECK-LABEL: @min_test2_unordered
+
+entry:
+  %cmp = fcmp ult double %x, %y
+  %x.y = select i1 %cmp, double %x, double %y
+  ret double %x.y
+
+; CHECK: xsmincdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define float @max_test1_float_unordered(float %x, float %y) #1 {
+
+; CHECK-LABEL: @max_test1_float_unordered
+
+entry:
+  %cmp = fcmp ugt float %x, %y
+  %x.y = select i1 %cmp, float %x, float %y
+  ret float %x.y
+
+; CHECK: xsmaxcdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define float @max_test2_float_unordered(float %x, float %y) #1 {
+
+; CHECK-LABEL: @max_test2_float_unordered
+
+entry:
+  %cmp = fcmp ult float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK: xsmaxcdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define float @min_test1_float_unordered(float %x, float %y) #1 {
+
+; CHECK-LABEL: @min_test1_float_unordered
+
+entry:
+  %cmp = fcmp ugt float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK: xsmincdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define float @min_test2_float_unordered(float %x, float %y) #1 {
+
+; CHECK-LABEL: @min_test2_float_unordered
+
+entry:
+  %cmp = fcmp ult float %x, %y
+  %x.y = select i1 %cmp, float %x, float %y
+  ret float %x.y
+
+; CHECK: xsmincdp 1, 1, 2
+; CHECK: blr
+
+}
+
+
+define double @max_test1_eq_unordered(double %x, double %y) #1 {
+
+; CHECK-LABEL: @max_test1_eq_unordered
+
+entry:
+  %cmp = fcmp uge double %x, %y
+  %x.y = select i1 %cmp, double %x, double %y
+  ret double %x.y
+
+; CHECK: xsmaxcdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define double @max_test2_eq_unordered(double %x, double %y) #1 {
+
+; CHECK-LABEL: @max_test2_eq_unordered
+
+entry:
+  %cmp = fcmp ule double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK: xsmaxcdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define double @min_test1_eq_unordered(double %x, double %y) #1 {
+
+; CHECK-LABEL: @min_test1_eq_unordered
+
+entry:
+  %cmp = fcmp uge double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK: xsmincdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define double @min_test2_eq_unordered(double %x, double %y) #1 {
+
+; CHECK-LABEL: @min_test2_eq_unordered
+
+entry:
+  %cmp = fcmp ule double %x, %y
+  %x.y = select i1 %cmp, double %x, double %y
+  ret double %x.y
+
+; CHECK: xsmincdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define float @max_test1_float_eq_unordered(float %x, float %y) #1 {
+
+; CHECK-LABEL: @max_test1_float_eq_unordered
+
+entry:
+  %cmp = fcmp uge float %x, %y
+  %x.y = select i1 %cmp, float %x, float %y
+  ret float %x.y
+
+; CHECK: xsmaxcdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define float @max_test2_float_eq_unordered(float %x, float %y) #1 {
+
+; CHECK-LABEL: @max_test2_float_eq_unordered
+
+entry:
+  %cmp = fcmp ule float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK: xsmaxcdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define float @min_test1_float_eq_unordered(float %x, float %y) #1 {
+
+; CHECK-LABEL: @min_test1_float_eq_unordered
+
+entry:
+  %cmp = fcmp uge float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK: xsmincdp 1, 2, 1
+; CHECK: blr
+
+}
+
+define float @min_test2_float_eq_unordered(float %x, float %y) #1 {
+
+; CHECK-LABEL: @min_test2_float_eq_unordered
+
+entry:
+  %cmp = fcmp ule float %x, %y
+  %x.y = select i1 %cmp, float %x, float %y
+  ret float %x.y
+
+; CHECK: xsmincdp 1, 1, 2
+; CHECK: blr
+
+}
+
+define double @max_test1_unordered_nan(double %x, double %y) #2 {
+
+; CHECK-LABEL: @max_test1_unordered_nan
+
+entry:
+  %cmp = fcmp ugt double %x, %y
+  %x.y = select i1 %cmp, double %x, double %y
+  ret double %x.y
+
+; CHECK-NOT: xsmaxcdp
+; CHECK: blr
+
+}
+
+define double @max_test2_unordered_nan(double %x, double %y) #2 {
+
+; CHECK-LABEL: @max_test2_unordered_nan
+
+entry:
+  %cmp = fcmp ult double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK-NOT: xsmaxcdp
+; CHECK: blr
+
+}
+
+define double @min_test1_unordered_nan(double %x, double %y) #2 {
+
+; CHECK-LABEL: @min_test1_unordered_nan
+
+entry:
+  %cmp = fcmp ugt double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK-NOT: xsmincdp
+; CHECK: blr
+
+}
+
+define double @min_test2_unordered_nan(double %x, double %y) #2 {
+
+; CHECK-LABEL: @min_test2_unordered_nan
+
+entry:
+  %cmp = fcmp ult double %x, %y
+  %x.y = select i1 %cmp, double %x, double %y
+  ret double %x.y
+
+; CHECK-NOT: xsmincdp
+; CHECK: blr
+
+}
+
+define float @max_test1_float_unordered_nan(float %x, float %y) #2 {
+
+; CHECK-LABEL: @max_test1_float_unordered_nan
+
+entry:
+  %cmp = fcmp ugt float %x, %y
+  %x.y = select i1 %cmp, float %x, float %y
+  ret float %x.y
+
+; CHECK-NOT: xsmaxcdp
+; CHECK: blr
+
+}
+
+define float @max_test2_float_unordered_nan(float %x, float %y) #2 {
+
+; CHECK-LABEL: @max_test2_float_unordered_nan
+
+entry:
+  %cmp = fcmp ult float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK-NOT: xsmaxcdp
+; CHECK: blr
+
+}
+
+define float @min_test1_float_unordered_nan(float %x, float %y) #2 {
+
+; CHECK-LABEL: @min_test1_float_unordered_nan
+
+entry:
+  %cmp = fcmp ugt float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK-NOT: xsmincdp
+; CHECK: blr
+
+}
+
+define float @min_test2_float_unordered_nan(float %x, float %y) #2 {
+
+; CHECK-LABEL: @min_test2_float_unordered_nan
+
+entry:
+  %cmp = fcmp ult float %x, %y
+  %x.y = select i1 %cmp, float %x, float %y
+  ret float %x.y
+
+; CHECK-NOT: xsmincdp
+; CHECK: blr
+
+}
+
+define double @max_test1_eq_unordered_nan(double %x, double %y) #2 {
+
+; CHECK-LABEL: @max_test1_eq_unordered_nan
+
+entry:
+  %cmp = fcmp uge double %x, %y
+  %x.y = select i1 %cmp, double %x, double %y
+  ret double %x.y
+
+; CHECK-NOT: xsmaxcdp
+; CHECK: blr
+
+}
+
+define double @max_test2_eq_unordered_nan(double %x, double %y) #2 {
+
+; CHECK-LABEL: @max_test2_eq_unordered_nan
+
+entry:
+  %cmp = fcmp ule double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK-NOT: xsmaxcdp
+; CHECK: blr
+
+}
+
+define double @min_test1_eq_unordered_nan(double %x, double %y) #2 {
+
+; CHECK-LABEL: @min_test1_eq_unordered_nan
+
+entry:
+  %cmp = fcmp uge double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK-NOT: xsmincdp
+; CHECK: blr
+
+}
+
+define double @min_test2_eq_unordered_nan(double %x, double %y) #2 {
+
+; CHECK-LABEL: @min_test2_eq_unordered_nan
+
+entry:
+  %cmp = fcmp ule double %x, %y
+  %x.y = select i1 %cmp, double %x, double %y
+  ret double %x.y
+
+; CHECK-NOT: xsmincdp
+; CHECK: blr
+
+}
+
+define float @max_test1_float_eq_unordered_nan(float %x, float %y) #2 {
+
+; CHECK-LABEL: @max_test1_float_eq_unordered_nan
+
+entry:
+  %cmp = fcmp uge float %x, %y
+  %x.y = select i1 %cmp, float %x, float %y
+  ret float %x.y
+
+; CHECK-NOT: xsmaxcdp
+; CHECK: blr
+
+}
+
+define float @max_test2_float_eq_unordered_nan(float %x, float %y) #2 {
+
+; CHECK-LABEL: @max_test2_float_eq_unordered_nan
+
+entry:
+  %cmp = fcmp ule float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK-NOT: xsmaxcdp
+; CHECK: blr
+
+}
+
+define float @min_test1_float_eq_unordered_nan(float %x, float %y) #2 {
+
+; CHECK-LABEL: @min_test1_float_eq_unordered_nan
+
+entry:
+  %cmp = fcmp uge float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK-NOT: xsmincdp
+; CHECK: blr
+
+}
+
+define float @min_test2_float_eq_unordered_nan(float %x, float %y) #2 {
+
+; CHECK-LABEL: @min_test2_float_eq_unordered_nan
+
+entry:
+  %cmp = fcmp ule float %x, %y
+  %x.y = select i1 %cmp, float %x, float %y
+  ret float %x.y
+
+; CHECK-NOT: xsmincdp
+; CHECK: blr
+
+}
+
+; 32 more tests for the following combinations: 2 data types (float, double)
+; 8 condition codes, and 2 non-status (#1, #2).
+
+define double @fast_double_ugt(double %x, double %y, double %a, double %b) #1 {
+
+; CHECK-LABEL: @fast_double_ugt
+; DISABLED-LABEL: @fast_double_ugt
+
+entry:
+  %cmp = fcmp fast ugt double %y, %x
+  %b.a = select i1 %cmp, double %b, double %a
+  ret double %b.a
+
+; CHECK: xscmpgtdp [[MASK:[0-9]+]], 2, 1
+; CHECK: xxsel 1, 3, 4, [[MASK]]
+; CHECK: blr
+; DISABLED-NOT: xscmpgtdp
+; DISABLED: blr
+
+}
+
+define double @nan_double_ugt(double %x, double %y, double %a, double %b) #2 {
+
+; CHECK-LABEL: @nan_double_ugt
+
+entry:
+  %cmp = fcmp fast ugt double %y, %x
+  %b.a = select i1 %cmp, double %b, double %a
+  ret double %b.a
+
+; CHECK-NOT: xscmpgtdp
+; CHECK-NOT: xscmpgedp
+; CHECK: blr
+
+}
+
+define double @fast_double_ult(double %x, double %y, double %a, double %b) #1 {
+
+; CHECK-LABEL: @fast_double_ult
+
+entry:
+  %cmp = fcmp fast ult double %y, %x
+  %b.a = select i1 %cmp, double %b, double %a
+  ret double %b.a
+
+; CHECK: xscmpgtdp [[MASK:[0-9]+]], 1, 2
+; CHECK: xxsel 1, 3, 4, [[MASK]]
+; CHECK: blr
+
+}
+
+define double @nan_double_ult(double %x, double %y, double %a, double %b) #2 {
+
+; CHECK-LABEL: @nan_double_ult
+
+entry:
+  %cmp = fcmp fast ult double %y, %x
+  %b.a = select i1 %cmp, double %b, double %a
+  ret double %b.a
+
+; CHECK-NOT: xscmpgtdp
+; CHECK-NOT: xscmpgedp
+; CHECK: blr
+
+}
+
+define double @fast_double_ogt(double %x, double %y, double %a, double %b) #1 {
+
+; CHECK-LABEL: @fast_double_ogt
+
+entry:
+  %cmp = fcmp fast ogt double %y, %x
+  %b.a = select i1 %cmp, double %b, double %a
+  ret double %b.a
+
+; CHECK: xscmpgtdp [[MASK:[0-9]+]], 2, 1
+; CHECK: xxsel 1, 3, 4, [[MASK]]
+; CHECK: blr
+
+}
+
+define double @nan_double_ogt(double %x, double %y, double %a, double %b) #2 {
+
+; CHECK-LABEL: @nan_double_ogt
+
+entry:
+  %cmp = fcmp fast ogt double %y, %x
+  %b.a = select i1 %cmp, double %b, double %a
+  ret double %b.a
+
+; CHECK-NOT: xscmpgtdp
+; CHECK-NOT: xscmpgedp
+; CHECK: blr
+
+}
+
+define double @fast_double_olt(double %x, double %y, double %a, double %b) #1 {
+
+; CHECK-LABEL: @fast_double_olt
+
+entry:
+  %cmp = fcmp fast olt double %y, %x
+  %b.a = select i1 %cmp, double %b, double %a
+  ret double %b.a
+
+; CHECK: xscmpgtdp [[MASK:[0-9]+]], 1, 2
+; CHECK: xxsel 1, 3, 4, [[MASK]]
+; CHECK: blr
+
+}
+
+define double @nan_double_olt(double %x, double %y, double %a, double %b) #2 {
+
+; CHECK-LABEL: @nan_double_olt
+
+entry:
+  %cmp = fcmp fast olt double %y, %x
+  %b.a = select i1 %cmp, double %b, double %a
+  ret double %b.a
+
+; CHECK-NOT: xscmpgtdp
+; CHECK-NOT: xscmpgedp
+; CHECK: blr
+
+}
+
+define float @fast_float_ugt(float %x, float %y, float %a, float %b) #1 {
+
+; CHECK-LABEL: @fast_float_ugt
+
+entry:
+  %cmp = fcmp fast ugt float %y, %x
+  %b.a = select i1 %cmp, float %b, float %a
+  ret float %b.a
+
+; CHECK: xscmpgtdp [[MASK:[0-9]+]], 2, 1
+; CHECK: xxsel 1, 3, 4, [[MASK]]
+; CHECK: blr
+
+}
+
+define float @nan_float_ugt(float %x, float %y, float %a, float %b) #2 {
+
+; CHECK-LABEL: @nan_float_ugt
+
+entry:
+  %cmp = fcmp fast ugt float %y, %x
+  %b.a = select i1 %cmp, float %b, float %a
+  ret float %b.a
+
+; CHECK-NOT: xscmpgtdp
+; CHECK-NOT: xscmpgedp
+; CHECK: blr
+
+}
+
+define float @fast_float_ult(float %x, float %y, float %a, float %b) #1 {
+
+; CHECK-LABEL: @fast_float_ult
+
+entry:
+  %cmp = fcmp fast ult float %y, %x
+  %b.a = select i1 %cmp, float %b, float %a
+  ret float %b.a
+
+; CHECK: xscmpgtdp [[MASK:[0-9]+]], 1, 2
+; CHECK: xxsel 1, 3, 4, [[MASK]]
+; CHECK: blr
+
+}
+
+define float @nan_float_ult(float %x, float %y, float %a, float %b) #2 {
+
+; CHECK-LABEL: @nan_float_ult
+
+entry:
+  %cmp = fcmp fast ult float %y, %x
+  %b.a = select i1 %cmp, float %b, float %a
+  ret float %b.a
+
+; CHECK-NOT: xscmpgtdp
+; CHECK-NOT: xscmpgedp
+; CHECK: blr
+
+}
+
+
+define float @fast_float_ogt(float %x, float %y, float %a, float %b) #1 {
+
+; CHECK-LABEL: @fast_float_ogt
+
+entry:
+  %cmp = fcmp fast ogt float %y, %x
+  %b.a = select i1 %cmp, float %b, float %a
+  ret float %b.a
+
+; CHECK: xscmpgtdp [[MASK:[0-9]+]], 2, 1
+; CHECK: xxsel 1, 3, 4, [[MASK]]
+; CHECK: blr
+
+}
+
+define float @nan_float_ogt(float %x, float %y, float %a, float %b) #2 {
+
+; CHECK-LABEL: @nan_float_ogt
+
+entry:
+  %cmp = fcmp fast ogt float %y, %x
+  %b.a = select i1 %cmp, float %b, float %a
+  ret float %b.a
+
+; CHECK-NOT: xscmpgtdp
+; CHECK-NOT: xscmpgedp
+; CHECK: blr
+
+}
+
+define float @fast_float_olt(float %x, float %y, float %a, float %b) #1 {
+
+; CHECK-LABEL: @fast_float_olt
+
+entry:
+  %cmp = fcmp fast olt float %y, %x
+  %b.a = select i1 %cmp, float %b, float %a
+  ret float %b.a
+
+; CHECK: xscmpgtdp [[MASK:[0-9]+]], 1, 2
+; CHECK: xxsel 1, 3, 4, [[MASK]]
+; CHECK: blr
+
+}
+
+define float @nan_float_olt(float %x, float %y, float %a, float %b) #2 {
+
+; CHECK-LABEL: @nan_float_olt
+
+entry:
+  %cmp = fcmp fast olt float %y, %x
+  %b.a = select i1 %cmp, float %b, float %a
+  ret float %b.a
+
+; CHECK-NOT: xscmpgtdp
+; CHECK-NOT: xscmpgedp
+; CHECK: blr
+
+}
+
+define double @fast_double_uge(double %x, double %y, double %a, double %b) #1 {
+
+; CHECK-LABEL: @fast_double_uge
+; DISABLED-LABEL: @fast_double_uge
+
+entry:
+  %cmp = fcmp fast uge double %y, %x
+  %b.a = select i1 %cmp, double %b, double %a
+  ret double %b.a
+
+; CHECK: xscmpgedp [[MASK:[0-9]+]], 2, 1
+; CHECK: xxsel 1, 3, 4, [[MASK]]
+; CHECK: blr
+; DISABLED-NOT: xscmpgedp
+; DISABLED: blr
+
+}
+
+define double @nan_double_uge(double %x, double %y, double %a, double %b) #2 {
+
+; CHECK-LABEL: @nan_double_uge
+
+entry:
+  %cmp = fcmp fast uge double %y, %x
+  %b.a = select i1 %cmp, double %b, double %a
+  ret double %b.a
+
+; CHECK-NOT: xscmpgtdp
+; CHECK-NOT: xscmpgedp
+; CHECK: blr
+
+}
+
+define double @fast_double_ule(double %x, double %y, double %a, double %b) #1 {
+
+; CHECK-LABEL: @fast_double_ule
+
+entry:
+  %cmp = fcmp fast ule double %y, %x
+  %b.a = select i1 %cmp, double %b, double %a
+  ret double %b.a
+
+; CHECK: xscmpgedp [[MASK:[0-9]+]], 1, 2
+; CHECK: xxsel 1, 3, 4, [[MASK]]
+; CHECK: blr
+
+}
+
+define double @nan_double_ule(double %x, double %y, double %a, double %b) #2 {
+
+; CHECK-LABEL: @nan_double_ule
+
+entry:
+  %cmp = fcmp fast ule double %y, %x
+  %b.a = select i1 %cmp, double %b, double %a
+  ret double %b.a
+
+; CHECK-NOT: xscmpgtdp
+; CHECK-NOT: xscmpgedp
+; CHECK: blr
+
+}
+
+define double @fast_double_oge(double %x, double %y, double %a, double %b) #1 {
+
+; CHECK-LABEL: @fast_double_oge
+
+entry:
+  %cmp = fcmp fast oge double %y, %x
+  %b.a = select i1 %cmp, double %b, double %a
+  ret double %b.a
+
+; CHECK: xscmpgedp [[MASK:[0-9]+]], 2, 1
+; CHECK: xxsel 1, 3, 4, [[MASK]]
+; CHECK: blr
+
+}
+
+define double @nan_double_oge(double %x, double %y, double %a, double %b) #2 {
+
+; CHECK-LABEL: @nan_double_oge
+
+entry:
+  %cmp = fcmp fast oge double %y, %x
+  %b.a = select i1 %cmp, double %b, double %a
+  ret double %b.a
+
+; CHECK-NOT: xscmpgtdp
+; CHECK-NOT: xscmpgedp
+; CHECK: blr
+
+}
+
+define double @fast_double_ole(double %x, double %y, double %a, double %b) #1 {
+
+; CHECK-LABEL: @fast_double_ole
+
+entry:
+  %cmp = fcmp fast ole double %y, %x
+  %b.a = select i1 %cmp, double %b, double %a
+  ret double %b.a
+
+; CHECK: xscmpgedp [[MASK:[0-9]+]], 1, 2
+; CHECK: xxsel 1, 3, 4, [[MASK]]
+; CHECK: blr
+
+}
+
+define double @nan_double_ole(double %x, double %y, double %a, double %b) #2 {
+
+; CHECK-LABEL: @nan_double_ole
+
+entry:
+  %cmp = fcmp fast ole double %y, %x
+  %b.a = select i1 %cmp, double %b, double %a
+  ret double %b.a
+
+; CHECK-NOT: xscmpgtdp
+; CHECK-NOT: xscmpgedp
+; CHECK: blr
+
+}
+
+define float @fast_float_uge(float %x, float %y, float %a, float %b) #1 {
+
+; CHECK-LABEL: @fast_float_uge
+
+entry:
+  %cmp = fcmp fast uge float %y, %x
+  %b.a = select i1 %cmp, float %b, float %a
+  ret float %b.a
+
+; CHECK: xscmpgedp [[MASK:[0-9]+]], 2, 1
+; CHECK: xxsel 1, 3, 4, [[MASK]]
+; CHECK: blr
+
+}
+
+define float @nan_float_uge(float %x, float %y, float %a, float %b) #2 {
+
+; CHECK-LABEL: @nan_float_uge
+
+entry:
+  %cmp = fcmp fast uge float %y, %x
+  %b.a = select i1 %cmp, float %b, float %a
+  ret float %b.a
+
+; CHECK-NOT: xscmpgtdp
+; CHECK-NOT: xscmpgedp
+; CHECK: blr
+
+}
+
+define float @fast_float_ule(float %x, float %y, float %a, float %b) #1 {
+
+; CHECK-LABEL: @fast_float_ule
+
+entry:
+  %cmp = fcmp fast ule float %y, %x
+  %b.a = select i1 %cmp, float %b, float %a
+  ret float %b.a
+
+; CHECK: xscmpgedp [[MASK:[0-9]+]], 1, 2
+; CHECK: xxsel 1, 3, 4, [[MASK]]
+; CHECK: blr
+
+}
+
+define float @nan_float_ule(float %x, float %y, float %a, float %b) #2 {
+
+; CHECK-LABEL: @nan_float_ule
+
+entry:
+  %cmp = fcmp fast ule float %y, %x
+  %b.a = select i1 %cmp, float %b, float %a
+  ret float %b.a
+
+; CHECK-NOT: xscmpgtdp
+; CHECK-NOT: xscmpgedp
+; CHECK: blr
+
+}
+
+
+define float @fast_float_oge(float %x, float %y, float %a, float %b) #1 {
+
+; CHECK-LABEL: @fast_float_oge
+
+entry:
+  %cmp = fcmp fast oge float %y, %x
+  %b.a = select i1 %cmp, float %b, float %a
+  ret float %b.a
+
+; CHECK: xscmpgedp [[MASK:[0-9]+]], 2, 1
+; CHECK: xxsel 1, 3, 4, [[MASK]]
+; CHECK: blr
+
+}
+
+define float @nan_float_oge(float %x, float %y, float %a, float %b) #2 {
+
+; CHECK-LABEL: @nan_float_oge
+
+entry:
+  %cmp = fcmp fast oge float %y, %x
+  %b.a = select i1 %cmp, float %b, float %a
+  ret float %b.a
+
+; CHECK-NOT: xscmpgtdp
+; CHECK-NOT: xscmpgedp
+; CHECK: blr
+
+}
+
+define float @fast_float_ole(float %x, float %y, float %a, float %b) #1 {
+
+; CHECK-LABEL: @fast_float_ole
+
+entry:
+  %cmp = fcmp fast ole float %y, %x
+  %b.a = select i1 %cmp, float %b, float %a
+  ret float %b.a
+
+; CHECK: xscmpgedp [[MASK:[0-9]+]], 1, 2
+; CHECK: xxsel 1, 3, 4, [[MASK]]
+; CHECK: blr
+
+}
+
+define float @nan_float_ole(float %x, float %y, float %a, float %b) #2 {
+
+; CHECK-LABEL: @nan_float_ole
+
+entry:
+  %cmp = fcmp fast ole float %y, %x
+  %b.a = select i1 %cmp, float %b, float %a
+  ret float %b.a
+
+; CHECK-NOT: xscmpgtdp
+; CHECK-NOT: xscmpgedp
+; CHECK: blr
+
+}
+
+define double @one_test_fast(double %x, double %y) #1 {
+
+; CHECK-LABEL: @one_test_fast
+; DISABLED-LABEL: @one_test_fast
+
+entry:
+  %cmp = fcmp one double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK: xscmpeqdp [[MASK:[0-9]+]], 1, 2
+; CHECK: xxsel 1, 2, 1, [[MASK]]
+; CHECK: blr
+; DISABLED-NOT: xscmpeqdp
+; DISABLED: blr
+
+}
+
+define double @one_test(double %x, double %y) #2 {
+
+; CHECK-LABEL: @one_test
+
+entry:
+  %cmp = fcmp one double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK: xscmpeqdp [[MASK:[0-9]+]], 1, 2
+; CHECK: xxsel 1, 2, 1, [[MASK]]
+; CHECK: blr
+
+}
+
+define double @oeq_test_fast(double %x, double %y) #1 {
+
+; CHECK-LABEL: @oeq_test_fast
+
+entry:
+  %cmp = fcmp oeq double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK: xscmpeqdp [[MASK:[0-9]+]], 1, 2
+; CHECK: xxsel 1, 1, 2, [[MASK]]
+; CHECK: blr
+
+}
+
+define double @oeq_test(double %x, double %y) #2 {
+
+; CHECK-LABEL: @oeq_test
+
+entry:
+  %cmp = fcmp oeq double %x, %y
+  %y.x = select i1 %cmp, double %y, double %x
+  ret double %y.x
+
+; CHECK: xscmpeqdp [[MASK:[0-9]+]], 1, 2
+; CHECK: xxsel 1, 1, 2, [[MASK]]
+; CHECK: blr
+
+}
+
+define float @one_test_fast_float(float %x, float %y) #1 {
+
+; CHECK-LABEL: @one_test_fast_float
+
+entry:
+  %cmp = fcmp one float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK: xscmpeqdp [[MASK:[0-9]+]], 1, 2
+; CHECK: xxsel 1, 2, 1, [[MASK]]
+; CHECK: blr
+
+}
+
+define float @one_test_float(float %x, float %y) #2 {
+
+; CHECK-LABEL: @one_test_float
+
+entry:
+  %cmp = fcmp one float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK: xscmpeqdp [[MASK:[0-9]+]], 1, 2
+; CHECK: xxsel 1, 2, 1, [[MASK]]
+; CHECK: blr
+
+}
+
+define float @oeq_test_fast_float(float %x, float %y) #1 {
+
+; CHECK-LABEL: @oeq_test_fast_float
+
+entry:
+  %cmp = fcmp oeq float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK: xscmpeqdp [[MASK:[0-9]+]], 1, 2
+; CHECK: xxsel 1, 1, 2, [[MASK]]
+; CHECK: blr
+
+}
+
+define float @oeq_test_float(float %x, float %y) #2 {
+
+; CHECK-LABEL: @oeq_test_float
+
+entry:
+  %cmp = fcmp oeq float %x, %y
+  %y.x = select i1 %cmp, float %y, float %x
+  ret float %y.x
+
+; CHECK: xscmpeqdp [[MASK:[0-9]+]], 1, 2
+; CHECK: xxsel 1, 1, 2, [[MASK]]
+; CHECK: blr
+
+}