Power9 - Enable the pwr9 cpu in the back end

[nemanjai]

Summary

This patch simply adds support for -mcpu=pwr9 in the back end. It makes some preliminary decisions with regard to scheduling that are likely to change once the necessary information becomes available. Any such decisions have FIXME in the code and refer to POWER9 so they are easy to find once we start adding this support.

Since this patch doesn't really add any functional changes, there is no tests associated. The subsequent patches will add exploitation of the new instructions and will have test cases as well.

[kbarton]

LGTM

[echristo]

Unrelated to this commit, but does FeatureISA3_0 make sense as a subtarget feature or should more granularity happen here?

Otherwise it would be nice to see any tests that make sure that mcpu=pwr9 is actually doing something :)

-eric

[nemanjai]

In D19683#420421, @echristo wrote:

Unrelated to this commit, but does FeatureISA3_0 make sense as a subtarget feature or should more granularity happen here?

Otherwise it would be nice to see any tests that make sure that mcpu=pwr9 is actually doing something :)

-eric

Due to the ISA not having any optional categories, we have decided that for most things, we don't want the granularity that we had with prior ISA levels. What we kind of settled on was the P9Vector, P9Altivec and ISA3_0. If you prefer that we split them out into finer grained features, we can certainly discuss what features we'd want.

For testing, I'll add an -mcpu=pwr9 line to one of the test cases to ensure that the feature is accepted by llc. Functional testing for the target features and predicates is already available in my follow-up patch for the new non-permuting loads and stores.

[nemanjai]

Committed revision 268950.

[echristo]

In D19683#424426, @nemanjai wrote:

In D19683#420421, @echristo wrote:

Unrelated to this commit, but does FeatureISA3_0 make sense as a subtarget feature or should more granularity happen here?

Otherwise it would be nice to see any tests that make sure that mcpu=pwr9 is actually doing something :)

-eric

Due to the ISA not having any optional categories, we have decided that for most things, we don't want the granularity that we had with prior ISA levels. What we kind of settled on was the P9Vector, P9Altivec and ISA3_0. If you prefer that we split them out into finer grained features, we can certainly discuss what features we'd want.

Good for me for now, and if we feel a need to have them split we can.

For testing, I'll add an -mcpu=pwr9 line to one of the test cases to ensure that the feature is accepted by llc. Functional testing for the target features and predicates is already available in my follow-up patch for the new non-permuting loads and stores.

Cool.

-eric

lib/Support/Host.cpp

return StringSwitch<const char *>(StringRef(CPUStart, CPULen))
     .Case("PPC970MP", "970")
     .Case("G5", "g5")
     .Case("POWER5", "g5")
     .Case("A2", "a2")
     .Case("POWER6", "pwr6")
     .Case("POWER7", "pwr7")
     .Case("POWER8", "pwr8")
     .Case("POWER8E", "pwr8")
+    .Case("POWER9", "pwr9")
     .Default(generic);
 }
 #elif defined(__linux__) && defined(__arm__)
 StringRef sys::getHostCPUName() {
   // The cpuid register on arm is not accessible from user space. On Linux,
   // it is exposed through the /proc/cpuinfo file.
 
   // Read 1024 bytes from /proc/cpuinfo, which should contain the CPU part line

lib/Target/PowerPC/PPC.td

 def DirectivePwr3: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR3", "">;
 def DirectivePwr4: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR4", "">;
 def DirectivePwr5: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5", "">;
 def DirectivePwr5x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR5X", "">;
 def DirectivePwr6: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6", "">;
 def DirectivePwr6x: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR6X", "">;
 def DirectivePwr7: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR7", "">;
 def DirectivePwr8: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR8", "">;
+def DirectivePwr9: SubtargetFeature<"", "DarwinDirective", "PPC::DIR_PWR9", "">;
 
 def Feature64Bit     : SubtargetFeature<"64bit","Has64BitSupport", "true",
                                         "Enable 64-bit instructions">;
 def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
                               "Use software emulation for floating point">;                                        
 def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
                               "Enable 64-bit registers usage for ppc32 [beta]">;
 def FeatureCRBits    : SubtargetFeature<"crbits", "UseCRBits", "true",
def ProcessorFeatures {
   list<SubtargetFeature> Power8SpecificFeatures =
       [DirectivePwr8, FeatureP8Altivec, FeatureP8Vector, FeatureP8Crypto,
        FeatureHTM, FeatureDirectMove, FeatureICBT, FeaturePartwordAtomic,
        FeatureFusion];
   list<SubtargetFeature> Power8FeatureList =
       !listconcat(Power7FeatureList, Power8SpecificFeatures);
   list<SubtargetFeature> Power9SpecificFeatures =
       [FeatureP9Altivec, FeatureP9Vector, FeatureISA3_0];
+  list<SubtargetFeature> Power9FeatureList =
+      !listconcat(Power8FeatureList, Power9SpecificFeatures);
 }
 
 // Note: Future features to add when support is extended to more
 // recent ISA levels:
 //
 // DFP          p6, p6x, p7        decimal floating-point instructions
 // POPCNTB      p5 through p7      popcntb and related instructions
 
def : ProcessorModel<"pwr6x", G5Model,
                   [DirectivePwr5x, FeatureAltivec, FeatureMFOCRF,
                    FeatureFCPSGN, FeatureFSqrt, FeatureFRE, FeatureFRES,
                    FeatureFRSQRTE, FeatureFRSQRTES, FeatureRecipPrec,
                    FeatureSTFIWX, FeatureLFIWAX, FeatureCMPB,
                    FeatureFPRND, Feature64Bit,
                    FeatureMFTB, DeprecatedDST]>;
 def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.Power7FeatureList>;
 def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.Power8FeatureList>;
+// FIXME: Same as P8 until the POWER9 scheduling info is available
+def : ProcessorModel<"pwr9", P8Model, ProcessorFeatures.Power9FeatureList>;
 def : Processor<"ppc", G3Itineraries, [Directive32, FeatureMFTB]>;
 def : ProcessorModel<"ppc64", G5Model,
                   [Directive64, FeatureAltivec,
                    FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
                    FeatureFRSQRTE, FeatureSTFIWX,
                    Feature64Bit /*, Feature64BitRegs */,
                    FeatureMFTB]>;
 def : ProcessorModel<"ppc64le", P8Model, ProcessorFeatures.Power8FeatureList>;

lib/Target/PowerPC/PPCHazardRecognizers.cpp

 unsigned PPCDispatchGroupSBHazardRecognizer::PreEmitNoops(SUnit *SU) {
   // We only need to fill out a maximum of 5 slots here: The 6th slot could
   // only be a second branch, and otherwise the next instruction will start a
   // new group.
   if (isLoadAfterStore(SU) && CurSlots < 6) {
     unsigned Directive =
         DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
     // If we're using a special group-terminating nop, then we need only one.
+    // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
     if (Directive == PPC::DIR_PWR6 || Directive == PPC::DIR_PWR7 ||
-        Directive == PPC::DIR_PWR8 )
+        Directive == PPC::DIR_PWR8 || Directive == PPC::DIR_PWR9)
       return 1;
 
     return 5 - CurSlots;
   }
 
   return ScoreboardHazardRecognizer::PreEmitNoops(SU);
 }
 
void PPCDispatchGroupSBHazardRecognizer::Reset() {
   return ScoreboardHazardRecognizer::Reset();
 }
 
 void PPCDispatchGroupSBHazardRecognizer::EmitNoop() {
   unsigned Directive =
       DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
   // If the group has now filled all of its slots, or if we're using a special
   // group-terminating nop, the group is complete.
+  // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
   if (Directive == PPC::DIR_PWR6 || Directive == PPC::DIR_PWR7 ||
-      Directive == PPC::DIR_PWR8 || CurSlots == 6)  {
+      Directive == PPC::DIR_PWR8 || Directive == PPC::DIR_PWR8 ||
+      CurSlots == 6) {
     CurGroup.clear();
     CurSlots = CurBranches = 0;
   } else {
     CurGroup.push_back(nullptr);
     ++CurSlots;
   }
 }
 

lib/Target/PowerPC/PPCISelLowering.cpp

PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
   case PPC::DIR_E5500:
   case PPC::DIR_PWR4:
   case PPC::DIR_PWR5:
   case PPC::DIR_PWR5X:
   case PPC::DIR_PWR6:
   case PPC::DIR_PWR6X:
   case PPC::DIR_PWR7:
   case PPC::DIR_PWR8:
+  case PPC::DIR_PWR9:
     setPrefFunctionAlignment(4);
     setPrefLoopAlignment(4);
     break;
   }
 
 
   if (Subtarget.enableMachineScheduler())
     setSchedulingPreference(Sched::Source);
unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
   default: break;
   case PPC::DIR_970:
   case PPC::DIR_PWR4:
   case PPC::DIR_PWR5:
   case PPC::DIR_PWR5X:
   case PPC::DIR_PWR6:
   case PPC::DIR_PWR6X:
   case PPC::DIR_PWR7:
-  case PPC::DIR_PWR8: {
+  case PPC::DIR_PWR8:
+  case PPC::DIR_PWR9: {
     if (!ML)
       break;
 
     const PPCInstrInfo *TII = Subtarget.getInstrInfo();
 
     // For small loops (between 5 and 8 instructions), align to a 32-byte
     // boundary so that the entire loop fits in one instruction-cache line.
     uint64_t LoopSize = 0;

lib/Target/PowerPC/PPCInstrInfo.cpp

 /// CreateTargetPostRAHazardRecognizer - Return the postRA hazard recognizer
 /// to use for this target when scheduling the DAG.
 ScheduleHazardRecognizer *
 PPCInstrInfo::CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
                                                  const ScheduleDAG *DAG) const {
   unsigned Directive =
       DAG->MF.getSubtarget<PPCSubtarget>().getDarwinDirective();
 
+  // FIXME: Leaving this as-is until we have POWER9 scheduling info
   if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8)
     return new PPCDispatchGroupSBHazardRecognizer(II, DAG);
 
   // Most subtargets use a PPC970 recognizer.
   if (Directive != PPC::DIR_440 && Directive != PPC::DIR_A2 &&
       Directive != PPC::DIR_E500mc && Directive != PPC::DIR_E5500) {
     assert(DAG->TII && "No InstrInfo?");
 
if (UseMI->isBranch() && IsRegCR) {
     case PPC::DIR_E5500:
     case PPC::DIR_PWR4:
     case PPC::DIR_PWR5:
     case PPC::DIR_PWR5X:
     case PPC::DIR_PWR6:
     case PPC::DIR_PWR6X:
     case PPC::DIR_PWR7:
     case PPC::DIR_PWR8:
+    // FIXME: Is this needed for POWER9?
       Latency += 2;
       break;
     }
   }
 
   return Latency;
 }
 
void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
   // that terminates dispatch groups on the POWER cores.
   unsigned Directive = Subtarget.getDarwinDirective();
   unsigned Opcode;
   switch (Directive) {
   default:            Opcode = PPC::NOP; break;
   case PPC::DIR_PWR6: Opcode = PPC::NOP_GT_PWR6; break;
   case PPC::DIR_PWR7: Opcode = PPC::NOP_GT_PWR7; break;
   case PPC::DIR_PWR8: Opcode = PPC::NOP_GT_PWR7; break; /* FIXME: Update when P8 InstrScheduling model is ready */
+  // FIXME: Update when POWER9 scheduling model is ready.
+  case PPC::DIR_PWR9: Opcode = PPC::NOP_GT_PWR7; break;
   }
 
   DebugLoc DL;
   BuildMI(MBB, MI, DL, get(Opcode));
 }
 
 /// getNoopForMachoTarget - Return the noop instruction to use for a noop.
 void PPCInstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {

lib/Target/PowerPC/PPCSubtarget.h

enum {
     DIR_PWR3,
     DIR_PWR4,
     DIR_PWR5,
     DIR_PWR5X,
     DIR_PWR6,
     DIR_PWR6X,
     DIR_PWR7,
     DIR_PWR8,
+    DIR_PWR9,
     DIR_64
   };
 }
 
 class GlobalValue;
 class TargetMachine;
 
 class PPCSubtarget : public PPCGenSubtargetInfo {

lib/Target/PowerPC/PPCSubtarget.cpp

static bool needsAggressiveScheduling(unsigned Directive) {
   switch (Directive) {
   default: return false;
   case PPC::DIR_440:
   case PPC::DIR_A2:
   case PPC::DIR_E500mc:
   case PPC::DIR_E5500:
   case PPC::DIR_PWR7:
   case PPC::DIR_PWR8:
+  // FIXME: Same as P8 until POWER9 scheduling info is available
+  case PPC::DIR_PWR9:
     return true;
   }
 }
 
 bool PPCSubtarget::enableMachineScheduler() const {
   // Enable MI scheduling for the embedded cores.
   // FIXME: Enable this for all cores (some additional modeling
   // may be necessary).

lib/Target/PowerPC/PPCTargetTransformInfo.cpp

if (Directive == PPC::DIR_A2)
     return 6;
 
   // FIXME: For lack of any better information, do no harm...
   if (Directive == PPC::DIR_E500mc || Directive == PPC::DIR_E5500)
     return 1;
 
   // For P7 and P8, floating-point instructions have a 6-cycle latency and
   // there are two execution units, so unroll by 12x for latency hiding.
-  if (Directive == PPC::DIR_PWR7 ||
-      Directive == PPC::DIR_PWR8)
+  // FIXME: the same for P9 as previous gen until POWER9 scheduling is ready
+  if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
+      Directive == PPC::DIR_PWR9)
     return 12;
 
   // For most things, modern systems have two execution units (and
   // out-of-order execution).
   return 2;
 }
 
 int PPCTTIImpl::getArithmeticInstrCost(