[Sparc] Add Soft Float support

[jacob_hansen]

Summary

This patch adds support for software floating point operations for Sparc targets.

This is the first in a set of patches to enable software floating point on Sparc. The next patch will enable the option to be used with Clang.

[jacob_hansen]

Reintroduced the header on line 1 of SparcISelLowering.h which was accidentally removed.

[jacob_hansen]

I had initially planned to do this over two patches but changed my mind a decided it was better to do it in one. This updated patch ensures that the soft-float attribute is retained when the target options are being reset (this change is identical to how other targets handles this situation).

[jyknight]

What's the ABI impact of this? Will this use the same calling convention as GCC does?

lib/Target/Sparc/SparcTargetMachine.cpp

88

I wonder what the point of having this redundant way of specifying soft-float via "use-soft-float" is. Clang seems to emit *both* use-soft-float=true and +soft-float. Hopefully this isn't needed these days. @echristo?

lib/Target/Sparc/SparcTargetMachine.h

25–26

Pretty sure this ought to be deleted while adding the SubtargetMap.

[jacob_hansen]

The change should use the same calling convention as GCC does, yes. I tested the change by linking with libgcc (from http://www.gaisler.com/index.php/products/operating-systems/bcc) which contains implementation of all the floating point procedures, that seemed to work perfectly. I also tested it by manually compiling a library of the builtins from the Compiler-RT project (Compiler-RT builtins are compatible with libgcc as noted on http://compiler-rt.llvm.org/), and that worked as well.

lib/Target/Sparc/SparcTargetMachine.cpp

88

I was wondering as well actually, didn't really find an answer to why this might be, but all targets seem to do this at the moment.

lib/Target/Sparc/SparcTargetMachine.h

25–26

I think you are right. Currently I use that object on line 100 of SparcTargetMachine.cpp to determine whether the target is currently 32 or 64 bit (using is64Bit()). Should I just create a new boolean variable here to determine this value instead of using the Subtarget object, or is there a better way?

[echristo]

lib/Target/Sparc/SparcSubtarget.cpp

56

Can you do this constification in a separate patch? (Feel free to just submit it).

lib/Target/Sparc/SparcTargetMachine.cpp

88

It's redundant as a subtarget feature for soft float wasn't across all targets yet, but if someone is willing to do that cleanup we can get rid of it. (Should do this in a separate patch as I know there are out of tree users etc...)

lib/Target/Sparc/SparcTargetMachine.h

25–26

This should be removed for sure. You should determine 32 or 64-bit ness in the TargetMachine based on what information you have in the TargetMachine configuration rather than the other. It can't change on a subtarget specific basis anyhow.

[jacob_hansen]

lib/Target/Sparc/SparcSubtarget.cpp

56

Sure, I submitted D19797 - This was my first patch so I do not have SVN write access at this time, could you submit it for me?

[jacob_hansen]

Removed the subtarget object from the TargetMachine and changed the way 32/64 bit ness is determined as requested.

The constification of TargetMachine arguments in SparcISelLowering and SparcSubtarget has been moved to D19797, which is now a dependency for this patch.

[jyknight]

Looks pretty good to me, but here's a few issues:

1. There's a *bunch* of trailing whitespace in your patch (e.g. most of getSubtargetImpl). If you run your patch through clang-format, it will fix that for you, either use git clang-format (if you're using git for your checkout -- which I'd recommend), or clang-format-diff as mentioned on http://clang.llvm.org/docs/ClangFormat.html, if you're using svn.

2. Your CHECKs in your test are incorrectly specified -- CHECK-LABEL is to specify the beginning of the function, *not* for the assertion itself. See http://llvm.org/docs/CommandGuide/FileCheck.html

3. You can simplify your test cases by getting rid of the alloca and loads: just move the values to function arguments.

Like this, for example:

 define i1 @test_gtdf2(double %a, double %b) #0 {
; CHECK-LABEL: test_gtdf2:
; CHECK: call __gtdf2
  %cmp = fcmp ogt double %a, %b
  ret i1 %cmp
}

5. There are no function call/return ABI tests. Can probably add to the existing 32abi.ll and 64abi.ll tests for this, by adding another RUN line.

E.g. for 64abi.ll

; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s --check-prefix=CHECK --check-prefix=HARD
; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc  -mattr=soft-float | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT

And then you just expand the CHECK: lines which differ for hard/soft-float to have a separate HARD: and SOFT: case, instead.

5. No tests for float or fp128. For fp128, it might make sense to have another RUN line on the existing tests in fp128.ll.

6. Nit: I'd rename the file "soft-float.ll", vs "softfloat.ll"

[jacob_hansen]

The following have been updated in this patch:

• trailing whitespace removed
• soft-float.ll tests is now correctly specified, the test cases have been simplified, added tests for fp128, and file was renamed from softfloat.ll
• adjusted the test cases in 32abi.ll and 62abi.ll to include testing for software floating point
• Adjusted behavior for fp128/quad floats so that the compiler-rt function calls (__addtf3 and so forth) are used for all floating point operations, including fp128, when soft-float option is enabled (before calls to _Q_add was used for fp128/quad floats when softfloat was enabled)

[jacob_hansen]

Accidentally removed two tests from 32abi.ll in the previous revision, this revision reintroduces them.

lib/Target/Sparc/Sparc.td

 
 def FeatureHardQuad
   : SubtargetFeature<"hard-quad-float", "HasHardQuad", "true",
                      "Enable quad-word floating point instructions">;
 
 def UsePopc : SubtargetFeature<"popc", "UsePopc", "true",
                                "Use the popc (population count) instruction">;
 
+def FeatureSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
+                              "Use software emulation for floating point">;  
+
 //==== Features added predmoninantly for LEON subtarget support                               
 include "LeonFeatures.td"
 
 //===----------------------------------------------------------------------===//
 // Register File, Calling Conv, Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
 include "SparcRegisterInfo.td"

lib/Target/Sparc/SparcISelLowering.h

namespace SPISD {
     };
   }
 
   class SparcTargetLowering : public TargetLowering {
     const SparcSubtarget *Subtarget;
   public:
     SparcTargetLowering(const TargetMachine &TM, const SparcSubtarget &STI);
     SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
     
+    bool useSoftFloat() const override;
+    
     /// computeKnownBitsForTargetNode - Determine which of the bits specified
     /// in Mask are known to be either zero or one and return them in the
     /// KnownZero/KnownOne bitsets.
     void computeKnownBitsForTargetNode(const SDValue Op,
                                        APInt &KnownZero,
                                        APInt &KnownOne,
                                        const SelectionDAG &DAG,
                                        unsigned Depth = 0) const override;

lib/Target/Sparc/SparcISelLowering.cpp

SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
   // matters much whether it's ZeroOrOneBooleanContent, or
   // ZeroOrNegativeOneBooleanContent, so, arbitrarily choose the
   // former.
   setBooleanContents(ZeroOrOneBooleanContent);
   setBooleanVectorContents(ZeroOrOneBooleanContent);
 
   // Set up the register classes.
   addRegisterClass(MVT::i32, &SP::IntRegsRegClass);
+  if (!Subtarget->useSoftFloat()) {
     addRegisterClass(MVT::f32, &SP::FPRegsRegClass);
     addRegisterClass(MVT::f64, &SP::DFPRegsRegClass);
     addRegisterClass(MVT::f128, &SP::QFPRegsRegClass);
+  }
   if (Subtarget->is64Bit()) {
     addRegisterClass(MVT::i64, &SP::I64RegsRegClass);
   } else {
     // On 32bit sparc, we define a double-register 32bit register
     // class, as well. This is modeled in LLVM as a 2-vector of i32.
     addRegisterClass(MVT::v2i32, &SP::IntPairRegClass);
 
     // ...but almost all operations must be expanded, so set that as
if (Subtarget->hasHardQuad()) {
     setOperationAction(ISD::FNEG,  MVT::f128, Custom);
     setOperationAction(ISD::FABS,  MVT::f128, Custom);
 
     setOperationAction(ISD::FP_EXTEND, MVT::f128, Custom);
     setOperationAction(ISD::FP_ROUND,  MVT::f64, Custom);
     setOperationAction(ISD::FP_ROUND,  MVT::f32, Custom);
 
     // Setup Runtime library names.
-    if (Subtarget->is64Bit()) {
+    if (Subtarget->is64Bit() && !Subtarget->useSoftFloat()) {
       setLibcallName(RTLIB::ADD_F128,  "_Qp_add");
       setLibcallName(RTLIB::SUB_F128,  "_Qp_sub");
       setLibcallName(RTLIB::MUL_F128,  "_Qp_mul");
       setLibcallName(RTLIB::DIV_F128,  "_Qp_div");
       setLibcallName(RTLIB::SQRT_F128, "_Qp_sqrt");
       setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Qp_qtoi");
       setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Qp_qtoui");
       setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Qp_itoq");
       setLibcallName(RTLIB::UINTTOFP_I32_F128, "_Qp_uitoq");
       setLibcallName(RTLIB::FPTOSINT_F128_I64, "_Qp_qtox");
       setLibcallName(RTLIB::FPTOUINT_F128_I64, "_Qp_qtoux");
       setLibcallName(RTLIB::SINTTOFP_I64_F128, "_Qp_xtoq");
       setLibcallName(RTLIB::UINTTOFP_I64_F128, "_Qp_uxtoq");
       setLibcallName(RTLIB::FPEXT_F32_F128, "_Qp_stoq");
       setLibcallName(RTLIB::FPEXT_F64_F128, "_Qp_dtoq");
       setLibcallName(RTLIB::FPROUND_F128_F32, "_Qp_qtos");
       setLibcallName(RTLIB::FPROUND_F128_F64, "_Qp_qtod");
-    } else {
+    } else if (!Subtarget->useSoftFloat()) {
       setLibcallName(RTLIB::ADD_F128,  "_Q_add");
       setLibcallName(RTLIB::SUB_F128,  "_Q_sub");
       setLibcallName(RTLIB::MUL_F128,  "_Q_mul");
       setLibcallName(RTLIB::DIV_F128,  "_Q_div");
       setLibcallName(RTLIB::SQRT_F128, "_Q_sqrt");
       setLibcallName(RTLIB::FPTOSINT_F128_I32, "_Q_qtoi");
       setLibcallName(RTLIB::FPTOUINT_F128_I32, "_Q_qtou");
       setLibcallName(RTLIB::SINTTOFP_I32_F128, "_Q_itoq");
SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
 
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
 
   setMinFunctionAlignment(2);
 
   computeRegisterProperties(Subtarget->getRegisterInfo());
 }
 
+bool SparcTargetLowering::useSoftFloat() const {
+  return Subtarget->useSoftFloat();
+}
+
 const char *SparcTargetLowering::getTargetNodeName(unsigned Opcode) const {
   switch ((SPISD::NodeType)Opcode) {
   case SPISD::FIRST_NUMBER:    break;
   case SPISD::CMPICC:          return "SPISD::CMPICC";
   case SPISD::CMPFCC:          return "SPISD::CMPFCC";
   case SPISD::BRICC:           return "SPISD::BRICC";
   case SPISD::BRXCC:           return "SPISD::BRXCC";
   case SPISD::BRFCC:           return "SPISD::BRFCC";

lib/Target/Sparc/SparcSubtarget.h

class SparcSubtarget : public SparcGenSubtargetInfo {
   bool IsV9;
   bool IsLeon;
   bool HasUmacSmac;
   bool V8DeprecatedInsts;
   bool IsVIS, IsVIS2, IsVIS3;
   bool Is64Bit;
   bool HasHardQuad;
   bool UsePopc;
+  bool UseSoftFloat;
   SparcInstrInfo InstrInfo;
   SparcTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
   SparcFrameLowering FrameLowering;
 
 public:
   SparcSubtarget(const Triple &TT, const std::string &CPU,
                  const std::string &FS, const TargetMachine &TM, bool is64bit);
public:
   bool isLeon() const { return IsLeon; }
   bool hasUmacSmac() const { return HasUmacSmac; }
   bool isVIS() const { return IsVIS; }
   bool isVIS2() const { return IsVIS2; }
   bool isVIS3() const { return IsVIS3; }
   bool useDeprecatedV8Instructions() const { return V8DeprecatedInsts; }
   bool hasHardQuad() const { return HasHardQuad; }
   bool usePopc() const { return UsePopc; }
+  bool useSoftFloat() const { return UseSoftFloat; }
 
   /// ParseSubtargetFeatures - Parses features string setting specified
   /// subtarget options.  Definition of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
   SparcSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS);
 
   bool is64Bit() const { return Is64Bit; }
 

lib/Target/Sparc/SparcSubtarget.cpp

 SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(StringRef CPU,
                                                                 StringRef FS) {
   IsV9 = false;
   IsLeon = false;
   V8DeprecatedInsts = false;
   IsVIS = false;
   HasHardQuad = false;
   UsePopc = false;
+  UseSoftFloat = false;
   HasUmacSmac = false;
 
   // Determine default and user specified characteristics
   std::string CPUName = CPU;
   if (CPUName.empty())
     CPUName = (Is64Bit) ? "v9" : "v8";
 
   // Parse features string.
   ParseSubtargetFeatures(CPUName, FS);
 
   // Popc is a v9-only instruction.
   if (!IsV9)
     UsePopc = false;
 
   return *this;
 }
 
 SparcSubtarget::SparcSubtarget(const Triple &TT, const std::string &CPU,
                                const std::string &FS, const TargetMachine &TM,
                                bool is64Bit)
     : SparcGenSubtargetInfo(TT, CPU, FS), TargetTriple(TT), Is64Bit(is64Bit),
       InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this),
       FrameLowering(*this) {}
 
 int SparcSubtarget::getAdjustedFrameSize(int frameSize) const {
 
   if (is64Bit()) {

lib/Target/Sparc/SparcTargetMachine.h

 #include "SparcInstrInfo.h"
 #include "SparcSubtarget.h"
 #include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
 
 class SparcTargetMachine : public LLVMTargetMachine {
   std::unique_ptr<TargetLoweringObjectFile> TLOF;
-  SparcSubtarget Subtarget;
+  bool is64Bit;
+  mutable StringMap<std::unique_ptr<SparcSubtarget>> SubtargetMap;
 public:
   SparcTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                      StringRef FS, const TargetOptions &Options,
                      Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL,
                      bool is64bit);
   ~SparcTargetMachine() override;
 
-  const SparcSubtarget *getSubtargetImpl(const Function &) const override {
-    return &Subtarget;
-  }
+  const SparcSubtarget *getSubtargetImpl(const Function &) const override;
 
   // Pass Pipeline Configuration
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
   TargetLoweringObjectFile *getObjFileLowering() const override {
     return TLOF.get();
   }
 };
 

lib/Target/Sparc/SparcTargetMachine.cpp

 ///
 SparcTargetMachine::SparcTargetMachine(const Target &T, const Triple &TT,
                                        StringRef CPU, StringRef FS,
                                        const TargetOptions &Options,
                                        Reloc::Model RM, CodeModel::Model CM,
                                        CodeGenOpt::Level OL, bool is64bit)
     : LLVMTargetMachine(T, computeDataLayout(TT, is64bit), TT, CPU, FS, Options,
                         RM, CM, OL),
-      TLOF(make_unique<SparcELFTargetObjectFile>()),
-      Subtarget(TT, CPU, FS, *this, is64bit) {
+      TLOF(make_unique<SparcELFTargetObjectFile>()) {
   initAsmInfo();
+  this->is64Bit = is64bit;
 }
 
 SparcTargetMachine::~SparcTargetMachine() {}
 
+const SparcSubtarget * 
+SparcTargetMachine::getSubtargetImpl(const Function &F) const {
+  Attribute CPUAttr = F.getFnAttribute("target-cpu");
+  Attribute FSAttr = F.getFnAttribute("target-features");
+
+  std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
+                        ? CPUAttr.getValueAsString().str()
+                        : TargetCPU;
+  std::string FS = !FSAttr.hasAttribute(Attribute::None)
+                       ? FSAttr.getValueAsString().str()
+                       : TargetFS;
+
+  // FIXME: This is related to the code below to reset the target options,
+  // we need to know whether or not the soft float flag is set on the
+  // function, so we can enable it as a subtarget feature.
+  bool softFloat =
+      F.hasFnAttribute("use-soft-float") &&
+      F.getFnAttribute("use-soft-float").getValueAsString() == "true";
+
+  if (softFloat)         
+    FS += FS.empty() ? "+soft-float" : ",+soft-float";
+
+  auto &I = SubtargetMap[CPU + FS];
+  if (!I) {
+    // This needs to be done before we create a new subtarget since any
+    // creation will depend on the TM and the code generation flags on the
+    // function that reside in TargetOptions.
+    resetTargetOptions(F);
+    I = llvm::make_unique<SparcSubtarget>(TargetTriple, CPU, FS, *this,
+                                          this->is64Bit);
+  }
+  return I.get();
+}
+
 namespace {
 /// Sparc Code Generator Pass Configuration Options.
 class SparcPassConfig : public TargetPassConfig {
 public:
   SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
     : TargetPassConfig(TM, PM) {}
 
   SparcTargetMachine &getSparcTargetMachine() const {

test/CodeGen/SPARC/32abi.ll

-; RUN: llc < %s -march=sparc -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-BE
-; RUN: llc < %s -march=sparcel -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-LE
+; RUN: llc < %s -march=sparc -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s --check-prefix=CHECK --check-prefix=HARD --check-prefix=CHECK-BE
+; RUN: llc < %s -march=sparcel -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s --check-prefix=CHECK --check-prefix=HARD --check-prefix=CHECK-LE
+; RUN: llc < %s -march=sparc -disable-sparc-delay-filler -disable-sparc-leaf-proc -mattr=soft-float | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT --check-prefix=CHECK-BE
 
 ; CHECK-LABEL: intarg:
 ; The save/restore frame is not strictly necessary here, but we would need to
 ; refer to %o registers instead.
 ; CHECK: save %sp, -96, %sp
 ; CHECK: ld [%fp+96], [[R2:%[gilo][0-7]]]
 ; CHECK: ld [%fp+92], [[R1:%[gilo][0-7]]]
 ; CHECK: stb %i0, [%i4]
define void @call_intarg(i32 %i0, i8* %i1) {
   call void @intarg(i8 0, i8 1, i16 2, i32 3, i8* undef, i32 5, i32 %i0, i8* %i1)
   ret void
 }
 
 ;; Verify doubles starting with an even reg, starting with an odd reg,
 ;; straddling the boundary of regs and mem, and floats in regs and mem.
 ;
 ; CHECK-LABEL: floatarg:
-; CHECK: save %sp, -120, %sp
-; CHECK: mov %i5, %g2
-; CHECK-NEXT: ld [%fp+92], %g3
-; CHECK-NEXT: mov %i4, %i5
-; CHECK-NEXT: std %g2, [%fp+-24]
-; CHECK-NEXT: mov %i3, %i4
-; CHECK-NEXT: std %i4, [%fp+-16]
-; CHECK-NEXT: std %i0, [%fp+-8]
-; CHECK-NEXT: st %i2, [%fp+-28]
-; CHECK-NEXT: ld [%fp+104], %f0
-; CHECK-NEXT: ldd [%fp+96], %f2
-; CHECK-NEXT: ld [%fp+-28], %f1
-; CHECK-NEXT: ldd [%fp+-8], %f4
-; CHECK-NEXT: ldd [%fp+-16], %f6
-; CHECK-NEXT: ldd [%fp+-24], %f8
-; CHECK-NEXT: fstod %f1, %f10
-; CHECK-NEXT: faddd %f4, %f10, %f4
-; CHECK-NEXT: faddd %f6, %f4, %f4
-; CHECK-NEXT: faddd %f8, %f4, %f4
-; CHECK-NEXT: faddd %f2, %f4, %f2
-; CHECK-NEXT: fstod %f0, %f0
-; CHECK-NEXT: faddd %f0, %f2, %f0
-; CHECK-NEXT: restore
+; HARD: save %sp, -120, %sp
+; HARD: mov %i5, %g2
+; HARD-NEXT: ld [%fp+92], %g3
+; HARD-NEXT: mov %i4, %i5
+; HARD-NEXT: std %g2, [%fp+-24]
+; HARD-NEXT: mov %i3, %i4
+; HARD-NEXT: std %i4, [%fp+-16]
+; HARD-NEXT: std %i0, [%fp+-8]
+; HARD-NEXT: st %i2, [%fp+-28]
+; HARD-NEXT: ld [%fp+104], %f0
+; HARD-NEXT: ldd [%fp+96], %f2
+; HARD-NEXT: ld [%fp+-28], %f1
+; HARD-NEXT: ldd [%fp+-8], %f4
+; HARD-NEXT: ldd [%fp+-16], %f6
+; HARD-NEXT: ldd [%fp+-24], %f8
+; HARD-NEXT: fstod %f1, %f10
+; HARD-NEXT: faddd %f4, %f10, %f4
+; HARD-NEXT: faddd %f6, %f4, %f4
+; HARD-NEXT: faddd %f8, %f4, %f4
+; HARD-NEXT: faddd %f2, %f4, %f2
+; HARD-NEXT: fstod %f0, %f0
+; HARD-NEXT: faddd %f0, %f2, %f0
+; SOFT: save %sp, -96, %sp
+; SOFT: ld [%fp+104], %l0
+; SOFT-NEXT: ld [%fp+96], %l1
+; SOFT-NEXT: ld [%fp+100], %l2
+; SOFT-NEXT: ld [%fp+92], %l3
+; SOFT-NEXT:  mov  %i2, %o0
+; SOFT-NEXT: call __extendsfdf2
+; SOFT-NEXT: nop
+; SOFT-NEXT:  mov  %o0, %i2
+; SOFT-NEXT:  mov  %o1, %g2
+; SOFT-NEXT:  mov  %i0, %o0
+; SOFT-NEXT:  mov  %i1, %o1
+; SOFT-NEXT:  mov  %i2, %o2
+; SOFT-NEXT:  mov  %g2, %o3
+; SOFT-NEXT:  call __adddf3
+; SOFT-NEXT:  nop
+; SOFT-NEXT:  mov  %o0, %i0
+; SOFT-NEXT:  mov  %o1, %i1
+; SOFT-NEXT:  mov  %i3, %o0
+; SOFT-NEXT:  mov  %i4, %o1
+; SOFT-NEXT:  mov  %i0, %o2
+; SOFT-NEXT:  mov  %i1, %o3
+; SOFT-NEXT:  call __adddf3
+; SOFT-NEXT:  nop
+; SOFT-NEXT:  mov  %o0, %i0
+; SOFT-NEXT:  mov  %o1, %i1
+; SOFT-NEXT:  mov  %i5, %o0
+; SOFT-NEXT:  mov  %l3, %o1
+; SOFT-NEXT:  mov  %i0, %o2
+; SOFT-NEXT:  mov  %i1, %o3
+; SOFT-NEXT:  call __adddf3
+; SOFT-NEXT:  nop
+; SOFT-NEXT:  mov  %o0, %i0
+; SOFT-NEXT:  mov  %o1, %i1
+; SOFT-NEXT:  mov  %l1, %o0
+; SOFT-NEXT:  mov  %l2, %o1
+; SOFT-NEXT:  mov  %i0, %o2
+; SOFT-NEXT:  mov  %i1, %o3
+; SOFT-NEXT:  call __adddf3
+; SOFT-NEXT:  nop
+; SOFT-NEXT:  mov  %o0, %i0
+; SOFT-NEXT:  mov  %o1, %i1
+; SOFT-NEXT:  mov  %l0, %o0
+; SOFT-NEXT:  call __extendsfdf2
+; SOFT-NEXT:  nop
+; SOFT-NEXT:  mov  %i0, %o2
+; SOFT-NEXT:  mov  %i1, %o3
+; SOFT-NEXT:  call __adddf3
+; SOFT-NEXT:  nop
+; SOFT-NEXT:  mov  %o0, %i0
+; SOFT-NEXT:  mov  %o1, %i1
+; CHECK: restore
 define double @floatarg(double %a0,   ; %i0,%i1
                         float %a1,    ; %i2
                         double %a2,   ; %i3, %i4
                         double %a3,   ; %i5, [%fp+92] (using 4 bytes)
                         double %a4,   ; [%fp+96] (using 8 bytes)
                         float %a5) {  ; [%fp+104] (using 4 bytes)
   %d1 = fpext float %a1 to double
   %s1 = fadd double %a0, %d1
   %s2 = fadd double %a2, %s1
   %s3 = fadd double %a3, %s2
   %s4 = fadd double %a4, %s3
   %d5 = fpext float %a5 to double
   %s5 = fadd double %d5, %s4
   ret double %s5
 }
 
 ; CHECK-LABEL: call_floatarg:
-; CHECK: save %sp, -112, %sp
-; CHECK: mov %i2, %o1
-; CHECK-NEXT: mov %i1, %o0
-; CHECK-NEXT: st %i0, [%sp+104]
-; CHECK-NEXT: std %o0, [%sp+96]
-; CHECK-NEXT: st %o1, [%sp+92]
-; CHECK-NEXT: mov %i0, %o2
-; CHECK-NEXT: mov %o0, %o3
-; CHECK-NEXT: mov %o1, %o4
-; CHECK-NEXT: mov %o0, %o5
-; CHECK-NEXT: call floatarg
-; CHECK: std %f0, [%i4]
+; HARD: save %sp, -112, %sp
+; HARD: mov %i2, %o1
+; HARD-NEXT: mov %i1, %o0
+; HARD-NEXT: st %i0, [%sp+104]
+; HARD-NEXT: std %o0, [%sp+96]
+; HARD-NEXT: st %o1, [%sp+92]
+; HARD-NEXT: mov %i0, %o2
+; HARD-NEXT: mov %o0, %o3
+; HARD-NEXT: mov %o1, %o4
+; HARD-NEXT: mov %o0, %o5
+; HARD-NEXT: call floatarg
+; HARD: std %f0, [%i4]
+; SOFT: st %i0, [%sp+104]
+; SOFT-NEXT:  st %i2, [%sp+100]
+; SOFT-NEXT:  st %i1, [%sp+96]
+; SOFT-NEXT:  st %i2, [%sp+92]
+; SOFT-NEXT:  mov  %i1, %o0
+; SOFT-NEXT:  mov  %i2, %o1
+; SOFT-NEXT:  mov  %i0, %o2
+; SOFT-NEXT:  mov  %i1, %o3
+; SOFT-NEXT:  mov  %i2, %o4
+; SOFT-NEXT:  mov  %i1, %o5
+; SOFT-NEXT:  call floatarg
+; SOFT:  std %o0, [%i4]
 ; CHECK: restore
 define void @call_floatarg(float %f1, double %d2, float %f5, double *%p) {
   %r = call double @floatarg(double %d2, float %f1, double %d2, double %d2,
                              double %d2, float %f1)
   store double %r, double* %p
   ret void
 }
 

test/CodeGen/SPARC/64abi.ll

-; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s
+; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s --check-prefix=CHECK --check-prefix=HARD
+; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc -mattr=soft-float | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT
 
 ; CHECK-LABEL: intarg:
 ; The save/restore frame is not strictly necessary here, but we would need to
 ; refer to %o registers instead.
 ; CHECK: save %sp, -128, %sp
 ; CHECK: ldx [%fp+2231], [[R2:%[gilo][0-7]]]
 ; CHECK: ld [%fp+2227], [[R1:%[gilo][0-7]]]
 ; CHECK: stb %i0, [%i4]

 ; CHECK-NOT: add %sp
 ; CHECK: restore
 define void @call_intarg(i32 %i0, i8* %i1) {
   call void @intarg(i8 0, i8 1, i16 2, i32 3, i8* undef, i32 5, i32 %i0, i8* %i1)
   ret void
 }
 
 ; CHECK-LABEL: floatarg:
-; CHECK: save %sp, -128, %sp
-; CHECK: ld [%fp+2307], [[F:%f[0-9]+]]
-; CHECK: fstod %f1,
-; CHECK: faddd %f2,
-; CHECK: faddd %f4,
-; CHECK: faddd %f6,
-; CHECK: fadds %f31, [[F]]
+; HARD: save %sp, -128, %sp
+; HARD: ld [%fp+2307], [[F:%f[0-9]+]]
+; HARD: fstod %f1,
+; HARD: faddd %f2,
+; HARD: faddd %f4,
+; HARD: faddd %f6,
+; HARD: fadds %f31, [[F]]
+; SOFT: save %sp, -176, %sp
+; SOFT: srl %i0, 0, %o0
+; SOFT-NEXT: call __extendsfdf2
+; SOFT: mov  %o0, %i0
+; SOFT: mov  %i1, %o0
+; SOFT: mov  %i2, %o0
+; SOFT: mov  %i3, %o0
+; SOFT: ld [%fp+2299], %o0
+; SOFT: ld [%fp+2307], %o1
 define double @floatarg(float %a0,    ; %f1
                         double %a1,   ; %d2
                         double %a2,   ; %d4
                         double %a3,   ; %d6
                         float %a4,    ; %f9
                         float %a5,    ; %f11
                         float %a6,    ; %f13
                         float %a7,    ; %f15
define double @floatarg(float %a0,    ; %f1
   %d16 = fpext float %s16 to double
   %s17 = fadd double %d16, %s3
   ret double %s17
 }
 
 ; CHECK-LABEL: call_floatarg:
 ; CHECK: save %sp, -272, %sp
 ; Store 8 bytes in full slot.
-; CHECK: std %f2, [%sp+2311]
+; HARD: std %f2, [%sp+2311]
 ; Store 4 bytes, right-aligned in slot.
-; CHECK: st %f1, [%sp+2307]
-; CHECK: fmovd %f2, %f4
+; HARD: st %f1, [%sp+2307]
+; HARD: fmovd %f2, %f4
+; SOFT: stx %i1, [%sp+2311]
+; SOFT: stx %i0, [%sp+2303]
+; SOFT: stx %i2, [%sp+2295]
+; SOFT: stx %i2, [%sp+2287]
+; SOFT: stx %i2, [%sp+2279]
+; SOFT: stx %i2, [%sp+2271]
+; SOFT: stx %i2, [%sp+2263]
+; SOFT: stx %i2, [%sp+2255]
+; SOFT: stx %i2, [%sp+2247]
+; SOFT: stx %i2, [%sp+2239]
+; SOFT: stx %i2, [%sp+2231]
+; SOFT: stx %i2, [%sp+2223]
+; SOFT: mov  %i2, %o0
+; SOFT: mov  %i1, %o1
+; SOFT: mov  %i1, %o2
+; SOFT: mov  %i1, %o3
+; SOFT: mov  %i2, %o4
+; SOFT: mov  %i2, %o5
 ; CHECK: call floatarg
 ; CHECK-NOT: add %sp
 ; CHECK: restore
+
 define void @call_floatarg(float %f1, double %d2, float %f5, double *%p) {
   %r = call double @floatarg(float %f5, double %d2, double %d2, double %d2,
                              float %f5, float %f5,  float %f5,  float %f5,
                              float %f5, float %f5,  float %f5,  float %f5,
                              float %f5, float %f5,  float %f5,  float %f5,
                              float %f1, double %d2)
   store double %r, double* %p
   ret void
 }
 
 ; CHECK-LABEL: mixedarg:
 ; CHECK: ldx [%fp+2247]
 ; CHECK: ldx [%fp+2231]
-; CHECK: fstod %f3
-; CHECK: faddd %f6
-; CHECK: faddd %f16
+; SOFT: ldx [%fp+2239], %i0
+; HARD: fstod %f3
+; HARD: faddd %f6
+; HARD: faddd %f16
+; SOFT: mov  %o0, %i1
+; SOFT-NEXT: mov  %i3, %o0
+; SOFT-NEXT: mov  %i1, %o1
+; SOFT-NEXT: call __adddf3
+; SOFT: mov  %o0, %i1
+; SOFT-NEXT: mov  %i0, %o0
+; SOFT-NEXT: mov  %i1, %o1
+; SOFT-NEXT: call __adddf3
+; HARD: std %f0, [%i1]
+; SOFT: stx %o0, [%i5]
+
 define void @mixedarg(i8 %a0,      ; %i0
                       float %a1,   ; %f3
                       i16 %a2,     ; %i2
                       double %a3,  ; %d6
                       i13 %a4,     ; %i4
                       float %a5,   ; %f11
                       i64 %a6,     ; [%fp+BIAS+176]
                       double *%a7, ; [%fp+BIAS+184]
                       double %a8,  ; %d16
                       i16* %a9) {  ; [%fp+BIAS+200]
   %d1 = fpext float %a1 to double
   %s3 = fadd double %a3, %d1
   %s8 = fadd double %a8, %s3
   store double %s8, double* %a7
   store i16 %a2, i16* %a9
   ret void
 }
 
 ; CHECK-LABEL: call_mixedarg:
 ; CHECK: stx %i2, [%sp+2247]
+; SOFT:  stx %i1, [%sp+2239]
 ; CHECK: stx %i0, [%sp+2223]
-; CHECK: fmovd %f2, %f6
-; CHECK: fmovd %f2, %f16
+; HARD: fmovd %f2, %f6
+; HARD: fmovd %f2, %f16
+; SOFT: mov  %i1, %o3
 ; CHECK: call mixedarg
 ; CHECK-NOT: add %sp
 ; CHECK: restore
+
 define void @call_mixedarg(i64 %i0, double %f2, i16* %i2) {
   call void @mixedarg(i8 undef,
                       float undef,
                       i16 undef,
                       double %f2,
                       i13 undef,
                       float undef,
                       i64 %i0,
                       double* undef,
                       double %f2,
                       i16* %i2)
   ret void
 }
 
 ; The inreg attribute is used to indicate 32-bit sized struct elements that
 ; share an 8-byte slot.
 ; CHECK-LABEL: inreg_fi:
-; CHECK: fstoi %f1
-; CHECK: srlx %i0, 32, [[R:%[gilo][0-7]]]
+; SOFT: srlx %i0, 32, [[R:%[gilo][0-7]]]
+; HARD: fstoi %f1
+; SOFT: call __fixsfsi
+; HARD: srlx %i0, 32, [[R:%[gilo][0-7]]]
 ; CHECK: sub [[R]],
 define i32 @inreg_fi(i32 inreg %a0,     ; high bits of %i0
                      float inreg %a1) { ; %f1
   %b1 = fptosi float %a1 to i32
   %rv = sub i32 %a0, %b1
   ret i32 %rv
 }
 
 ; CHECK-LABEL: call_inreg_fi:
 ; Allocate space for 6 arguments, even when only 2 are used.
 ; CHECK: save %sp, -176, %sp
-; CHECK: sllx %i1, 32, %o0
-; CHECK: fmovs %f5, %f1
+; HARD:  sllx %i1, 32, %o0
+; HARD:  fmovs %f5, %f1
+; SOFT:  srl %i2, 0, %i0
+; SOFT:  sllx %i1, 32, %i1
+; SOFT:  or %i1, %i0, %o0
 ; CHECK: call inreg_fi
 define void @call_inreg_fi(i32* %p, i32 %i1, float %f5) {
   %x = call i32 @inreg_fi(i32 %i1, float %f5)
   ret void
 }
 
 ; CHECK-LABEL: inreg_ff:
-; CHECK: fsubs %f0, %f1, %f0
+; HARD: fsubs %f0, %f1, %f0
+; SOFT: srlx %i0, 32, %o0
+; SOFT: srl %i0, 0, %o1
+; SOFT: call __subsf3
 define float @inreg_ff(float inreg %a0,   ; %f0
                        float inreg %a1) { ; %f1
   %rv = fsub float %a0, %a1
   ret float %rv
 }
 
 ; CHECK-LABEL: call_inreg_ff:
-; CHECK: fmovs %f3, %f0
-; CHECK: fmovs %f5, %f1
+; HARD: fmovs %f3, %f0
+; HARD: fmovs %f5, %f1
+; SOFT: srl %i2, 0, %i0
+; SOFT: sllx %i1, 32, %i1
+; SOFT: or %i1, %i0, %o0
 ; CHECK: call inreg_ff
 define void @call_inreg_ff(i32* %p, float %f3, float %f5) {
   %x = call float @inreg_ff(float %f3, float %f5)
   ret void
 }
 
 ; CHECK-LABEL: inreg_if:
-; CHECK: fstoi %f0
+; HARD: fstoi %f0
+; SOFT: srlx %i0, 32, %o0
+; SOFT: call __fixsfsi
 ; CHECK: sub %i0
 define i32 @inreg_if(float inreg %a0, ; %f0
                      i32 inreg %a1) { ; low bits of %i0
   %b0 = fptosi float %a0 to i32
   %rv = sub i32 %a1, %b0
   ret i32 %rv
 }
 
 ; CHECK-LABEL: call_inreg_if:
-; CHECK: fmovs %f3, %f0
-; CHECK: mov %i2, %o0
+; HARD: fmovs %f3, %f0
+; HARD: mov %i2, %o0
+; SOFT: srl %i2, 0, %i0
+; SOFT: sllx %i1, 32, %i1
+; SOFT: or %i1, %i0, %o0
 ; CHECK: call inreg_if
 define void @call_inreg_if(i32* %p, float %f3, i32 %i2) {
   %x = call i32 @inreg_if(float %f3, i32 %i2)
   ret void
 }
 
 ; The frontend shouldn't do this. Just pass i64 instead.
 ; CHECK-LABEL: inreg_ii:
define void @call_ret_i64_pair(i64* %i0) {
   %e1 = extractvalue { i64, i64 } %rv, 1
   store i64 %e1, i64* %i0
   ret void
 }
 
 ; This is not a C struct, the i32 member uses 8 bytes, but the float only 4.
 ; CHECK-LABEL: ret_i32_float_pair:
 ; CHECK: ld [%i2], %i0
-; CHECK: ld [%i3], %f2
+; HARD: ld [%i3], %f2
+; SOFT: ld [%i3], %i1
 define { i32, float } @ret_i32_float_pair(i32 %a0, i32 %a1,
                                           i32* %p, float* %q) {
   %r1 = load i32, i32* %p
   %rv1 = insertvalue { i32, float } undef, i32 %r1, 0
   store i32 0, i32* %p
   %r2 = load float, float* %q
   %rv2 = insertvalue { i32, float } %rv1, float %r2, 1
   ret { i32, float } %rv2
 }
 
 ; CHECK-LABEL: call_ret_i32_float_pair:
 ; CHECK: call ret_i32_float_pair
 ; CHECK: st %o0, [%i0]
-; CHECK: st %f2, [%i1]
+; HARD: st %f2, [%i1]
+; SOFT: st %o1, [%i1]
 define void @call_ret_i32_float_pair(i32* %i0, float* %i1) {
   %rv = call { i32, float } @ret_i32_float_pair(i32 undef, i32 undef,
                                                 i32* undef, float* undef)
   %e0 = extractvalue { i32, float } %rv, 0
   store i32 %e0, i32* %i0
   %e1 = extractvalue { i32, float } %rv, 1
   store float %e1, float* %i1
   ret void
 }
 
 ; This is a C struct, each member uses 4 bytes.
 ; CHECK-LABEL: ret_i32_float_packed:
 ; CHECK: ld [%i2], [[R:%[gilo][0-7]]]
-; CHECK: ld [%i3], %f1
+; HARD: ld [%i3], %f1
+; SOFT: ld [%i3], %i1
 ; CHECK: sllx [[R]], 32, %i0
 define inreg { i32, float } @ret_i32_float_packed(i32 %a0, i32 %a1,
                                                   i32* %p, float* %q) {
   %r1 = load i32, i32* %p
   %rv1 = insertvalue { i32, float } undef, i32 %r1, 0
   store i32 0, i32* %p
   %r2 = load float, float* %q
   %rv2 = insertvalue { i32, float } %rv1, float %r2, 1
   ret { i32, float } %rv2
 }
 
 ; CHECK-LABEL: call_ret_i32_float_packed:
 ; CHECK: call ret_i32_float_packed
 ; CHECK: srlx %o0, 32, [[R:%[gilo][0-7]]]
 ; CHECK: st [[R]], [%i0]
-; CHECK: st %f1, [%i1]
+; HARD: st %f1, [%i1]
+; SOFT: st %o0, [%i1]
 define void @call_ret_i32_float_packed(i32* %i0, float* %i1) {
   %rv = call { i32, float } @ret_i32_float_packed(i32 undef, i32 undef,
                                                   i32* undef, float* undef)
   %e0 = extractvalue { i32, float } %rv, 0
   store i32 %e0, i32* %i0
   %e1 = extractvalue { i32, float } %rv, 1
   store float %e1, float* %i1
   ret void
entry:
   %buffer1.sub = getelementptr inbounds [16384 x i8], [16384 x i8]* %buffer1, i32 0, i32 0
   %0 = call i32 @use_buf(i32 16384, i8* %buffer1.sub)
   ret i32 %0
 }
 
 declare i32 @use_buf(i32, i8*)
 
 ; CHECK-LABEL: test_fp128_args:
-; CHECK-DAG:   std %f0, [%fp+{{.+}}]
-; CHECK-DAG:   std %f2, [%fp+{{.+}}]
-; CHECK-DAG:   std %f6, [%fp+{{.+}}]
-; CHECK-DAG:   std %f4, [%fp+{{.+}}]
-; CHECK:       add %fp, [[Offset:[0-9]+]], %o0
-; CHECK:       call _Qp_add
-; CHECK:       ldd [%fp+[[Offset]]], %f0
+; HARD-DAG:   std %f0, [%fp+{{.+}}]
+; HARD-DAG:   std %f2, [%fp+{{.+}}]
+; HARD-DAG:   std %f6, [%fp+{{.+}}]
+; HARD-DAG:   std %f4, [%fp+{{.+}}]
+; HARD:       add %fp, [[Offset:[0-9]+]], %o0
+; HARD:       call _Qp_add
+; HARD:       ldd [%fp+[[Offset]]], %f0
+; SOFT-DAG:       mov  %i0, %o0
+; SOFT-DAG:       mov  %i1, %o1
+; SOFT-DAG:       mov  %i2, %o2
+; SOFT-DAG:       mov  %i3, %o3
+; SOFT:           call __addtf3
+; SOFT:           mov  %o0, %i0
+; SOFT:           mov  %o1, %i1
+
 define fp128 @test_fp128_args(fp128 %a, fp128 %b) {
 entry:
   %0 = fadd fp128 %a, %b
   ret fp128 %0
 }
 
 declare i64 @receive_fp128(i64 %a, ...)
 
 ; CHECK-LABEL: test_fp128_variable_args:
-; CHECK-DAG:   std %f4, [%sp+[[Offset0:[0-9]+]]]
-; CHECK-DAG:   std %f6, [%sp+[[Offset1:[0-9]+]]]
-; CHECK-DAG:   ldx [%sp+[[Offset0]]], %o2
-; CHECK-DAG:   ldx [%sp+[[Offset1]]], %o3
-; CHECK:       call receive_fp128
+; HARD-DAG:   std %f4, [%sp+[[Offset0:[0-9]+]]]
+; HARD-DAG:   std %f6, [%sp+[[Offset1:[0-9]+]]]
+; HARD-DAG:   ldx [%sp+[[Offset0]]], %o2
+; HARD-DAG:   ldx [%sp+[[Offset1]]], %o3
+; SOFT-DAG:   mov  %i0, %o0
+; SOFT-DAG:   mov  %i1, %o1
+; SOFT-DAG:   mov  %i2, %o2
+; CHECK:      call receive_fp128
 define i64 @test_fp128_variable_args(i64 %a, fp128 %b) {
 entry:
   %0 = call i64 (i64, ...) @receive_fp128(i64 %a, fp128 %b)
   ret i64 %0
 }
 
 ; CHECK-LABEL: test_call_libfunc:
-; CHECK:       st %f1, [%fp+[[Offset0:[0-9]+]]]
-; CHECK:       fmovs %f3, %f1
-; CHECK:       call cosf
-; CHECK:       st %f0, [%fp+[[Offset1:[0-9]+]]]
-; CHECK:       ld [%fp+[[Offset0]]], %f1
-; CHECK:       call sinf
-; CHECK:       ld [%fp+[[Offset1]]], %f1
-; CHECK:       fmuls %f1, %f0, %f0
+; HARD:   st %f1, [%fp+[[Offset0:[0-9]+]]]
+; HARD:   fmovs %f3, %f1
+; SOFT:   srl %i1, 0, %o0
+; CHECK:  call cosf
+; HARD:   st %f0, [%fp+[[Offset1:[0-9]+]]]
+; HARD:   ld [%fp+[[Offset0]]], %f1
+; SOFT:   mov  %o0, %i1
+; SOFT:   srl %i0, 0, %o0
+; CHECK:  call sinf
+; HARD:   ld [%fp+[[Offset1]]], %f1
+; HARD:   fmuls %f1, %f0, %f0
+; SOFT:   mov  %o0, %i0
+; SOFT:   mov  %i1, %o0
+; SOFT:   mov  %i0, %o1
+; SOFT:   call __mulsf3
+; SOFT:   sllx %o0, 32, %i0
 
 define inreg float @test_call_libfunc(float %arg0, float %arg1) {
 entry:
   %0 = tail call inreg float @cosf(float %arg1)
   %1 = tail call inreg float @sinf(float %arg0)
   %2 = fmul float %0, %1
   ret float %2
 }
 
 declare inreg float @cosf(float %arg) readnone nounwind
 declare inreg float @sinf(float %arg) readnone nounwind
-
-

test/CodeGen/SPARC/soft-float.ll

+; RUN: llc -march=sparc -mattr=soft-float -O0 < %s | FileCheck %s
+
+; Arithmetic functions
+
+define float @test_addsf3(float %a, float %b) #0 {
+  ; CHECK-LABEL:  test_addsf3:
+  ; CHECK:        call __addsf3
+  %add = fadd float %a, %b
+  ret float %add
+}
+
+define double @test_adddf3(double %a, double %b) #0 {
+  ; CHECK-LABEL:  test_adddf3:
+  ; CHECK:        call __adddf3
+  %add = fadd double %a, %b
+  ret double %add
+}
+
+define fp128 @test_addtf3(fp128 %a, fp128 %b) #0 {
+  ; CHECK-LABEL:  test_addtf3:
+  ; CHECK:        call __addtf3
+  %add = fadd fp128 %a, %b
+  ret fp128 %add
+}
+
+define float @test_mulsf3(float %a, float %b) #0 {
+  ; CHECK-LABEL:  test_mulsf3:
+  ; CHECK:        call __mulsf3
+  %mul = fmul float %a, %b
+  ret float %mul
+}
+
+define double @test_muldf3(double %a, double %b) #0 {
+  ; CHECK-LABEL:  test_muldf3:
+  ; CHECK:        call __muldf3
+  %mul = fmul double %a, %b
+  ret double %mul
+}
+
+define fp128 @test_multf3(fp128 %a, fp128 %b) #0 {
+  ; CHECK-LABEL:  test_multf3:
+  ; CHECK:        call __multf3
+  %mul = fmul fp128 %a, %b
+  ret fp128 %mul
+}
+
+define float @test_subsf3(float %a, float %b) #0 {
+  ; CHCEK-LABEL:  test_subsf3:
+  ; CHECK:        call __subsf3
+  %sub = fsub float %a, %b
+  ret float %sub
+}
+
+define double @test_subdf3(double %a, double %b) #0 {
+  ; CHCEK-LABEL:  test_subdf3:
+  ; CHECK:        call __subdf3
+  %sub = fsub double %a, %b
+  ret double %sub
+}
+
+define fp128 @test_subtf3(fp128 %a, fp128 %b) #0 {
+  ; CHCEK-LABEL:  test_subtf3:
+  ; CHECK:        call __subtf3
+  %sub = fsub fp128 %a, %b
+  ret fp128 %sub
+}
+
+define float @test_divsf3(float %a, float %b) #0 {
+  ; CHECK-LABEL:  test_divsf3:
+  ; CHECK:        call __divsf3
+  %div = fdiv float %a, %b
+  ret float %div
+}
+
+define double @test_divdf3(double %a, double %b) #0 {
+  ; CHECK-LABEL:  test_divdf3:
+  ; CHECK:        call __divdf3
+  %div = fdiv double %a, %b
+  ret double %div
+}
+
+define fp128 @test_divtf3(fp128 %a, fp128 %b) #0 {
+  ; CHECK-LABEL:  test_divtf3:
+  ; CHECK:        call __divtf3
+  %div = fdiv fp128 %a, %b
+  ret fp128 %div
+}
+
+; Comparison functions
+define i1 @test_unordsf2(float %a, float %b) #0 {
+  ; CHECK-LABEL:  test_unordsf2:
+  ; CHECK:        call __unordsf2
+  %cmp = fcmp uno float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_unorddf2(double %a, double %b) #0 {
+  ; CHECK-LABEL:  test_unorddf2:
+  ; CHECK:        call __unorddf2
+  %cmp = fcmp uno double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_unordtf2(fp128 %a, fp128 %b) #0 {
+  ; CHECK-LABEL:  test_unordtf2:
+  ; CHECK:        call __unordtf2
+  %cmp = fcmp uno fp128 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_eqsf2(float %a, float %b) #0 {
+  ; CHECK-LABEL:  test_eqsf2:
+  ; CHECK:        call __eqsf2
+  %cmp = fcmp oeq float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_eqdf2(double %a, double %b) #0 {
+  ; CHECK-LABEL:  test_eqdf2:
+  ; CHECK:        call __eqdf2
+  %cmp = fcmp oeq double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_eqtf2(fp128 %a, fp128 %b) #0 {
+  ; CHECK-LABEL:  test_eqtf2:
+  ; CHECK:        call __eqtf2
+  %cmp = fcmp oeq fp128 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_nesf2(float %a, float %b) #0 {
+  ; CHECK-LABEL:  test_nesf2:
+  ; CHECK:        call __nesf2
+  %cmp = fcmp une float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_nedf2(double %a, double %b) #0 {
+  ; CHECK-LABEL:  test_nedf2:
+  ; CHECK:        call __nedf2
+  %cmp = fcmp une double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_netf2(fp128 %a, fp128 %b) #0 {
+  ; CHECK-LABEL:  test_netf2:
+  ; CHECK:        call __netf2
+  %cmp = fcmp une fp128 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_gesf2(float %a, float %b) #0 {
+  ; CHECK-LABLE:  test_gesf2:
+  ; CHECK:        call __gesf2
+  %cmp = fcmp oge float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_gedf2(double %a, double %b) #0 {
+  ; CHECK-LABLE:  test_gedf2:
+  ; CHECK:        call __gedf2
+  %cmp = fcmp oge double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_getf2(fp128 %a, fp128 %b) #0 {
+  ; CHECK-LABLE:  test_getf2:
+  ; CHECK:        call __getf2
+  %cmp = fcmp oge fp128 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_ltsf2(float %a, float %b) #0 {
+  ; CHECK-LABEL:  test_ltsf2:
+  ; CHECK:        call __ltsf2
+  %cmp = fcmp olt float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_ltdf2(double %a, double %b) #0 {
+  ; CHECK-LABEL:  test_ltdf2:
+  ; CHECK:        call __ltdf2
+  %cmp = fcmp olt double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_lttf2(fp128 %a, fp128 %b) #0 {
+  ; CHECK-LABEL:  test_lttf2:
+  ; CHECK:        call __lttf2
+  %cmp = fcmp olt fp128 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_lesf2(float %a, float %b) #0 {
+  ; CHECK-LABEL:  test_lesf2:
+  ; CHECK:        call __lesf2
+  %cmp = fcmp ole float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_ledf2(double %a, double %b) #0 {
+  ; CHECK-LABEL:  test_ledf2:
+  ; CHECK:        call __ledf2
+  %cmp = fcmp ole double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_letf2(fp128 %a, fp128 %b) #0 {
+  ; CHECK-LABEL:  test_letf2:
+  ; CHECK:        call __letf2
+  %cmp = fcmp ole fp128 %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_gtsf2(float %a, float %b) #0 {
+  ; CHECK-LABEL:  test_gtsf2:
+  ; CHECK:        call __gtsf2
+  %cmp = fcmp ogt float %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_gtdf2(double %a, double %b) #0 {
+  ; CHECK-LABEL:  test_gtdf2:
+  ; CHECK:        call __gtdf2
+  %cmp = fcmp ogt double %a, %b
+  ret i1 %cmp
+}
+
+define i1 @test_gttf2(fp128 %a, fp128 %b) #0 {
+  ; CHECK-LABEL:  test_gttf2:
+  ; CHECK:        call __gttf2
+  %cmp = fcmp ogt fp128 %a, %b
+  ret i1 %cmp
+}