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Differential D18944

[DAGCombiner] Fold xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) anytime before LegalizeVectorOprs
ClosedPublic

Authored by RKSimon on Apr 10 2016, 8:19 AM.

Details

Reviewers
spatel
qcolombet
delena
andreadb
Commits
rG82e54871d03e: [DAGCombiner] Fold xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))…
rL265998: [DAGCombiner] Fold xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))…
Summary

xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) was only being combined at the AfterLegalizeTypes stage, this patch permits the combine to occur anytime before then as well.

My aim with this to improve the ability to recognise bitmasks that can be coverted to shuffles.

Elena - I had to modify a number of AVX512 mask tests as the basic bitcast to/from scalar pattern was being stripped out preventing testing of the mmask bitops. By replacing the bitcasts with loads I can get almost the same result.

Diff Detail

Repository
rL LLVM

Event Timeline

RKSimon updated this revision to Diff 53179.Apr 10 2016, 8:19 AM
RKSimon retitled this revision from to [DAGCombiner] Fold xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) anytime before LegalizeVectorOprs.
RKSimon updated this object.
RKSimon added reviewers: qcolombet, delena, spatel, andreadb.
RKSimon set the repository for this revision to rL LLVM.
RKSimon added a subscriber: llvm-commits.
delena added inline comments.Apr 10 2016, 10:31 AM
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
2776 ↗(On Diff #53179)

I'm not sure that it is safe for illegal types. You don't cover this in the tests.
If you want to do the transformation before type promotion, you, probably, should check that the types are legal.

test/CodeGen/X86/avx512-mask-op.ll
95 ↗(On Diff #53179)

What code will be generated on the original test?
I'd prefer do not change the existing tests.

RKSimon mentioned this in rL265925: [X86] Added widening tests for and/xor/or bit operations.Apr 11 2016, 3:22 AM
RKSimon mentioned this in rL265930: [X86] Added extra widening tests for and/xor/or bit operations.Apr 11 2016, 4:16 AM
RKSimon updated this revision to Diff 53216.Apr 11 2016, 4:24 AM

Thanks Elena,

I've split the AVX512 mask tests - the old tests now perform the operations on the scalar unit (as that was what the masks have been bitcasted from), but the new memory tests perform the operations on the mask unit.

I've also added a number of widening/legalization tests to demonstrate the effect of permitting the combine to work on pre-legalized types.

delena accepted this revision.Apr 11 2016, 5:13 AM
delena edited edge metadata.

Thank you.

This revision is now accepted and ready to land.Apr 11 2016, 5:13 AM
Closed by commit rL265998: [DAGCombiner] Fold xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))… (authored by RKSimon). · Explain WhyApr 11 2016, 2:16 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
CodeGen/
SelectionDAG/
4 lines
test/
CodeGen/
X86/
78 lines
45 lines
52 lines
26 lines
75 lines
27 lines
1263 lines
1146 lines

Diff 53319

llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,759 Lines • ▼ Show 20 Lines SDValue ORNode = DAG.getNode(N->getOpcode(), SDLoc(N0),
N0.getOperand(0).getValueType(), N0.getOperand(0).getValueType(),
N0.getOperand(0), N1.getOperand(0)); N0.getOperand(0), N1.getOperand(0));
AddToWorklist(ORNode.getNode()); AddToWorklist(ORNode.getNode());
return DAG.getNode(N0.getOpcode(), SDLoc(N), VT, return DAG.getNode(N0.getOpcode(), SDLoc(N), VT,
ORNode, N0.getOperand(1)); ORNode, N0.getOperand(1));
} }
// Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B)) // Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
// Only perform this optimization after type legalization and before // Only perform this optimization up until type legalization, before
// LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by // LegalizeVectorOprs. LegalizeVectorOprs promotes vector operations by
// adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and // adding bitcasts. For example (xor v4i32) is promoted to (v2i64), and
// we don't want to undo this promotion. // we don't want to undo this promotion.
// We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper // We also handle SCALAR_TO_VECTOR because xor/or/and operations are cheaper
// on scalars. // on scalars.
if ((N0.getOpcode() == ISD::BITCAST || if ((N0.getOpcode() == ISD::BITCAST ||
N0.getOpcode() == ISD::SCALAR_TO_VECTOR) && N0.getOpcode() == ISD::SCALAR_TO_VECTOR) &&
Level == AfterLegalizeTypes) { Level <= AfterLegalizeTypes) {
SDValue In0 = N0.getOperand(0); SDValue In0 = N0.getOperand(0);
SDValue In1 = N1.getOperand(0); SDValue In1 = N1.getOperand(0);
EVT In0Ty = In0.getValueType(); EVT In0Ty = In0.getValueType();
EVT In1Ty = In1.getValueType(); EVT In1Ty = In1.getValueType();
SDLoc DL(N); SDLoc DL(N);
// If both incoming values are integers, and the original types are the // If both incoming values are integers, and the original types are the
// same. // same.
if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) { if (In0Ty.isInteger() && In1Ty.isInteger() && In0Ty == In1Ty) {
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llvm/trunk/test/CodeGen/X86/avx512-mask-op.ll

Show First 20 Lines • Show All 71 Lines • ▼ Show 20 Lines; SKX-NEXT: retq
%ret = bitcast <8 x i1> %m1 to i8 %ret = bitcast <8 x i1> %m1 to i8
store i8 %ret, i8* %ptr, align 4 store i8 %ret, i8* %ptr, align 4
ret void ret void
} }
define i16 @mand16(i16 %x, i16 %y) { define i16 @mand16(i16 %x, i16 %y) {
; CHECK-LABEL: mand16: ; CHECK-LABEL: mand16:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edi, %k0 ; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: kmovw %esi, %k1 ; CHECK-NEXT: xorl %esi, %eax
; CHECK-NEXT: andl %esi, %edi
; CHECK-NEXT: orl %eax, %edi
; CHECK-NEXT: movw %di, %ax
; CHECK-NEXT: retq
%ma = bitcast i16 %x to <16 x i1>
%mb = bitcast i16 %y to <16 x i1>
%mc = and <16 x i1> %ma, %mb
%md = xor <16 x i1> %ma, %mb
%me = or <16 x i1> %mc, %md
%ret = bitcast <16 x i1> %me to i16
ret i16 %ret
}
define i16 @mand16_mem(<16 x i1>* %x, <16 x i1>* %y) {
; CHECK-LABEL: mand16_mem:
; CHECK: ## BB#0:
; CHECK-NEXT: kmovw (%rdi), %k0
; CHECK-NEXT: kmovw (%rsi), %k1
; CHECK-NEXT: kandw %k1, %k0, %k2 ; CHECK-NEXT: kandw %k1, %k0, %k2
; CHECK-NEXT: kxorw %k1, %k0, %k0 ; CHECK-NEXT: kxorw %k1, %k0, %k0
; CHECK-NEXT: korw %k0, %k2, %k0 ; CHECK-NEXT: korw %k0, %k2, %k0
; CHECK-NEXT: kmovw %k0, %eax ; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%ma = bitcast i16 %x to <16 x i1> %ma = load <16 x i1>, <16 x i1>* %x
%mb = bitcast i16 %y to <16 x i1> %mb = load <16 x i1>, <16 x i1>* %y
%mc = and <16 x i1> %ma, %mb %mc = and <16 x i1> %ma, %mb
%md = xor <16 x i1> %ma, %mb %md = xor <16 x i1> %ma, %mb
%me = or <16 x i1> %mc, %md %me = or <16 x i1> %mc, %md
%ret = bitcast <16 x i1> %me to i16 %ret = bitcast <16 x i1> %me to i16
ret i16 %ret ret i16 %ret
} }
define i8 @shuf_test1(i16 %v) nounwind { define i8 @shuf_test1(i16 %v) nounwind {
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false: false:
ret void ret void
} }
define <16 x i8> @test8(<16 x i32>%a, <16 x i32>%b, i32 %a1, i32 %b1) { define <16 x i8> @test8(<16 x i32>%a, <16 x i32>%b, i32 %a1, i32 %b1) {
; KNL-LABEL: test8: ; KNL-LABEL: test8:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: vpxord %zmm2, %zmm2, %zmm2 ; KNL-NEXT: vpxord %zmm2, %zmm2, %zmm2
; KNL-NEXT: cmpl %esi, %edi ; KNL-NEXT: cmpl %esi, %edi
; KNL-NEXT: jg LBB14_1 ; KNL-NEXT: jg LBB15_1
; KNL-NEXT: ## BB#2: ; KNL-NEXT: ## BB#2:
; KNL-NEXT: vpcmpltud %zmm2, %zmm1, %k1 ; KNL-NEXT: vpcmpltud %zmm2, %zmm1, %k1
; KNL-NEXT: jmp LBB14_3 ; KNL-NEXT: jmp LBB15_3
; KNL-NEXT: LBB14_1: ; KNL-NEXT: LBB15_1:
; KNL-NEXT: vpcmpgtd %zmm2, %zmm0, %k1 ; KNL-NEXT: vpcmpgtd %zmm2, %zmm0, %k1
; KNL-NEXT: LBB14_3: ; KNL-NEXT: LBB15_3:
; KNL-NEXT: vpbroadcastd {{.*}}(%rip), %zmm0 {%k1} {z} ; KNL-NEXT: vpbroadcastd {{.*}}(%rip), %zmm0 {%k1} {z}
; KNL-NEXT: vpmovdb %zmm0, %xmm0 ; KNL-NEXT: vpmovdb %zmm0, %xmm0
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test8: ; SKX-LABEL: test8:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: vpxord %zmm2, %zmm2, %zmm2 ; SKX-NEXT: vpxord %zmm2, %zmm2, %zmm2
; SKX-NEXT: cmpl %esi, %edi ; SKX-NEXT: cmpl %esi, %edi
; SKX-NEXT: jg LBB14_1 ; SKX-NEXT: jg LBB15_1
; SKX-NEXT: ## BB#2: ; SKX-NEXT: ## BB#2:
; SKX-NEXT: vpcmpltud %zmm2, %zmm1, %k0 ; SKX-NEXT: vpcmpltud %zmm2, %zmm1, %k0
; SKX-NEXT: vpmovm2b %k0, %xmm0 ; SKX-NEXT: vpmovm2b %k0, %xmm0
; SKX-NEXT: retq ; SKX-NEXT: retq
; SKX-NEXT: LBB14_1: ; SKX-NEXT: LBB15_1:
; SKX-NEXT: vpcmpgtd %zmm2, %zmm0, %k0 ; SKX-NEXT: vpcmpgtd %zmm2, %zmm0, %k0
; SKX-NEXT: vpmovm2b %k0, %xmm0 ; SKX-NEXT: vpmovm2b %k0, %xmm0
; SKX-NEXT: retq ; SKX-NEXT: retq
%cond = icmp sgt i32 %a1, %b1 %cond = icmp sgt i32 %a1, %b1
%cmp1 = icmp sgt <16 x i32> %a, zeroinitializer %cmp1 = icmp sgt <16 x i32> %a, zeroinitializer
%cmp2 = icmp ult <16 x i32> %b, zeroinitializer %cmp2 = icmp ult <16 x i32> %b, zeroinitializer
%mix = select i1 %cond, <16 x i1> %cmp1, <16 x i1> %cmp2 %mix = select i1 %cond, <16 x i1> %cmp1, <16 x i1> %cmp2
%res = sext <16 x i1> %mix to <16 x i8> %res = sext <16 x i1> %mix to <16 x i8>
ret <16 x i8> %res ret <16 x i8> %res
} }
define <16 x i1> @test9(<16 x i1>%a, <16 x i1>%b, i32 %a1, i32 %b1) { define <16 x i1> @test9(<16 x i1>%a, <16 x i1>%b, i32 %a1, i32 %b1) {
; KNL-LABEL: test9: ; KNL-LABEL: test9:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: cmpl %esi, %edi ; KNL-NEXT: cmpl %esi, %edi
; KNL-NEXT: jg LBB15_1 ; KNL-NEXT: jg LBB16_1
; KNL-NEXT: ## BB#2: ; KNL-NEXT: ## BB#2:
; KNL-NEXT: vpmovsxbd %xmm1, %zmm0 ; KNL-NEXT: vpmovsxbd %xmm1, %zmm0
; KNL-NEXT: jmp LBB15_3 ; KNL-NEXT: jmp LBB16_3
; KNL-NEXT: LBB15_1: ; KNL-NEXT: LBB16_1:
; KNL-NEXT: vpmovsxbd %xmm0, %zmm0 ; KNL-NEXT: vpmovsxbd %xmm0, %zmm0
; KNL-NEXT: LBB15_3: ; KNL-NEXT: LBB16_3:
; KNL-NEXT: vpslld $31, %zmm0, %zmm0 ; KNL-NEXT: vpslld $31, %zmm0, %zmm0
; KNL-NEXT: vptestmd %zmm0, %zmm0, %k1 ; KNL-NEXT: vptestmd %zmm0, %zmm0, %k1
; KNL-NEXT: vpbroadcastd {{.*}}(%rip), %zmm0 {%k1} {z} ; KNL-NEXT: vpbroadcastd {{.*}}(%rip), %zmm0 {%k1} {z}
; KNL-NEXT: vpmovdb %zmm0, %xmm0 ; KNL-NEXT: vpmovdb %zmm0, %xmm0
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test9: ; SKX-LABEL: test9:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: cmpl %esi, %edi ; SKX-NEXT: cmpl %esi, %edi
; SKX-NEXT: jg LBB15_1 ; SKX-NEXT: jg LBB16_1
; SKX-NEXT: ## BB#2: ; SKX-NEXT: ## BB#2:
; SKX-NEXT: vpsllw $7, %xmm1, %xmm0 ; SKX-NEXT: vpsllw $7, %xmm1, %xmm0
; SKX-NEXT: jmp LBB15_3 ; SKX-NEXT: jmp LBB16_3
; SKX-NEXT: LBB15_1: ; SKX-NEXT: LBB16_1:
; SKX-NEXT: vpsllw $7, %xmm0, %xmm0 ; SKX-NEXT: vpsllw $7, %xmm0, %xmm0
; SKX-NEXT: LBB15_3: ; SKX-NEXT: LBB16_3:
; SKX-NEXT: vpmovb2m %xmm0, %k0 ; SKX-NEXT: vpmovb2m %xmm0, %k0
; SKX-NEXT: vpmovm2b %k0, %xmm0 ; SKX-NEXT: vpmovm2b %k0, %xmm0
; SKX-NEXT: retq ; SKX-NEXT: retq
%mask = icmp sgt i32 %a1, %b1 %mask = icmp sgt i32 %a1, %b1
%c = select i1 %mask, <16 x i1>%a, <16 x i1>%b %c = select i1 %mask, <16 x i1>%a, <16 x i1>%b
ret <16 x i1>%c ret <16 x i1>%c
}define <8 x i1> @test10(<8 x i1>%a, <8 x i1>%b, i32 %a1, i32 %b1) { }define <8 x i1> @test10(<8 x i1>%a, <8 x i1>%b, i32 %a1, i32 %b1) {
%mask = icmp sgt i32 %a1, %b1 %mask = icmp sgt i32 %a1, %b1
%c = select i1 %mask, <8 x i1>%a, <8 x i1>%b %c = select i1 %mask, <8 x i1>%a, <8 x i1>%b
ret <8 x i1>%c ret <8 x i1>%c
} }
define <4 x i1> @test11(<4 x i1>%a, <4 x i1>%b, i32 %a1, i32 %b1) { define <4 x i1> @test11(<4 x i1>%a, <4 x i1>%b, i32 %a1, i32 %b1) {
; KNL-LABEL: test11: ; KNL-LABEL: test11:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: cmpl %esi, %edi ; KNL-NEXT: cmpl %esi, %edi
; KNL-NEXT: jg LBB17_2 ; KNL-NEXT: jg LBB18_2
; KNL-NEXT: ## BB#1: ; KNL-NEXT: ## BB#1:
; KNL-NEXT: vmovaps %zmm1, %zmm0 ; KNL-NEXT: vmovaps %zmm1, %zmm0
; KNL-NEXT: LBB17_2: ; KNL-NEXT: LBB18_2:
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: test11: ; SKX-LABEL: test11:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: cmpl %esi, %edi ; SKX-NEXT: cmpl %esi, %edi
; SKX-NEXT: jg LBB17_1 ; SKX-NEXT: jg LBB18_1
; SKX-NEXT: ## BB#2: ; SKX-NEXT: ## BB#2:
; SKX-NEXT: vpslld $31, %xmm1, %xmm0 ; SKX-NEXT: vpslld $31, %xmm1, %xmm0
; SKX-NEXT: jmp LBB17_3 ; SKX-NEXT: jmp LBB18_3
; SKX-NEXT: LBB17_1: ; SKX-NEXT: LBB18_1:
; SKX-NEXT: vpslld $31, %xmm0, %xmm0 ; SKX-NEXT: vpslld $31, %xmm0, %xmm0
; SKX-NEXT: LBB17_3: ; SKX-NEXT: LBB18_3:
; SKX-NEXT: vptestmd %xmm0, %xmm0, %k0 ; SKX-NEXT: vptestmd %xmm0, %xmm0, %k0
; SKX-NEXT: vpmovm2d %k0, %xmm0 ; SKX-NEXT: vpmovm2d %k0, %xmm0
; SKX-NEXT: retq ; SKX-NEXT: retq
%mask = icmp sgt i32 %a1, %b1 %mask = icmp sgt i32 %a1, %b1
%c = select i1 %mask, <4 x i1>%a, <4 x i1>%b %c = select i1 %mask, <4 x i1>%a, <4 x i1>%b
ret <4 x i1>%c ret <4 x i1>%c
} }
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; KNL-LABEL: ktest_1: ; KNL-LABEL: ktest_1:
; KNL: ## BB#0: ; KNL: ## BB#0:
; KNL-NEXT: vmovupd (%rdi), %zmm1 ; KNL-NEXT: vmovupd (%rdi), %zmm1
; KNL-NEXT: vcmpltpd %zmm0, %zmm1, %k1 ; KNL-NEXT: vcmpltpd %zmm0, %zmm1, %k1
; KNL-NEXT: vmovupd 8(%rdi), %zmm1 {%k1} {z} ; KNL-NEXT: vmovupd 8(%rdi), %zmm1 {%k1} {z}
; KNL-NEXT: vcmpltpd %zmm1, %zmm0, %k0 {%k1} ; KNL-NEXT: vcmpltpd %zmm1, %zmm0, %k0 {%k1}
; KNL-NEXT: kmovw %k0, %eax ; KNL-NEXT: kmovw %k0, %eax
; KNL-NEXT: testb %al, %al ; KNL-NEXT: testb %al, %al
; KNL-NEXT: je LBB38_2 ; KNL-NEXT: je LBB39_2
; KNL-NEXT: ## BB#1: ## %L1 ; KNL-NEXT: ## BB#1: ## %L1
; KNL-NEXT: vmovapd %zmm0, (%rdi) ; KNL-NEXT: vmovapd %zmm0, (%rdi)
; KNL-NEXT: retq ; KNL-NEXT: retq
; KNL-NEXT: LBB38_2: ## %L2 ; KNL-NEXT: LBB39_2: ## %L2
; KNL-NEXT: vmovapd %zmm0, 8(%rdi) ; KNL-NEXT: vmovapd %zmm0, 8(%rdi)
; KNL-NEXT: retq ; KNL-NEXT: retq
; ;
; SKX-LABEL: ktest_1: ; SKX-LABEL: ktest_1:
; SKX: ## BB#0: ; SKX: ## BB#0:
; SKX-NEXT: vmovupd (%rdi), %zmm1 ; SKX-NEXT: vmovupd (%rdi), %zmm1
; SKX-NEXT: vcmpltpd %zmm0, %zmm1, %k1 ; SKX-NEXT: vcmpltpd %zmm0, %zmm1, %k1
; SKX-NEXT: vmovupd 8(%rdi), %zmm1 {%k1} {z} ; SKX-NEXT: vmovupd 8(%rdi), %zmm1 {%k1} {z}
; SKX-NEXT: vcmpltpd %zmm1, %zmm0, %k0 {%k1} ; SKX-NEXT: vcmpltpd %zmm1, %zmm0, %k0 {%k1}
; SKX-NEXT: ktestb %k0, %k0 ; SKX-NEXT: ktestb %k0, %k0
; SKX-NEXT: je LBB38_2 ; SKX-NEXT: je LBB39_2
; SKX-NEXT: ## BB#1: ## %L1 ; SKX-NEXT: ## BB#1: ## %L1
; SKX-NEXT: vmovapd %zmm0, (%rdi) ; SKX-NEXT: vmovapd %zmm0, (%rdi)
; SKX-NEXT: retq ; SKX-NEXT: retq
; SKX-NEXT: LBB38_2: ## %L2 ; SKX-NEXT: LBB39_2: ## %L2
; SKX-NEXT: vmovapd %zmm0, 8(%rdi) ; SKX-NEXT: vmovapd %zmm0, 8(%rdi)
; SKX-NEXT: retq ; SKX-NEXT: retq
%addr1 = getelementptr double, double * %base, i64 0 %addr1 = getelementptr double, double * %base, i64 0
%addr2 = getelementptr double, double * %base, i64 1 %addr2 = getelementptr double, double * %base, i64 1
%vaddr1 = bitcast double* %addr1 to <8 x double>* %vaddr1 = bitcast double* %addr1 to <8 x double>*
%vaddr2 = bitcast double* %addr2 to <8 x double>* %vaddr2 = bitcast double* %addr2 to <8 x double>*
Show All 29 Lines
; SKX-NEXT: kunpckwd %k1, %k2, %k0 ; SKX-NEXT: kunpckwd %k1, %k2, %k0
; SKX-NEXT: vmovups 68(%rdi), %zmm2 {%k2} {z} ; SKX-NEXT: vmovups 68(%rdi), %zmm2 {%k2} {z}
; SKX-NEXT: vmovups 4(%rdi), %zmm3 {%k1} {z} ; SKX-NEXT: vmovups 4(%rdi), %zmm3 {%k1} {z}
; SKX-NEXT: vcmpltps %zmm3, %zmm0, %k1 ; SKX-NEXT: vcmpltps %zmm3, %zmm0, %k1
; SKX-NEXT: vcmpltps %zmm2, %zmm1, %k2 ; SKX-NEXT: vcmpltps %zmm2, %zmm1, %k2
; SKX-NEXT: kunpckwd %k1, %k2, %k1 ; SKX-NEXT: kunpckwd %k1, %k2, %k1
; SKX-NEXT: kord %k1, %k0, %k0 ; SKX-NEXT: kord %k1, %k0, %k0
; SKX-NEXT: ktestd %k0, %k0 ; SKX-NEXT: ktestd %k0, %k0
; SKX-NEXT: je LBB39_2 ; SKX-NEXT: je LBB40_2
; SKX-NEXT: ## BB#1: ## %L1 ; SKX-NEXT: ## BB#1: ## %L1
; SKX-NEXT: vmovaps %zmm0, (%rdi) ; SKX-NEXT: vmovaps %zmm0, (%rdi)
; SKX-NEXT: vmovaps %zmm1, 64(%rdi) ; SKX-NEXT: vmovaps %zmm1, 64(%rdi)
; SKX-NEXT: retq ; SKX-NEXT: retq
; SKX-NEXT: LBB39_2: ## %L2 ; SKX-NEXT: LBB40_2: ## %L2
; SKX-NEXT: vmovaps %zmm0, 4(%rdi) ; SKX-NEXT: vmovaps %zmm0, 4(%rdi)
; SKX-NEXT: vmovaps %zmm1, 68(%rdi) ; SKX-NEXT: vmovaps %zmm1, 68(%rdi)
; SKX-NEXT: retq ; SKX-NEXT: retq
%addr1 = getelementptr float, float * %base, i64 0 %addr1 = getelementptr float, float * %base, i64 0
%addr2 = getelementptr float, float * %base, i64 1 %addr2 = getelementptr float, float * %base, i64 1
%vaddr1 = bitcast float* %addr1 to <32 x float>* %vaddr1 = bitcast float* %addr1 to <32 x float>*
%vaddr2 = bitcast float* %addr2 to <32 x float>* %vaddr2 = bitcast float* %addr2 to <32 x float>*
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llvm/trunk/test/CodeGen/X86/avx512-select.ll

Show First 20 Lines • Show All 65 Lines • ▼ Show 20 Lines
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%sel = select <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x double> %a, <16 x double> %b %sel = select <16 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <16 x double> %a, <16 x double> %b
ret <16 x double> %sel ret <16 x double> %sel
} }
define i8 @select05(i8 %a.0, i8 %m) { define i8 @select05(i8 %a.0, i8 %m) {
; CHECK-LABEL: select05: ; CHECK-LABEL: select05:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %esi, %k0 ; CHECK-NEXT: orl %esi, %edi
; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: movb %dil, %al
; CHECK-NEXT: korw %k1, %k0, %k0
; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%mask = bitcast i8 %m to <8 x i1> %mask = bitcast i8 %m to <8 x i1>
%a = bitcast i8 %a.0 to <8 x i1> %a = bitcast i8 %a.0 to <8 x i1>
%r = select <8 x i1> %mask, <8 x i1> <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>, <8 x i1> %a %r = select <8 x i1> %mask, <8 x i1> <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>, <8 x i1> %a
%res = bitcast <8 x i1> %r to i8 %res = bitcast <8 x i1> %r to i8
ret i8 %res; ret i8 %res;
} }
define i8 @select05_mem(<8 x i1>* %a.0, <8 x i1>* %m) {
; CHECK-LABEL: select05_mem:
; CHECK: ## BB#0:
; CHECK-NEXT: movzbw (%rsi), %ax
; CHECK-NEXT: kmovw %eax, %k0
; CHECK-NEXT: movzbw (%rdi), %ax
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: korw %k1, %k0, %k0
; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: retq
%mask = load <8 x i1> , <8 x i1>* %m
%a = load <8 x i1> , <8 x i1>* %a.0
%r = select <8 x i1> %mask, <8 x i1> <i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1, i1 -1>, <8 x i1> %a
%res = bitcast <8 x i1> %r to i8
ret i8 %res;
}
define i8 @select06(i8 %a.0, i8 %m) { define i8 @select06(i8 %a.0, i8 %m) {
; CHECK-LABEL: select06: ; CHECK-LABEL: select06:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %esi, %k0 ; CHECK-NEXT: andl %esi, %edi
; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: movb %dil, %al
; CHECK-NEXT: kandw %k1, %k0, %k0
; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%mask = bitcast i8 %m to <8 x i1> %mask = bitcast i8 %m to <8 x i1>
%a = bitcast i8 %a.0 to <8 x i1> %a = bitcast i8 %a.0 to <8 x i1>
%r = select <8 x i1> %mask, <8 x i1> %a, <8 x i1> zeroinitializer %r = select <8 x i1> %mask, <8 x i1> %a, <8 x i1> zeroinitializer
%res = bitcast <8 x i1> %r to i8 %res = bitcast <8 x i1> %r to i8
ret i8 %res; ret i8 %res;
} }
define i8 @select06_mem(<8 x i1>* %a.0, <8 x i1>* %m) {
; CHECK-LABEL: select06_mem:
; CHECK: ## BB#0:
; CHECK-NEXT: movzbw (%rsi), %ax
; CHECK-NEXT: kmovw %eax, %k0
; CHECK-NEXT: movzbw (%rdi), %ax
; CHECK-NEXT: kmovw %eax, %k1
; CHECK-NEXT: kandw %k1, %k0, %k0
; CHECK-NEXT: kmovw %k0, %eax
; CHECK-NEXT: retq
%mask = load <8 x i1> , <8 x i1>* %m
%a = load <8 x i1> , <8 x i1>* %a.0
%r = select <8 x i1> %mask, <8 x i1> %a, <8 x i1> zeroinitializer
%res = bitcast <8 x i1> %r to i8
ret i8 %res;
}
define i8 @select07(i8 %a.0, i8 %b.0, i8 %m) { define i8 @select07(i8 %a.0, i8 %b.0, i8 %m) {
; CHECK-LABEL: select07: ; CHECK-LABEL: select07:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovw %edx, %k0 ; CHECK-NEXT: kmovw %edx, %k0
; CHECK-NEXT: kmovw %edi, %k1 ; CHECK-NEXT: kmovw %edi, %k1
; CHECK-NEXT: kmovw %esi, %k2 ; CHECK-NEXT: kmovw %esi, %k2
; CHECK-NEXT: kandw %k0, %k1, %k1 ; CHECK-NEXT: kandw %k0, %k1, %k1
; CHECK-NEXT: knotw %k0, %k0 ; CHECK-NEXT: knotw %k0, %k0
Show All 11 Lines

llvm/trunk/test/CodeGen/X86/avx512bw-mask-op.ll

Show First 20 Lines • Show All 74 Lines • ▼ Show 20 Lines; CHECK-NEXT: retq
%ret = bitcast <64 x i1> %m1 to i64 %ret = bitcast <64 x i1> %m1 to i64
store i64 %ret, i64* %ptr, align 4 store i64 %ret, i64* %ptr, align 4
ret void ret void
} }
define i32 @mand32(i32 %x, i32 %y) { define i32 @mand32(i32 %x, i32 %y) {
; CHECK-LABEL: mand32: ; CHECK-LABEL: mand32:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovd %edi, %k0 ; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: kmovd %esi, %k1 ; CHECK-NEXT: andl %esi, %eax
; CHECK-NEXT: xorl %esi, %edi
; CHECK-NEXT: orl %eax, %edi
; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: retq
%ma = bitcast i32 %x to <32 x i1>
%mb = bitcast i32 %y to <32 x i1>
%mc = and <32 x i1> %ma, %mb
%md = xor <32 x i1> %ma, %mb
%me = or <32 x i1> %mc, %md
%ret = bitcast <32 x i1> %me to i32
ret i32 %ret
}
define i32 @mand32_mem(<32 x i1>* %x, <32 x i1>* %y) {
; CHECK-LABEL: mand32_mem:
; CHECK: ## BB#0:
; CHECK-NEXT: kmovd (%rdi), %k0
; CHECK-NEXT: kmovd (%rsi), %k1
; CHECK-NEXT: kandd %k1, %k0, %k2 ; CHECK-NEXT: kandd %k1, %k0, %k2
; CHECK-NEXT: kxord %k1, %k0, %k0 ; CHECK-NEXT: kxord %k1, %k0, %k0
; CHECK-NEXT: kord %k0, %k2, %k0 ; CHECK-NEXT: kord %k0, %k2, %k0
; CHECK-NEXT: kmovd %k0, %eax ; CHECK-NEXT: kmovd %k0, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%ma = bitcast i32 %x to <32 x i1> %ma = load <32 x i1>, <32 x i1>* %x
%mb = bitcast i32 %y to <32 x i1> %mb = load <32 x i1>, <32 x i1>* %y
%mc = and <32 x i1> %ma, %mb %mc = and <32 x i1> %ma, %mb
%md = xor <32 x i1> %ma, %mb %md = xor <32 x i1> %ma, %mb
%me = or <32 x i1> %mc, %md %me = or <32 x i1> %mc, %md
%ret = bitcast <32 x i1> %me to i32 %ret = bitcast <32 x i1> %me to i32
ret i32 %ret ret i32 %ret
} }
define i64 @mand64(i64 %x, i64 %y) { define i64 @mand64(i64 %x, i64 %y) {
; CHECK-LABEL: mand64: ; CHECK-LABEL: mand64:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovq %rdi, %k0 ; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: kmovq %rsi, %k1 ; CHECK-NEXT: andq %rsi, %rax
; CHECK-NEXT: xorq %rsi, %rdi
; CHECK-NEXT: orq %rax, %rdi
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: retq
%ma = bitcast i64 %x to <64 x i1>
%mb = bitcast i64 %y to <64 x i1>
%mc = and <64 x i1> %ma, %mb
%md = xor <64 x i1> %ma, %mb
%me = or <64 x i1> %mc, %md
%ret = bitcast <64 x i1> %me to i64
ret i64 %ret
}
define i64 @mand64_mem(<64 x i1>* %x, <64 x i1>* %y) {
; CHECK-LABEL: mand64_mem:
; CHECK: ## BB#0:
; CHECK-NEXT: kmovq (%rdi), %k0
; CHECK-NEXT: kmovq (%rsi), %k1
; CHECK-NEXT: kandq %k1, %k0, %k2 ; CHECK-NEXT: kandq %k1, %k0, %k2
; CHECK-NEXT: kxorq %k1, %k0, %k0 ; CHECK-NEXT: kxorq %k1, %k0, %k0
; CHECK-NEXT: korq %k0, %k2, %k0 ; CHECK-NEXT: korq %k0, %k2, %k0
; CHECK-NEXT: kmovq %k0, %rax ; CHECK-NEXT: kmovq %k0, %rax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%ma = bitcast i64 %x to <64 x i1> %ma = load <64 x i1>, <64 x i1>* %x
%mb = bitcast i64 %y to <64 x i1> %mb = load <64 x i1>, <64 x i1>* %y
%mc = and <64 x i1> %ma, %mb %mc = and <64 x i1> %ma, %mb
%md = xor <64 x i1> %ma, %mb %md = xor <64 x i1> %ma, %mb
%me = or <64 x i1> %mc, %md %me = or <64 x i1> %mc, %md
%ret = bitcast <64 x i1> %me to i64 %ret = bitcast <64 x i1> %me to i64
ret i64 %ret ret i64 %ret
} }

llvm/trunk/test/CodeGen/X86/avx512dq-mask-op.ll

Show All 26 Lines; CHECK-NEXT: retq
%ret = bitcast <8 x i1> %m1 to i8 %ret = bitcast <8 x i1> %m1 to i8
store i8 %ret, i8* %ptr, align 4 store i8 %ret, i8* %ptr, align 4
ret void ret void
} }
define i8 @mand8(i8 %x, i8 %y) { define i8 @mand8(i8 %x, i8 %y) {
; CHECK-LABEL: mand8: ; CHECK-LABEL: mand8:
; CHECK: ## BB#0: ; CHECK: ## BB#0:
; CHECK-NEXT: kmovb %edi, %k0 ; CHECK-NEXT: movl %edi, %eax
; CHECK-NEXT: kmovb %esi, %k1 ; CHECK-NEXT: xorl %esi, %eax
; CHECK-NEXT: andl %esi, %edi
; CHECK-NEXT: orl %eax, %edi
; CHECK-NEXT: movb %dil, %al
; CHECK-NEXT: retq
%ma = bitcast i8 %x to <8 x i1>
%mb = bitcast i8 %y to <8 x i1>
%mc = and <8 x i1> %ma, %mb
%md = xor <8 x i1> %ma, %mb
%me = or <8 x i1> %mc, %md
%ret = bitcast <8 x i1> %me to i8
ret i8 %ret
}
define i8 @mand8_mem(<8 x i1>* %x, <8 x i1>* %y) {
; CHECK-LABEL: mand8_mem:
; CHECK: ## BB#0:
; CHECK-NEXT: kmovb (%rdi), %k0
; CHECK-NEXT: kmovb (%rsi), %k1
; CHECK-NEXT: kandb %k1, %k0, %k2 ; CHECK-NEXT: kandb %k1, %k0, %k2
; CHECK-NEXT: kxorb %k1, %k0, %k0 ; CHECK-NEXT: kxorb %k1, %k0, %k0
; CHECK-NEXT: korb %k0, %k2, %k0 ; CHECK-NEXT: korb %k0, %k2, %k0
; CHECK-NEXT: kmovb %k0, %eax ; CHECK-NEXT: kmovb %k0, %eax
; CHECK-NEXT: retq ; CHECK-NEXT: retq
%ma = bitcast i8 %x to <8 x i1> %ma = load <8 x i1>, <8 x i1>* %x
%mb = bitcast i8 %y to <8 x i1> %mb = load <8 x i1>, <8 x i1>* %y
%mc = and <8 x i1> %ma, %mb %mc = and <8 x i1> %ma, %mb
%md = xor <8 x i1> %ma, %mb %md = xor <8 x i1> %ma, %mb
%me = or <8 x i1> %mc, %md %me = or <8 x i1> %mc, %md
%ret = bitcast <8 x i1> %me to i8 %ret = bitcast <8 x i1> %me to i8
ret i8 %ret ret i8 %ret
} }

llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v4.ll

Show First 20 Lines • Show All 1,863 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%5 = or <4 x i32> %4, %3 %5 = or <4 x i32> %4, %3
%6 = bitcast <4 x i32> %5 to <4 x float> %6 = bitcast <4 x i32> %5 to <4 x float>
ret <4 x float> %6 ret <4 x float> %6
} }
define <4 x float> @mask_v4f32_0127(<4 x float> %a, <4 x float> %b) { define <4 x float> @mask_v4f32_0127(<4 x float> %a, <4 x float> %b) {
; SSE2-LABEL: mask_v4f32_0127: ; SSE2-LABEL: mask_v4f32_0127:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: andps {{.*}}(%rip), %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
; SSE2-NEXT: andps {{.*}}(%rip), %xmm1 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
; SSE2-NEXT: orps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: mask_v4f32_0127: ; SSE3-LABEL: mask_v4f32_0127:
; SSE3: # BB#0: ; SSE3: # BB#0:
; SSE3-NEXT: andps {{.*}}(%rip), %xmm0 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
; SSE3-NEXT: andps {{.*}}(%rip), %xmm1 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
; SSE3-NEXT: orps %xmm1, %xmm0 ; SSE3-NEXT: movaps %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: mask_v4f32_0127: ; SSSE3-LABEL: mask_v4f32_0127:
; SSSE3: # BB#0: ; SSSE3: # BB#0:
; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
; SSSE3-NEXT: andps {{.*}}(%rip), %xmm1 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
; SSSE3-NEXT: orps %xmm1, %xmm0 ; SSSE3-NEXT: movaps %xmm1, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: mask_v4f32_0127: ; SSE41-LABEL: mask_v4f32_0127:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: pxor %xmm2, %xmm2 ; SSE41-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3,4,5],xmm0[6,7]
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1,2,3,4,5],xmm2[6,7]
; SSE41-NEXT: por %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: mask_v4f32_0127: ; AVX-LABEL: mask_v4f32_0127:
; AVX1: # BB#0: ; AVX: # BB#0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3,4,5],xmm0[6,7] ; AVX-NEXT: retq
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5],xmm2[6,7]
; AVX1-NEXT: vpor %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq
;
; AVX2-LABEL: mask_v4f32_0127:
; AVX2: # BB#0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[3]
; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3]
; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
; AVX2-NEXT: retq
%1 = bitcast <4 x float> %a to <2 x i64> %1 = bitcast <4 x float> %a to <2 x i64>
%2 = bitcast <4 x float> %b to <2 x i64> %2 = bitcast <4 x float> %b to <2 x i64>
%3 = and <2 x i64> %1, <i64 0, i64 -4294967296> %3 = and <2 x i64> %1, <i64 0, i64 -4294967296>
%4 = and <2 x i64> %2, <i64 -1, i64 4294967295> %4 = and <2 x i64> %2, <i64 -1, i64 4294967295>
%5 = or <2 x i64> %4, %3 %5 = or <2 x i64> %4, %3
%6 = bitcast <2 x i64> %5 to <4 x float> %6 = bitcast <2 x i64> %5 to <4 x float>
ret <4 x float> %6 ret <4 x float> %6
} }
define <4 x i32> @mask_v4i32_0127(<4 x i32> %a, <4 x i32> %b) { define <4 x i32> @mask_v4i32_0127(<4 x i32> %a, <4 x i32> %b) {
; SSE2-LABEL: mask_v4i32_0127: ; SSE2-LABEL: mask_v4i32_0127:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: andps {{.*}}(%rip), %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
; SSE2-NEXT: andps {{.*}}(%rip), %xmm1 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
; SSE2-NEXT: orps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSE3-LABEL: mask_v4i32_0127: ; SSE3-LABEL: mask_v4i32_0127:
; SSE3: # BB#0: ; SSE3: # BB#0:
; SSE3-NEXT: andps {{.*}}(%rip), %xmm0 ; SSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
; SSE3-NEXT: andps {{.*}}(%rip), %xmm1 ; SSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
; SSE3-NEXT: orps %xmm1, %xmm0 ; SSE3-NEXT: movaps %xmm1, %xmm0
; SSE3-NEXT: retq ; SSE3-NEXT: retq
; ;
; SSSE3-LABEL: mask_v4i32_0127: ; SSSE3-LABEL: mask_v4i32_0127:
; SSSE3: # BB#0: ; SSSE3: # BB#0:
; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
; SSSE3-NEXT: andps {{.*}}(%rip), %xmm1 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
; SSSE3-NEXT: orps %xmm1, %xmm0 ; SSSE3-NEXT: movaps %xmm1, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: mask_v4i32_0127: ; SSE41-LABEL: mask_v4i32_0127:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: pxor %xmm2, %xmm2 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3,4,5],xmm0[6,7]
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1,2,3,4,5],xmm2[6,7]
; SSE41-NEXT: por %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: mask_v4i32_0127: ; AVX1-LABEL: mask_v4i32_0127:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3,4,5],xmm0[6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5],xmm2[6,7]
; AVX1-NEXT: vpor %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: mask_v4i32_0127: ; AVX2-LABEL: mask_v4i32_0127:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[3]
; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3]
; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%1 = bitcast <4 x i32> %a to <2 x i64> %1 = bitcast <4 x i32> %a to <2 x i64>
%2 = bitcast <4 x i32> %b to <2 x i64> %2 = bitcast <4 x i32> %b to <2 x i64>
%3 = and <2 x i64> %1, <i64 0, i64 -4294967296> %3 = and <2 x i64> %1, <i64 0, i64 -4294967296>
%4 = and <2 x i64> %2, <i64 -1, i64 4294967295> %4 = and <2 x i64> %2, <i64 -1, i64 4294967295>
%5 = or <2 x i64> %4, %3 %5 = or <2 x i64> %4, %3
%6 = bitcast <2 x i64> %5 to <4 x i32> %6 = bitcast <2 x i64> %5 to <4 x i32>
ret <4 x i32> %6 ret <4 x i32> %6
▲ Show 20 Lines • Show All 334 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/X86/vector-shuffle-128-v8.ll

Show First 20 Lines • Show All 2,134 Lines • ▼ Show 20 Lines; AVX-NEXT: retq
%shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 8, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 undef> %shuffle = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 8, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 undef>
ret <8 x i16> %shuffle ret <8 x i16> %shuffle
} }
define <8 x i16> @mask_v8i16_012345ef(<8 x i16> %a, <8 x i16> %b) { define <8 x i16> @mask_v8i16_012345ef(<8 x i16> %a, <8 x i16> %b) {
; SSE2-LABEL: mask_v8i16_012345ef: ; SSE2-LABEL: mask_v8i16_012345ef:
; SSE2: # BB#0: ; SSE2: # BB#0:
; SSE2-NEXT: andps {{.*}}(%rip), %xmm0 ; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
; SSE2-NEXT: andps {{.*}}(%rip), %xmm1 ; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
; SSE2-NEXT: orps %xmm1, %xmm0 ; SSE2-NEXT: movaps %xmm1, %xmm0
; SSE2-NEXT: retq ; SSE2-NEXT: retq
; ;
; SSSE3-LABEL: mask_v8i16_012345ef: ; SSSE3-LABEL: mask_v8i16_012345ef:
; SSSE3: # BB#0: ; SSSE3: # BB#0:
; SSSE3-NEXT: andps {{.*}}(%rip), %xmm0 ; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,0],xmm1[2,0]
; SSSE3-NEXT: andps {{.*}}(%rip), %xmm1 ; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[2,0]
; SSSE3-NEXT: orps %xmm1, %xmm0 ; SSSE3-NEXT: movaps %xmm1, %xmm0
; SSSE3-NEXT: retq ; SSSE3-NEXT: retq
; ;
; SSE41-LABEL: mask_v8i16_012345ef: ; SSE41-LABEL: mask_v8i16_012345ef:
; SSE41: # BB#0: ; SSE41: # BB#0:
; SSE41-NEXT: pxor %xmm2, %xmm2 ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm2[0,1,2,3,4,5],xmm0[6,7]
; SSE41-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1,2,3,4,5],xmm2[6,7]
; SSE41-NEXT: por %xmm2, %xmm0
; SSE41-NEXT: retq ; SSE41-NEXT: retq
; ;
; AVX1-LABEL: mask_v8i16_012345ef: ; AVX1-LABEL: mask_v8i16_012345ef:
; AVX1: # BB#0: ; AVX1: # BB#0:
; AVX1-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm2[0,1,2,3,4,5],xmm0[6,7]
; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5],xmm2[6,7]
; AVX1-NEXT: vpor %xmm0, %xmm1, %xmm0
; AVX1-NEXT: retq ; AVX1-NEXT: retq
; ;
; AVX2-LABEL: mask_v8i16_012345ef: ; AVX2-LABEL: mask_v8i16_012345ef:
; AVX2: # BB#0: ; AVX2: # BB#0:
; AVX2-NEXT: vpxor %xmm2, %xmm2, %xmm2 ; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0,1,2],xmm0[3]
; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm2[0,1,2],xmm0[3]
; AVX2-NEXT: vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm2[3]
; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0
; AVX2-NEXT: retq ; AVX2-NEXT: retq
%1 = bitcast <8 x i16> %a to <2 x i64> %1 = bitcast <8 x i16> %a to <2 x i64>
%2 = bitcast <8 x i16> %b to <2 x i64> %2 = bitcast <8 x i16> %b to <2 x i64>
%3 = and <2 x i64> %1, <i64 0, i64 -4294967296> %3 = and <2 x i64> %1, <i64 0, i64 -4294967296>
%4 = and <2 x i64> %2, <i64 -1, i64 4294967295> %4 = and <2 x i64> %2, <i64 -1, i64 4294967295>
%5 = or <2 x i64> %4, %3 %5 = or <2 x i64> %4, %3
%6 = bitcast <2 x i64> %5 to <8 x i16> %6 = bitcast <2 x i64> %5 to <8 x i16>
ret <8 x i16> %6 ret <8 x i16> %6
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llvm/trunk/test/CodeGen/X86/widen_bitops-0.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE42 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE42
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE42 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE42
; ;
; AND/XOR/OR i24 as v3i8 ; AND/XOR/OR i24 as v3i8
; ;
define i24 @and_i24_as_v3i8(i24 %a, i24 %b) nounwind { define i24 @and_i24_as_v3i8(i24 %a, i24 %b) nounwind {
; X32-SSE-LABEL: and_i24_as_v3i8: ; X32-SSE-LABEL: and_i24_as_v3i8:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: subl $12, %esp ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero ; X32-SSE-NEXT: andl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; X32-SSE-NEXT: pand %xmm0, %xmm1
; X32-SSE-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: addl $12, %esp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: and_i24_as_v3i8: ; X64-SSE-LABEL: and_i24_as_v3i8:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movd %esi, %xmm0 ; X64-SSE-NEXT: andl %esi, %edi
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: movd %edi, %xmm1
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
; X64-SSE-NEXT: pand %xmm0, %xmm1
; X64-SSE-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast i24 %a to <3 x i8> %1 = bitcast i24 %a to <3 x i8>
%2 = bitcast i24 %b to <3 x i8> %2 = bitcast i24 %b to <3 x i8>
%3 = and <3 x i8> %1, %2 %3 = and <3 x i8> %1, %2
%4 = bitcast <3 x i8> %3 to i24 %4 = bitcast <3 x i8> %3 to i24
ret i24 %4 ret i24 %4
} }
define i24 @xor_i24_as_v3i8(i24 %a, i24 %b) nounwind { define i24 @xor_i24_as_v3i8(i24 %a, i24 %b) nounwind {
; X32-SSE-LABEL: xor_i24_as_v3i8: ; X32-SSE-LABEL: xor_i24_as_v3i8:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: subl $12, %esp ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero ; X32-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; X32-SSE-NEXT: pxor %xmm0, %xmm1
; X32-SSE-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: addl $12, %esp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: xor_i24_as_v3i8: ; X64-SSE-LABEL: xor_i24_as_v3i8:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movd %esi, %xmm0 ; X64-SSE-NEXT: xorl %esi, %edi
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: movd %edi, %xmm1
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
; X64-SSE-NEXT: pxor %xmm0, %xmm1
; X64-SSE-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast i24 %a to <3 x i8> %1 = bitcast i24 %a to <3 x i8>
%2 = bitcast i24 %b to <3 x i8> %2 = bitcast i24 %b to <3 x i8>
%3 = xor <3 x i8> %1, %2 %3 = xor <3 x i8> %1, %2
%4 = bitcast <3 x i8> %3 to i24 %4 = bitcast <3 x i8> %3 to i24
ret i24 %4 ret i24 %4
} }
define i24 @or_i24_as_v3i8(i24 %a, i24 %b) nounwind { define i24 @or_i24_as_v3i8(i24 %a, i24 %b) nounwind {
; X32-SSE-LABEL: or_i24_as_v3i8: ; X32-SSE-LABEL: or_i24_as_v3i8:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: subl $12, %esp ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero ; X32-SSE-NEXT: orl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; X32-SSE-NEXT: por %xmm0, %xmm1
; X32-SSE-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: addl $12, %esp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: or_i24_as_v3i8: ; X64-SSE-LABEL: or_i24_as_v3i8:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movd %esi, %xmm0 ; X64-SSE-NEXT: orl %esi, %edi
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: movd %edi, %xmm1
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
; X64-SSE-NEXT: por %xmm0, %xmm1
; X64-SSE-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast i24 %a to <3 x i8> %1 = bitcast i24 %a to <3 x i8>
%2 = bitcast i24 %b to <3 x i8> %2 = bitcast i24 %b to <3 x i8>
%3 = or <3 x i8> %1, %2 %3 = or <3 x i8> %1, %2
%4 = bitcast <3 x i8> %3 to i24 %4 = bitcast <3 x i8> %3 to i24
ret i24 %4 ret i24 %4
} }
; ;
; AND/XOR/OR i24 as v8i3 ; AND/XOR/OR i24 as v8i3
; ;
define i24 @and_i24_as_v8i3(i24 %a, i24 %b) nounwind { define i24 @and_i24_as_v8i3(i24 %a, i24 %b) nounwind {
; X32-SSE-LABEL: and_i24_as_v8i3: ; X32-SSE-LABEL: and_i24_as_v8i3:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pushl %ebp ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: movl %esp, %ebp ; X32-SSE-NEXT: andl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: andl $-8, %esp
; X32-SSE-NEXT: subl $24, %esp
; X32-SSE-NEXT: movl 12(%ebp), %eax
; X32-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: shrl $16, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movl 8(%ebp), %eax
; X32-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: shrl $16, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $3, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $7, %edx
; X32-SSE-NEXT: movd %edx, %xmm1
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $6, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $9, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm1
; X32-SSE-NEXT: shrl $15, %eax
; X32-SSE-NEXT: pinsrw $5, %eax, %xmm1
; X32-SSE-NEXT: pxor %xmm2, %xmm2
; X32-SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5],xmm2[6,7]
; X32-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $3, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $7, %edx
; X32-SSE-NEXT: movd %edx, %xmm0
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $6, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $9, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X32-SSE-NEXT: shrl $15, %eax
; X32-SSE-NEXT: pinsrw $5, %eax, %xmm0
; X32-SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm2[6,7]
; X32-SSE-NEXT: pand %xmm1, %xmm0
; X32-SSE-NEXT: pextrw $7, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $6, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $5, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $4, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $3, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $2, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $1, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movd %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X32-SSE-NEXT: shll $16, %ecx
; X32-SSE-NEXT: movzwl (%esp), %eax
; X32-SSE-NEXT: orl %ecx, %eax
; X32-SSE-NEXT: movl %ebp, %esp
; X32-SSE-NEXT: popl %ebp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: and_i24_as_v8i3: ; X64-SSE-LABEL: and_i24_as_v8i3:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movw %si, -{{[0-9]+}}(%rsp) ; X64-SSE-NEXT: andl %esi, %edi
; X64-SSE-NEXT: shrl $16, %esi ; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: movb %sil, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movw %di, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: shrl $16, %edi
; X64-SSE-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $3, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: movl %eax, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: movd %edx, %xmm0
; X64-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $6, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $9, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $12, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X64-SSE-NEXT: shrl $15, %eax
; X64-SSE-NEXT: movzwl %ax, %eax
; X64-SSE-NEXT: pinsrw $5, %eax, %xmm0
; X64-SSE-NEXT: xorl %eax, %eax
; X64-SSE-NEXT: pinsrw $6, %eax, %xmm0
; X64-SSE-NEXT: pinsrw $7, %eax, %xmm0
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %ecx
; X64-SSE-NEXT: movl %ecx, %edx
; X64-SSE-NEXT: shrl $3, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: movl %ecx, %esi
; X64-SSE-NEXT: andl $7, %esi
; X64-SSE-NEXT: movd %esi, %xmm1
; X64-SSE-NEXT: pinsrw $1, %edx, %xmm1
; X64-SSE-NEXT: movl %ecx, %edx
; X64-SSE-NEXT: shrl $6, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: pinsrw $2, %edx, %xmm1
; X64-SSE-NEXT: movl %ecx, %edx
; X64-SSE-NEXT: shrl $9, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: pinsrw $3, %edx, %xmm1
; X64-SSE-NEXT: movl %ecx, %edx
; X64-SSE-NEXT: shrl $12, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: pinsrw $4, %edx, %xmm1
; X64-SSE-NEXT: shrl $15, %ecx
; X64-SSE-NEXT: movzwl %cx, %ecx
; X64-SSE-NEXT: pinsrw $5, %ecx, %xmm1
; X64-SSE-NEXT: pinsrw $6, %eax, %xmm1
; X64-SSE-NEXT: pinsrw $7, %eax, %xmm1
; X64-SSE-NEXT: pand %xmm0, %xmm1
; X64-SSE-NEXT: pextrw $7, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; X64-SSE-NEXT: shll $16, %ecx
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: orl %ecx, %eax
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast i24 %a to <8 x i3> %1 = bitcast i24 %a to <8 x i3>
%2 = bitcast i24 %b to <8 x i3> %2 = bitcast i24 %b to <8 x i3>
%3 = and <8 x i3> %1, %2 %3 = and <8 x i3> %1, %2
%4 = bitcast <8 x i3> %3 to i24 %4 = bitcast <8 x i3> %3 to i24
ret i24 %4 ret i24 %4
} }
define i24 @xor_i24_as_v8i3(i24 %a, i24 %b) nounwind { define i24 @xor_i24_as_v8i3(i24 %a, i24 %b) nounwind {
; X32-SSE-LABEL: xor_i24_as_v8i3: ; X32-SSE-LABEL: xor_i24_as_v8i3:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pushl %ebp ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: movl %esp, %ebp ; X32-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: andl $-8, %esp
; X32-SSE-NEXT: subl $24, %esp
; X32-SSE-NEXT: movl 12(%ebp), %eax
; X32-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: shrl $16, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movl 8(%ebp), %eax
; X32-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: shrl $16, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $3, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $7, %edx
; X32-SSE-NEXT: movd %edx, %xmm1
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $6, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $9, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm1
; X32-SSE-NEXT: shrl $15, %eax
; X32-SSE-NEXT: pinsrw $5, %eax, %xmm1
; X32-SSE-NEXT: pxor %xmm2, %xmm2
; X32-SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5],xmm2[6,7]
; X32-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $3, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $7, %edx
; X32-SSE-NEXT: movd %edx, %xmm0
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $6, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $9, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X32-SSE-NEXT: shrl $15, %eax
; X32-SSE-NEXT: pinsrw $5, %eax, %xmm0
; X32-SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm2[6,7]
; X32-SSE-NEXT: pxor %xmm1, %xmm0
; X32-SSE-NEXT: pextrw $7, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $6, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $5, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $4, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $3, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $2, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $1, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movd %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X32-SSE-NEXT: shll $16, %ecx
; X32-SSE-NEXT: movzwl (%esp), %eax
; X32-SSE-NEXT: orl %ecx, %eax
; X32-SSE-NEXT: movl %ebp, %esp
; X32-SSE-NEXT: popl %ebp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: xor_i24_as_v8i3: ; X64-SSE-LABEL: xor_i24_as_v8i3:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movw %si, -{{[0-9]+}}(%rsp) ; X64-SSE-NEXT: xorl %esi, %edi
; X64-SSE-NEXT: shrl $16, %esi ; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: movb %sil, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movw %di, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: shrl $16, %edi
; X64-SSE-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $3, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: movl %eax, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: movd %edx, %xmm0
; X64-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $6, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $9, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $12, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X64-SSE-NEXT: shrl $15, %eax
; X64-SSE-NEXT: movzwl %ax, %eax
; X64-SSE-NEXT: pinsrw $5, %eax, %xmm0
; X64-SSE-NEXT: xorl %eax, %eax
; X64-SSE-NEXT: pinsrw $6, %eax, %xmm0
; X64-SSE-NEXT: pinsrw $7, %eax, %xmm0
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %ecx
; X64-SSE-NEXT: movl %ecx, %edx
; X64-SSE-NEXT: shrl $3, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: movl %ecx, %esi
; X64-SSE-NEXT: andl $7, %esi
; X64-SSE-NEXT: movd %esi, %xmm1
; X64-SSE-NEXT: pinsrw $1, %edx, %xmm1
; X64-SSE-NEXT: movl %ecx, %edx
; X64-SSE-NEXT: shrl $6, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: pinsrw $2, %edx, %xmm1
; X64-SSE-NEXT: movl %ecx, %edx
; X64-SSE-NEXT: shrl $9, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: pinsrw $3, %edx, %xmm1
; X64-SSE-NEXT: movl %ecx, %edx
; X64-SSE-NEXT: shrl $12, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: pinsrw $4, %edx, %xmm1
; X64-SSE-NEXT: shrl $15, %ecx
; X64-SSE-NEXT: movzwl %cx, %ecx
; X64-SSE-NEXT: pinsrw $5, %ecx, %xmm1
; X64-SSE-NEXT: pinsrw $6, %eax, %xmm1
; X64-SSE-NEXT: pinsrw $7, %eax, %xmm1
; X64-SSE-NEXT: pxor %xmm0, %xmm1
; X64-SSE-NEXT: pextrw $7, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; X64-SSE-NEXT: shll $16, %ecx
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: orl %ecx, %eax
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast i24 %a to <8 x i3> %1 = bitcast i24 %a to <8 x i3>
%2 = bitcast i24 %b to <8 x i3> %2 = bitcast i24 %b to <8 x i3>
%3 = xor <8 x i3> %1, %2 %3 = xor <8 x i3> %1, %2
%4 = bitcast <8 x i3> %3 to i24 %4 = bitcast <8 x i3> %3 to i24
ret i24 %4 ret i24 %4
} }
define i24 @or_i24_as_v8i3(i24 %a, i24 %b) nounwind { define i24 @or_i24_as_v8i3(i24 %a, i24 %b) nounwind {
; X32-SSE-LABEL: or_i24_as_v8i3: ; X32-SSE-LABEL: or_i24_as_v8i3:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pushl %ebp ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: movl %esp, %ebp ; X32-SSE-NEXT: orl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: andl $-8, %esp
; X32-SSE-NEXT: subl $24, %esp
; X32-SSE-NEXT: movl 12(%ebp), %eax
; X32-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: shrl $16, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movl 8(%ebp), %eax
; X32-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: shrl $16, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $3, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $7, %edx
; X32-SSE-NEXT: movd %edx, %xmm1
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $6, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $9, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm1
; X32-SSE-NEXT: shrl $15, %eax
; X32-SSE-NEXT: pinsrw $5, %eax, %xmm1
; X32-SSE-NEXT: pxor %xmm2, %xmm2
; X32-SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3,4,5],xmm2[6,7]
; X32-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $3, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $7, %edx
; X32-SSE-NEXT: movd %edx, %xmm0
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $6, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $9, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X32-SSE-NEXT: shrl $15, %eax
; X32-SSE-NEXT: pinsrw $5, %eax, %xmm0
; X32-SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm2[6,7]
; X32-SSE-NEXT: por %xmm1, %xmm0
; X32-SSE-NEXT: pextrw $7, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $6, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $5, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $4, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $3, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $2, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $1, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movd %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movzbl {{[0-9]+}}(%esp), %ecx
; X32-SSE-NEXT: shll $16, %ecx
; X32-SSE-NEXT: movzwl (%esp), %eax
; X32-SSE-NEXT: orl %ecx, %eax
; X32-SSE-NEXT: movl %ebp, %esp
; X32-SSE-NEXT: popl %ebp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: or_i24_as_v8i3: ; X64-SSE-LABEL: or_i24_as_v8i3:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movw %si, -{{[0-9]+}}(%rsp) ; X64-SSE-NEXT: orl %esi, %edi
; X64-SSE-NEXT: shrl $16, %esi ; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: movb %sil, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movw %di, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: shrl $16, %edi
; X64-SSE-NEXT: movb %dil, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $3, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: movl %eax, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: movd %edx, %xmm0
; X64-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $6, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $9, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $12, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X64-SSE-NEXT: shrl $15, %eax
; X64-SSE-NEXT: movzwl %ax, %eax
; X64-SSE-NEXT: pinsrw $5, %eax, %xmm0
; X64-SSE-NEXT: xorl %eax, %eax
; X64-SSE-NEXT: pinsrw $6, %eax, %xmm0
; X64-SSE-NEXT: pinsrw $7, %eax, %xmm0
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %ecx
; X64-SSE-NEXT: movl %ecx, %edx
; X64-SSE-NEXT: shrl $3, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: movl %ecx, %esi
; X64-SSE-NEXT: andl $7, %esi
; X64-SSE-NEXT: movd %esi, %xmm1
; X64-SSE-NEXT: pinsrw $1, %edx, %xmm1
; X64-SSE-NEXT: movl %ecx, %edx
; X64-SSE-NEXT: shrl $6, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: pinsrw $2, %edx, %xmm1
; X64-SSE-NEXT: movl %ecx, %edx
; X64-SSE-NEXT: shrl $9, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: pinsrw $3, %edx, %xmm1
; X64-SSE-NEXT: movl %ecx, %edx
; X64-SSE-NEXT: shrl $12, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: pinsrw $4, %edx, %xmm1
; X64-SSE-NEXT: shrl $15, %ecx
; X64-SSE-NEXT: movzwl %cx, %ecx
; X64-SSE-NEXT: pinsrw $5, %ecx, %xmm1
; X64-SSE-NEXT: pinsrw $6, %eax, %xmm1
; X64-SSE-NEXT: pinsrw $7, %eax, %xmm1
; X64-SSE-NEXT: por %xmm0, %xmm1
; X64-SSE-NEXT: pextrw $7, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %ecx
; X64-SSE-NEXT: shll $16, %ecx
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: orl %ecx, %eax
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast i24 %a to <8 x i3> %1 = bitcast i24 %a to <8 x i3>
%2 = bitcast i24 %b to <8 x i3> %2 = bitcast i24 %b to <8 x i3>
%3 = or <8 x i3> %1, %2 %3 = or <8 x i3> %1, %2
%4 = bitcast <8 x i3> %3 to i24 %4 = bitcast <8 x i3> %3 to i24
ret i24 %4 ret i24 %4
} }
; ;
; AND/XOR/OR v3i8 as i24 ; AND/XOR/OR v3i8 as i24
; ;
define <3 x i8> @and_v3i8_as_i24(<3 x i8> %a, <3 x i8> %b) nounwind { define <3 x i8> @and_v3i8_as_i24(<3 x i8> %a, <3 x i8> %b) nounwind {
; X32-SSE-LABEL: and_v3i8_as_i24: ; X32-SSE-LABEL: and_v3i8_as_i24:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: subl $12, %esp
; X32-SSE-NEXT: pinsrb $0, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: pinsrb $1, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: pinsrb $2, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: movd %xmm0, %eax
; X32-SSE-NEXT: pinsrb $0, {{[0-9]+}}(%esp), %xmm0 ; X32-SSE-NEXT: pinsrb $0, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: pinsrb $1, {{[0-9]+}}(%esp), %xmm0 ; X32-SSE-NEXT: pinsrb $4, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: pinsrb $2, {{[0-9]+}}(%esp), %xmm0 ; X32-SSE-NEXT: pinsrb $8, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: movd %xmm0, %ecx ; X32-SSE-NEXT: pinsrb $0, {{[0-9]+}}(%esp), %xmm1
; X32-SSE-NEXT: andl %eax, %ecx ; X32-SSE-NEXT: pinsrb $4, {{[0-9]+}}(%esp), %xmm1
; X32-SSE-NEXT: movd %ecx, %xmm0 ; X32-SSE-NEXT: pinsrb $8, {{[0-9]+}}(%esp), %xmm1
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; X32-SSE-NEXT: pand %xmm0, %xmm1
; X32-SSE-NEXT: pextrb $0, %xmm0, %eax ; X32-SSE-NEXT: pextrb $0, %xmm1, %eax
; X32-SSE-NEXT: pextrb $4, %xmm0, %edx ; X32-SSE-NEXT: pextrb $4, %xmm1, %edx
; X32-SSE-NEXT: pextrb $8, %xmm0, %ecx ; X32-SSE-NEXT: pextrb $8, %xmm1, %ecx
; X32-SSE-NEXT: addl $12, %esp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: and_v3i8_as_i24: ; X64-SSE-LABEL: and_v3i8_as_i24:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movd %ecx, %xmm0 ; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: pinsrd $1, %r8d, %xmm0 ; X64-SSE-NEXT: pinsrd $1, %r8d, %xmm0
; X64-SSE-NEXT: pinsrd $2, %r9d, %xmm0 ; X64-SSE-NEXT: pinsrd $2, %r9d, %xmm0
; X64-SSE-NEXT: movdqa {{.*#+}} xmm1 = <0,4,8,128,u,u,u,u,u,u,u,u,u,u,u,u> ; X64-SSE-NEXT: movd %edi, %xmm1
; X64-SSE-NEXT: pshufb %xmm1, %xmm0 ; X64-SSE-NEXT: pinsrd $1, %esi, %xmm1
; X64-SSE-NEXT: movd %xmm0, %eax ; X64-SSE-NEXT: pinsrd $2, %edx, %xmm1
; X64-SSE-NEXT: movd %edi, %xmm0 ; X64-SSE-NEXT: pand %xmm0, %xmm1
; X64-SSE-NEXT: pinsrd $1, %esi, %xmm0 ; X64-SSE-NEXT: pextrb $0, %xmm1, %eax
; X64-SSE-NEXT: pinsrd $2, %edx, %xmm0 ; X64-SSE-NEXT: pextrb $4, %xmm1, %edx
; X64-SSE-NEXT: pshufb %xmm1, %xmm0 ; X64-SSE-NEXT: pextrb $8, %xmm1, %ecx
; X64-SSE-NEXT: movd %xmm0, %ecx
; X64-SSE-NEXT: andl %eax, %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; X64-SSE-NEXT: pextrb $0, %xmm0, %eax
; X64-SSE-NEXT: pextrb $4, %xmm0, %edx
; X64-SSE-NEXT: pextrb $8, %xmm0, %ecx
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast <3 x i8> %a to i24 %1 = bitcast <3 x i8> %a to i24
%2 = bitcast <3 x i8> %b to i24 %2 = bitcast <3 x i8> %b to i24
%3 = and i24 %1, %2 %3 = and i24 %1, %2
%4 = bitcast i24 %3 to <3 x i8> %4 = bitcast i24 %3 to <3 x i8>
ret <3 x i8> %4 ret <3 x i8> %4
} }
define <3 x i8> @xor_v3i8_as_i24(<3 x i8> %a, <3 x i8> %b) nounwind { define <3 x i8> @xor_v3i8_as_i24(<3 x i8> %a, <3 x i8> %b) nounwind {
; X32-SSE-LABEL: xor_v3i8_as_i24: ; X32-SSE-LABEL: xor_v3i8_as_i24:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: subl $12, %esp
; X32-SSE-NEXT: pinsrb $0, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: pinsrb $1, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: pinsrb $2, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: movd %xmm0, %eax
; X32-SSE-NEXT: pinsrb $0, {{[0-9]+}}(%esp), %xmm0 ; X32-SSE-NEXT: pinsrb $0, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: pinsrb $1, {{[0-9]+}}(%esp), %xmm0 ; X32-SSE-NEXT: pinsrb $4, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: pinsrb $2, {{[0-9]+}}(%esp), %xmm0 ; X32-SSE-NEXT: pinsrb $8, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: movd %xmm0, %ecx ; X32-SSE-NEXT: pinsrb $0, {{[0-9]+}}(%esp), %xmm1
; X32-SSE-NEXT: xorl %eax, %ecx ; X32-SSE-NEXT: pinsrb $4, {{[0-9]+}}(%esp), %xmm1
; X32-SSE-NEXT: movd %ecx, %xmm0 ; X32-SSE-NEXT: pinsrb $8, {{[0-9]+}}(%esp), %xmm1
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; X32-SSE-NEXT: pxor %xmm0, %xmm1
; X32-SSE-NEXT: pextrb $0, %xmm0, %eax ; X32-SSE-NEXT: pextrb $0, %xmm1, %eax
; X32-SSE-NEXT: pextrb $4, %xmm0, %edx ; X32-SSE-NEXT: pextrb $4, %xmm1, %edx
; X32-SSE-NEXT: pextrb $8, %xmm0, %ecx ; X32-SSE-NEXT: pextrb $8, %xmm1, %ecx
; X32-SSE-NEXT: addl $12, %esp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: xor_v3i8_as_i24: ; X64-SSE-LABEL: xor_v3i8_as_i24:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movd %ecx, %xmm0 ; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: pinsrd $1, %r8d, %xmm0 ; X64-SSE-NEXT: pinsrd $1, %r8d, %xmm0
; X64-SSE-NEXT: pinsrd $2, %r9d, %xmm0 ; X64-SSE-NEXT: pinsrd $2, %r9d, %xmm0
; X64-SSE-NEXT: movdqa {{.*#+}} xmm1 = <0,4,8,128,u,u,u,u,u,u,u,u,u,u,u,u> ; X64-SSE-NEXT: movd %edi, %xmm1
; X64-SSE-NEXT: pshufb %xmm1, %xmm0 ; X64-SSE-NEXT: pinsrd $1, %esi, %xmm1
; X64-SSE-NEXT: movd %xmm0, %eax ; X64-SSE-NEXT: pinsrd $2, %edx, %xmm1
; X64-SSE-NEXT: movd %edi, %xmm0 ; X64-SSE-NEXT: pxor %xmm0, %xmm1
; X64-SSE-NEXT: pinsrd $1, %esi, %xmm0 ; X64-SSE-NEXT: pextrb $0, %xmm1, %eax
; X64-SSE-NEXT: pinsrd $2, %edx, %xmm0 ; X64-SSE-NEXT: pextrb $4, %xmm1, %edx
; X64-SSE-NEXT: pshufb %xmm1, %xmm0 ; X64-SSE-NEXT: pextrb $8, %xmm1, %ecx
; X64-SSE-NEXT: movd %xmm0, %ecx
; X64-SSE-NEXT: xorl %eax, %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; X64-SSE-NEXT: pextrb $0, %xmm0, %eax
; X64-SSE-NEXT: pextrb $4, %xmm0, %edx
; X64-SSE-NEXT: pextrb $8, %xmm0, %ecx
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast <3 x i8> %a to i24 %1 = bitcast <3 x i8> %a to i24
%2 = bitcast <3 x i8> %b to i24 %2 = bitcast <3 x i8> %b to i24
%3 = xor i24 %1, %2 %3 = xor i24 %1, %2
%4 = bitcast i24 %3 to <3 x i8> %4 = bitcast i24 %3 to <3 x i8>
ret <3 x i8> %4 ret <3 x i8> %4
} }
define <3 x i8> @or_v3i8_as_i24(<3 x i8> %a, <3 x i8> %b) nounwind { define <3 x i8> @or_v3i8_as_i24(<3 x i8> %a, <3 x i8> %b) nounwind {
; X32-SSE-LABEL: or_v3i8_as_i24: ; X32-SSE-LABEL: or_v3i8_as_i24:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: subl $12, %esp
; X32-SSE-NEXT: pinsrb $0, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: pinsrb $1, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: pinsrb $2, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: movd %xmm0, %eax
; X32-SSE-NEXT: pinsrb $0, {{[0-9]+}}(%esp), %xmm0 ; X32-SSE-NEXT: pinsrb $0, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: pinsrb $1, {{[0-9]+}}(%esp), %xmm0 ; X32-SSE-NEXT: pinsrb $4, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: pinsrb $2, {{[0-9]+}}(%esp), %xmm0 ; X32-SSE-NEXT: pinsrb $8, {{[0-9]+}}(%esp), %xmm0
; X32-SSE-NEXT: movd %xmm0, %ecx ; X32-SSE-NEXT: pinsrb $0, {{[0-9]+}}(%esp), %xmm1
; X32-SSE-NEXT: orl %eax, %ecx ; X32-SSE-NEXT: pinsrb $4, {{[0-9]+}}(%esp), %xmm1
; X32-SSE-NEXT: movd %ecx, %xmm0 ; X32-SSE-NEXT: pinsrb $8, {{[0-9]+}}(%esp), %xmm1
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; X32-SSE-NEXT: por %xmm0, %xmm1
; X32-SSE-NEXT: pextrb $0, %xmm0, %eax ; X32-SSE-NEXT: pextrb $0, %xmm1, %eax
; X32-SSE-NEXT: pextrb $4, %xmm0, %edx ; X32-SSE-NEXT: pextrb $4, %xmm1, %edx
; X32-SSE-NEXT: pextrb $8, %xmm0, %ecx ; X32-SSE-NEXT: pextrb $8, %xmm1, %ecx
; X32-SSE-NEXT: addl $12, %esp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: or_v3i8_as_i24: ; X64-SSE-LABEL: or_v3i8_as_i24:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movd %ecx, %xmm0 ; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: pinsrd $1, %r8d, %xmm0 ; X64-SSE-NEXT: pinsrd $1, %r8d, %xmm0
; X64-SSE-NEXT: pinsrd $2, %r9d, %xmm0 ; X64-SSE-NEXT: pinsrd $2, %r9d, %xmm0
; X64-SSE-NEXT: movdqa {{.*#+}} xmm1 = <0,4,8,128,u,u,u,u,u,u,u,u,u,u,u,u> ; X64-SSE-NEXT: movd %edi, %xmm1
; X64-SSE-NEXT: pshufb %xmm1, %xmm0 ; X64-SSE-NEXT: pinsrd $1, %esi, %xmm1
; X64-SSE-NEXT: movd %xmm0, %eax ; X64-SSE-NEXT: pinsrd $2, %edx, %xmm1
; X64-SSE-NEXT: movd %edi, %xmm0 ; X64-SSE-NEXT: por %xmm0, %xmm1
; X64-SSE-NEXT: pinsrd $1, %esi, %xmm0 ; X64-SSE-NEXT: pextrb $0, %xmm1, %eax
; X64-SSE-NEXT: pinsrd $2, %edx, %xmm0 ; X64-SSE-NEXT: pextrb $4, %xmm1, %edx
; X64-SSE-NEXT: pshufb %xmm1, %xmm0 ; X64-SSE-NEXT: pextrb $8, %xmm1, %ecx
; X64-SSE-NEXT: movd %xmm0, %ecx
; X64-SSE-NEXT: orl %eax, %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; X64-SSE-NEXT: pextrb $0, %xmm0, %eax
; X64-SSE-NEXT: pextrb $4, %xmm0, %edx
; X64-SSE-NEXT: pextrb $8, %xmm0, %ecx
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast <3 x i8> %a to i24 %1 = bitcast <3 x i8> %a to i24
%2 = bitcast <3 x i8> %b to i24 %2 = bitcast <3 x i8> %b to i24
%3 = or i24 %1, %2 %3 = or i24 %1, %2
%4 = bitcast i24 %3 to <3 x i8> %4 = bitcast i24 %3 to <3 x i8>
ret <3 x i8> %4 ret <3 x i8> %4
} }
; ;
; AND/XOR/OR v8i3 as i24 ; AND/XOR/OR v8i3 as i24
; ;
define <8 x i3> @and_v8i3_as_i24(<8 x i3> %a, <8 x i3> %b) nounwind { define <8 x i3> @and_v8i3_as_i24(<8 x i3> %a, <8 x i3> %b) nounwind {
; X32-SSE-LABEL: and_v8i3_as_i24: ; X32-SSE-LABEL: and_v8i3_as_i24:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pushl %ebp ; X32-SSE-NEXT: andps %xmm1, %xmm0
; X32-SSE-NEXT: movl %esp, %ebp
; X32-SSE-NEXT: andl $-8, %esp
; X32-SSE-NEXT: subl $24, %esp
; X32-SSE-NEXT: pextrw $7, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $6, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $5, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $4, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $3, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $2, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $1, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $7, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $6, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $5, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $4, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $3, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $2, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $1, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movd %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: shll $16, %eax
; X32-SSE-NEXT: movzwl (%esp), %ecx
; X32-SSE-NEXT: orl %eax, %ecx
; X32-SSE-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; X32-SSE-NEXT: shll $16, %edx
; X32-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: orl %edx, %eax
; X32-SSE-NEXT: andl %ecx, %eax
; X32-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: shrl $16, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $3, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $7, %edx
; X32-SSE-NEXT: movd %edx, %xmm1
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $6, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $9, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm1
; X32-SSE-NEXT: shrl $15, %eax
; X32-SSE-NEXT: pinsrw $5, %eax, %xmm1
; X32-SSE-NEXT: pxor %xmm0, %xmm0
; X32-SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
; X32-SSE-NEXT: movl %ebp, %esp
; X32-SSE-NEXT: popl %ebp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: and_v8i3_as_i24: ; X64-SSE-LABEL: and_v8i3_as_i24:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pextrw $7, %xmm1, %eax ; X64-SSE-NEXT: andps %xmm1, %xmm0
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $7, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: shll $16, %eax
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %ecx
; X64-SSE-NEXT: orl %eax, %ecx
; X64-SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: shll $16, %eax
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %edx
; X64-SSE-NEXT: orl %eax, %edx
; X64-SSE-NEXT: andl %ecx, %edx
; X64-SSE-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: shrl $16, %edx
; X64-SSE-NEXT: movb %dl, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $3, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: movl %eax, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: movd %edx, %xmm0
; X64-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $6, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $9, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $12, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X64-SSE-NEXT: shrl $15, %eax
; X64-SSE-NEXT: movzwl %ax, %eax
; X64-SSE-NEXT: pinsrw $5, %eax, %xmm0
; X64-SSE-NEXT: xorl %eax, %eax
; X64-SSE-NEXT: pinsrw $6, %eax, %xmm0
; X64-SSE-NEXT: pinsrw $7, %eax, %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast <8 x i3> %a to i24 %1 = bitcast <8 x i3> %a to i24
%2 = bitcast <8 x i3> %b to i24 %2 = bitcast <8 x i3> %b to i24
%3 = and i24 %1, %2 %3 = and i24 %1, %2
%4 = bitcast i24 %3 to <8 x i3> %4 = bitcast i24 %3 to <8 x i3>
ret <8 x i3> %4 ret <8 x i3> %4
} }
define <8 x i3> @xor_v8i3_as_i24(<8 x i3> %a, <8 x i3> %b) nounwind { define <8 x i3> @xor_v8i3_as_i24(<8 x i3> %a, <8 x i3> %b) nounwind {
; X32-SSE-LABEL: xor_v8i3_as_i24: ; X32-SSE-LABEL: xor_v8i3_as_i24:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pushl %ebp ; X32-SSE-NEXT: xorps %xmm1, %xmm0
; X32-SSE-NEXT: movl %esp, %ebp
; X32-SSE-NEXT: andl $-8, %esp
; X32-SSE-NEXT: subl $24, %esp
; X32-SSE-NEXT: pextrw $7, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $6, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $5, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $4, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $3, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $2, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $1, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $7, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $6, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $5, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $4, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $3, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $2, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $1, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movd %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: shll $16, %eax
; X32-SSE-NEXT: movzwl (%esp), %ecx
; X32-SSE-NEXT: orl %eax, %ecx
; X32-SSE-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; X32-SSE-NEXT: shll $16, %edx
; X32-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: orl %edx, %eax
; X32-SSE-NEXT: xorl %ecx, %eax
; X32-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: shrl $16, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $3, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $7, %edx
; X32-SSE-NEXT: movd %edx, %xmm1
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $6, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $9, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm1
; X32-SSE-NEXT: shrl $15, %eax
; X32-SSE-NEXT: pinsrw $5, %eax, %xmm1
; X32-SSE-NEXT: pxor %xmm0, %xmm0
; X32-SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
; X32-SSE-NEXT: movl %ebp, %esp
; X32-SSE-NEXT: popl %ebp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: xor_v8i3_as_i24: ; X64-SSE-LABEL: xor_v8i3_as_i24:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pextrw $7, %xmm1, %eax ; X64-SSE-NEXT: xorps %xmm1, %xmm0
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $7, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: shll $16, %eax
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %ecx
; X64-SSE-NEXT: orl %eax, %ecx
; X64-SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: shll $16, %eax
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %edx
; X64-SSE-NEXT: orl %eax, %edx
; X64-SSE-NEXT: xorl %ecx, %edx
; X64-SSE-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: shrl $16, %edx
; X64-SSE-NEXT: movb %dl, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $3, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: movl %eax, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: movd %edx, %xmm0
; X64-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $6, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $9, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $12, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X64-SSE-NEXT: shrl $15, %eax
; X64-SSE-NEXT: movzwl %ax, %eax
; X64-SSE-NEXT: pinsrw $5, %eax, %xmm0
; X64-SSE-NEXT: xorl %eax, %eax
; X64-SSE-NEXT: pinsrw $6, %eax, %xmm0
; X64-SSE-NEXT: pinsrw $7, %eax, %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast <8 x i3> %a to i24 %1 = bitcast <8 x i3> %a to i24
%2 = bitcast <8 x i3> %b to i24 %2 = bitcast <8 x i3> %b to i24
%3 = xor i24 %1, %2 %3 = xor i24 %1, %2
%4 = bitcast i24 %3 to <8 x i3> %4 = bitcast i24 %3 to <8 x i3>
ret <8 x i3> %4 ret <8 x i3> %4
} }
define <8 x i3> @or_v8i3_as_i24(<8 x i3> %a, <8 x i3> %b) nounwind { define <8 x i3> @or_v8i3_as_i24(<8 x i3> %a, <8 x i3> %b) nounwind {
; X32-SSE-LABEL: or_v8i3_as_i24: ; X32-SSE-LABEL: or_v8i3_as_i24:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pushl %ebp ; X32-SSE-NEXT: orps %xmm1, %xmm0
; X32-SSE-NEXT: movl %esp, %ebp
; X32-SSE-NEXT: andl $-8, %esp
; X32-SSE-NEXT: subl $24, %esp
; X32-SSE-NEXT: pextrw $7, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $6, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $5, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $4, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $3, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $2, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $1, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $7, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $6, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $5, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $4, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $3, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $2, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $1, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movd %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movzbl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: shll $16, %eax
; X32-SSE-NEXT: movzwl (%esp), %ecx
; X32-SSE-NEXT: orl %eax, %ecx
; X32-SSE-NEXT: movzbl {{[0-9]+}}(%esp), %edx
; X32-SSE-NEXT: shll $16, %edx
; X32-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: orl %edx, %eax
; X32-SSE-NEXT: orl %ecx, %eax
; X32-SSE-NEXT: movw %ax, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: shrl $16, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movzwl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $3, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $7, %edx
; X32-SSE-NEXT: movd %edx, %xmm1
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $6, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $9, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $7, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm1
; X32-SSE-NEXT: shrl $15, %eax
; X32-SSE-NEXT: pinsrw $5, %eax, %xmm1
; X32-SSE-NEXT: pxor %xmm0, %xmm0
; X32-SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7]
; X32-SSE-NEXT: movl %ebp, %esp
; X32-SSE-NEXT: popl %ebp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: or_v8i3_as_i24: ; X64-SSE-LABEL: or_v8i3_as_i24:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pextrw $7, %xmm1, %eax ; X64-SSE-NEXT: orps %xmm1, %xmm0
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $7, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: shll $16, %eax
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %ecx
; X64-SSE-NEXT: orl %eax, %ecx
; X64-SSE-NEXT: movzbl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: shll $16, %eax
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %edx
; X64-SSE-NEXT: orl %eax, %edx
; X64-SSE-NEXT: orl %ecx, %edx
; X64-SSE-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: shrl $16, %edx
; X64-SSE-NEXT: movb %dl, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movzwl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $3, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: movl %eax, %edx
; X64-SSE-NEXT: andl $7, %edx
; X64-SSE-NEXT: movd %edx, %xmm0
; X64-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $6, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $9, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $12, %ecx
; X64-SSE-NEXT: andl $7, %ecx
; X64-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X64-SSE-NEXT: shrl $15, %eax
; X64-SSE-NEXT: movzwl %ax, %eax
; X64-SSE-NEXT: pinsrw $5, %eax, %xmm0
; X64-SSE-NEXT: xorl %eax, %eax
; X64-SSE-NEXT: pinsrw $6, %eax, %xmm0
; X64-SSE-NEXT: pinsrw $7, %eax, %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast <8 x i3> %a to i24 %1 = bitcast <8 x i3> %a to i24
%2 = bitcast <8 x i3> %b to i24 %2 = bitcast <8 x i3> %b to i24
%3 = or i24 %1, %2 %3 = or i24 %1, %2
%4 = bitcast i24 %3 to <8 x i3> %4 = bitcast i24 %3 to <8 x i3>
ret <8 x i3> %4 ret <8 x i3> %4
} }

llvm/trunk/test/CodeGen/X86/widen_bitops-1.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE42 ; RUN: llc < %s -mtriple=i686-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X32-SSE --check-prefix=X32-SSE42
; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE42 ; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+sse4.2 | FileCheck %s --check-prefix=X64-SSE --check-prefix=X64-SSE42
; ;
; AND/XOR/OR i32 as v4i8 ; AND/XOR/OR i32 as v4i8
; ;
define i32 @and_i32_as_v4i8(i32 %a, i32 %b) nounwind { define i32 @and_i32_as_v4i8(i32 %a, i32 %b) nounwind {
; X32-SSE-LABEL: and_i32_as_v4i8: ; X32-SSE-LABEL: and_i32_as_v4i8:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pushl %eax ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero ; X32-SSE-NEXT: andl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; X32-SSE-NEXT: pand %xmm0, %xmm1
; X32-SSE-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: popl %ecx
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: and_i32_as_v4i8: ; X64-SSE-LABEL: and_i32_as_v4i8:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movd %esi, %xmm0 ; X64-SSE-NEXT: andl %esi, %edi
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: movd %edi, %xmm1
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
; X64-SSE-NEXT: pand %xmm0, %xmm1
; X64-SSE-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast i32 %a to <4 x i8> %1 = bitcast i32 %a to <4 x i8>
%2 = bitcast i32 %b to <4 x i8> %2 = bitcast i32 %b to <4 x i8>
%3 = and <4 x i8> %1, %2 %3 = and <4 x i8> %1, %2
%4 = bitcast <4 x i8> %3 to i32 %4 = bitcast <4 x i8> %3 to i32
ret i32 %4 ret i32 %4
} }
define i32 @xor_i32_as_v4i8(i32 %a, i32 %b) nounwind { define i32 @xor_i32_as_v4i8(i32 %a, i32 %b) nounwind {
; X32-SSE-LABEL: xor_i32_as_v4i8: ; X32-SSE-LABEL: xor_i32_as_v4i8:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pushl %eax ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero ; X32-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; X32-SSE-NEXT: pxor %xmm0, %xmm1
; X32-SSE-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: popl %ecx
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: xor_i32_as_v4i8: ; X64-SSE-LABEL: xor_i32_as_v4i8:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movd %esi, %xmm0 ; X64-SSE-NEXT: xorl %esi, %edi
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: movd %edi, %xmm1
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
; X64-SSE-NEXT: pxor %xmm0, %xmm1
; X64-SSE-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast i32 %a to <4 x i8> %1 = bitcast i32 %a to <4 x i8>
%2 = bitcast i32 %b to <4 x i8> %2 = bitcast i32 %b to <4 x i8>
%3 = xor <4 x i8> %1, %2 %3 = xor <4 x i8> %1, %2
%4 = bitcast <4 x i8> %3 to i32 %4 = bitcast <4 x i8> %3 to i32
ret i32 %4 ret i32 %4
} }
define i32 @or_i32_as_v4i8(i32 %a, i32 %b) nounwind { define i32 @or_i32_as_v4i8(i32 %a, i32 %b) nounwind {
; X32-SSE-LABEL: or_i32_as_v4i8: ; X32-SSE-LABEL: or_i32_as_v4i8:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pushl %eax ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero ; X32-SSE-NEXT: orl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
; X32-SSE-NEXT: por %xmm0, %xmm1
; X32-SSE-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: popl %ecx
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: or_i32_as_v4i8: ; X64-SSE-LABEL: or_i32_as_v4i8:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movd %esi, %xmm0 ; X64-SSE-NEXT: orl %esi, %edi
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero ; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: movd %edi, %xmm1
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
; X64-SSE-NEXT: por %xmm0, %xmm1
; X64-SSE-NEXT: pshufb {{.*#+}} xmm1 = xmm1[0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u]
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast i32 %a to <4 x i8> %1 = bitcast i32 %a to <4 x i8>
%2 = bitcast i32 %b to <4 x i8> %2 = bitcast i32 %b to <4 x i8>
%3 = or <4 x i8> %1, %2 %3 = or <4 x i8> %1, %2
%4 = bitcast <4 x i8> %3 to i32 %4 = bitcast <4 x i8> %3 to i32
ret i32 %4 ret i32 %4
} }
; ;
; AND/XOR/OR i32 as v8i4 ; AND/XOR/OR i32 as v8i4
; ;
define i32 @and_i32_as_v8i4(i32 %a, i32 %b) nounwind { define i32 @and_i32_as_v8i4(i32 %a, i32 %b) nounwind {
; X32-SSE-LABEL: and_i32_as_v8i4: ; X32-SSE-LABEL: and_i32_as_v8i4:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pushl %ebp ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: movl %esp, %ebp ; X32-SSE-NEXT: andl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: andl $-8, %esp
; X32-SSE-NEXT: subl $24, %esp
; X32-SSE-NEXT: movl 12(%ebp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $4, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $15, %edx
; X32-SSE-NEXT: movd %edx, %xmm0
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $8, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $16, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $20, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $5, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $24, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $6, %ecx, %xmm0
; X32-SSE-NEXT: shrl $28, %eax
; X32-SSE-NEXT: pinsrw $7, %eax, %xmm0
; X32-SSE-NEXT: movl 8(%ebp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $4, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $15, %edx
; X32-SSE-NEXT: movd %edx, %xmm1
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $8, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $16, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $20, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $5, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $24, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $6, %ecx, %xmm1
; X32-SSE-NEXT: shrl $28, %eax
; X32-SSE-NEXT: pinsrw $7, %eax, %xmm1
; X32-SSE-NEXT: pand %xmm0, %xmm1
; X32-SSE-NEXT: pextrw $7, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $6, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $5, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $4, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $3, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $2, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $1, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movl (%esp), %eax
; X32-SSE-NEXT: movl %ebp, %esp
; X32-SSE-NEXT: popl %ebp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: and_i32_as_v8i4: ; X64-SSE-LABEL: and_i32_as_v8i4:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movl %esi, %eax ; X64-SSE-NEXT: andl %esi, %edi
; X64-SSE-NEXT: shrl $4, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movl %esi, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: pinsrw $1, %eax, %xmm0
; X64-SSE-NEXT: movl %esi, %eax
; X64-SSE-NEXT: shrl $8, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $2, %eax, %xmm0
; X64-SSE-NEXT: movl %esi, %eax
; X64-SSE-NEXT: shrl $12, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $3, %eax, %xmm0
; X64-SSE-NEXT: movl %esi, %eax
; X64-SSE-NEXT: shrl $16, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $4, %eax, %xmm0
; X64-SSE-NEXT: movl %esi, %eax
; X64-SSE-NEXT: shrl $20, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $5, %eax, %xmm0
; X64-SSE-NEXT: movl %esi, %eax
; X64-SSE-NEXT: shrl $24, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $6, %eax, %xmm0
; X64-SSE-NEXT: shrl $28, %esi
; X64-SSE-NEXT: pinsrw $7, %esi, %xmm0
; X64-SSE-NEXT: movl %edi, %eax ; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $4, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movl %edi, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: movd %ecx, %xmm1
; X64-SSE-NEXT: pinsrw $1, %eax, %xmm1
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $8, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $2, %eax, %xmm1
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $12, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $3, %eax, %xmm1
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $16, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $4, %eax, %xmm1
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $20, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $5, %eax, %xmm1
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $24, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $6, %eax, %xmm1
; X64-SSE-NEXT: shrl $28, %edi
; X64-SSE-NEXT: pinsrw $7, %edi, %xmm1
; X64-SSE-NEXT: pand %xmm0, %xmm1
; X64-SSE-NEXT: pextrw $7, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast i32 %a to <8 x i4> %1 = bitcast i32 %a to <8 x i4>
%2 = bitcast i32 %b to <8 x i4> %2 = bitcast i32 %b to <8 x i4>
%3 = and <8 x i4> %1, %2 %3 = and <8 x i4> %1, %2
%4 = bitcast <8 x i4> %3 to i32 %4 = bitcast <8 x i4> %3 to i32
ret i32 %4 ret i32 %4
} }
define i32 @xor_i32_as_v8i4(i32 %a, i32 %b) nounwind { define i32 @xor_i32_as_v8i4(i32 %a, i32 %b) nounwind {
; X32-SSE-LABEL: xor_i32_as_v8i4: ; X32-SSE-LABEL: xor_i32_as_v8i4:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pushl %ebp ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: movl %esp, %ebp ; X32-SSE-NEXT: xorl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: andl $-8, %esp
; X32-SSE-NEXT: subl $24, %esp
; X32-SSE-NEXT: movl 12(%ebp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $4, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $15, %edx
; X32-SSE-NEXT: movd %edx, %xmm0
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $8, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $16, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $20, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $5, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $24, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $6, %ecx, %xmm0
; X32-SSE-NEXT: shrl $28, %eax
; X32-SSE-NEXT: pinsrw $7, %eax, %xmm0
; X32-SSE-NEXT: movl 8(%ebp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $4, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $15, %edx
; X32-SSE-NEXT: movd %edx, %xmm1
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $8, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $16, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $20, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $5, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $24, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $6, %ecx, %xmm1
; X32-SSE-NEXT: shrl $28, %eax
; X32-SSE-NEXT: pinsrw $7, %eax, %xmm1
; X32-SSE-NEXT: pxor %xmm0, %xmm1
; X32-SSE-NEXT: pextrw $7, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $6, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $5, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $4, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $3, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $2, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $1, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movl (%esp), %eax
; X32-SSE-NEXT: movl %ebp, %esp
; X32-SSE-NEXT: popl %ebp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: xor_i32_as_v8i4: ; X64-SSE-LABEL: xor_i32_as_v8i4:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movl %esi, %eax ; X64-SSE-NEXT: xorl %esi, %edi
; X64-SSE-NEXT: shrl $4, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movl %esi, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: pinsrw $1, %eax, %xmm0
; X64-SSE-NEXT: movl %esi, %eax
; X64-SSE-NEXT: shrl $8, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $2, %eax, %xmm0
; X64-SSE-NEXT: movl %esi, %eax
; X64-SSE-NEXT: shrl $12, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $3, %eax, %xmm0
; X64-SSE-NEXT: movl %esi, %eax
; X64-SSE-NEXT: shrl $16, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $4, %eax, %xmm0
; X64-SSE-NEXT: movl %esi, %eax
; X64-SSE-NEXT: shrl $20, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $5, %eax, %xmm0
; X64-SSE-NEXT: movl %esi, %eax
; X64-SSE-NEXT: shrl $24, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $6, %eax, %xmm0
; X64-SSE-NEXT: shrl $28, %esi
; X64-SSE-NEXT: pinsrw $7, %esi, %xmm0
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $4, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movl %edi, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: movd %ecx, %xmm1
; X64-SSE-NEXT: pinsrw $1, %eax, %xmm1
; X64-SSE-NEXT: movl %edi, %eax ; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $8, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $2, %eax, %xmm1
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $12, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $3, %eax, %xmm1
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $16, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $4, %eax, %xmm1
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $20, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $5, %eax, %xmm1
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $24, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $6, %eax, %xmm1
; X64-SSE-NEXT: shrl $28, %edi
; X64-SSE-NEXT: pinsrw $7, %edi, %xmm1
; X64-SSE-NEXT: pxor %xmm0, %xmm1
; X64-SSE-NEXT: pextrw $7, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast i32 %a to <8 x i4> %1 = bitcast i32 %a to <8 x i4>
%2 = bitcast i32 %b to <8 x i4> %2 = bitcast i32 %b to <8 x i4>
%3 = xor <8 x i4> %1, %2 %3 = xor <8 x i4> %1, %2
%4 = bitcast <8 x i4> %3 to i32 %4 = bitcast <8 x i4> %3 to i32
ret i32 %4 ret i32 %4
} }
define i32 @or_i32_as_v8i4(i32 %a, i32 %b) nounwind { define i32 @or_i32_as_v8i4(i32 %a, i32 %b) nounwind {
; X32-SSE-LABEL: or_i32_as_v8i4: ; X32-SSE-LABEL: or_i32_as_v8i4:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pushl %ebp ; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: movl %esp, %ebp ; X32-SSE-NEXT: orl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: andl $-8, %esp
; X32-SSE-NEXT: subl $24, %esp
; X32-SSE-NEXT: movl 12(%ebp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $4, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $15, %edx
; X32-SSE-NEXT: movd %edx, %xmm0
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $8, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $16, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $20, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $5, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $24, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $6, %ecx, %xmm0
; X32-SSE-NEXT: shrl $28, %eax
; X32-SSE-NEXT: pinsrw $7, %eax, %xmm0
; X32-SSE-NEXT: movl 8(%ebp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $4, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $15, %edx
; X32-SSE-NEXT: movd %edx, %xmm1
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $8, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $16, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $20, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $5, %ecx, %xmm1
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $24, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $6, %ecx, %xmm1
; X32-SSE-NEXT: shrl $28, %eax
; X32-SSE-NEXT: pinsrw $7, %eax, %xmm1
; X32-SSE-NEXT: por %xmm0, %xmm1
; X32-SSE-NEXT: pextrw $7, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $6, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $5, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $4, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $3, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $2, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $1, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movl (%esp), %eax
; X32-SSE-NEXT: movl %ebp, %esp
; X32-SSE-NEXT: popl %ebp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: or_i32_as_v8i4: ; X64-SSE-LABEL: or_i32_as_v8i4:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movl %esi, %eax ; X64-SSE-NEXT: orl %esi, %edi
; X64-SSE-NEXT: shrl $4, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movl %esi, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: pinsrw $1, %eax, %xmm0
; X64-SSE-NEXT: movl %esi, %eax
; X64-SSE-NEXT: shrl $8, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $2, %eax, %xmm0
; X64-SSE-NEXT: movl %esi, %eax
; X64-SSE-NEXT: shrl $12, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $3, %eax, %xmm0
; X64-SSE-NEXT: movl %esi, %eax
; X64-SSE-NEXT: shrl $16, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $4, %eax, %xmm0
; X64-SSE-NEXT: movl %esi, %eax
; X64-SSE-NEXT: shrl $20, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $5, %eax, %xmm0
; X64-SSE-NEXT: movl %esi, %eax
; X64-SSE-NEXT: shrl $24, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $6, %eax, %xmm0
; X64-SSE-NEXT: shrl $28, %esi
; X64-SSE-NEXT: pinsrw $7, %esi, %xmm0
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $4, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movl %edi, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: movd %ecx, %xmm1
; X64-SSE-NEXT: pinsrw $1, %eax, %xmm1
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $8, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $2, %eax, %xmm1
; X64-SSE-NEXT: movl %edi, %eax ; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $12, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $3, %eax, %xmm1
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $16, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $4, %eax, %xmm1
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $20, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $5, %eax, %xmm1
; X64-SSE-NEXT: movl %edi, %eax
; X64-SSE-NEXT: shrl $24, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: pinsrw $6, %eax, %xmm1
; X64-SSE-NEXT: shrl $28, %edi
; X64-SSE-NEXT: pinsrw $7, %edi, %xmm1
; X64-SSE-NEXT: por %xmm0, %xmm1
; X64-SSE-NEXT: pextrw $7, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast i32 %a to <8 x i4> %1 = bitcast i32 %a to <8 x i4>
%2 = bitcast i32 %b to <8 x i4> %2 = bitcast i32 %b to <8 x i4>
%3 = or <8 x i4> %1, %2 %3 = or <8 x i4> %1, %2
%4 = bitcast <8 x i4> %3 to i32 %4 = bitcast <8 x i4> %3 to i32
ret i32 %4 ret i32 %4
} }
; ;
; AND/XOR/OR v4i8 as i32 ; AND/XOR/OR v4i8 as i32
; ;
define <4 x i8> @and_v4i8_as_i32(<4 x i8> %a, <4 x i8> %b) nounwind { define <4 x i8> @and_v4i8_as_i32(<4 x i8> %a, <4 x i8> %b) nounwind {
; X32-SSE-LABEL: and_v4i8_as_i32: ; X32-SSE-LABEL: and_v4i8_as_i32:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: subl $12, %esp ; X32-SSE-NEXT: andps %xmm1, %xmm0
; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = <0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u>
; X32-SSE-NEXT: pshufb %xmm2, %xmm1
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: pshufb %xmm2, %xmm0
; X32-SSE-NEXT: movd %xmm0, %ecx
; X32-SSE-NEXT: andl %eax, %ecx
; X32-SSE-NEXT: movd %ecx, %xmm0
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; X32-SSE-NEXT: addl $12, %esp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: and_v4i8_as_i32: ; X64-SSE-LABEL: and_v4i8_as_i32:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movdqa {{.*#+}} xmm2 = <0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u> ; X64-SSE-NEXT: andps %xmm1, %xmm0
; X64-SSE-NEXT: pshufb %xmm2, %xmm1
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: pshufb %xmm2, %xmm0
; X64-SSE-NEXT: movd %xmm0, %ecx
; X64-SSE-NEXT: andl %eax, %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast <4 x i8> %a to i32 %1 = bitcast <4 x i8> %a to i32
%2 = bitcast <4 x i8> %b to i32 %2 = bitcast <4 x i8> %b to i32
%3 = and i32 %1, %2 %3 = and i32 %1, %2
%4 = bitcast i32 %3 to <4 x i8> %4 = bitcast i32 %3 to <4 x i8>
ret <4 x i8> %4 ret <4 x i8> %4
} }
define <4 x i8> @xor_v4i8_as_i32(<4 x i8> %a, <4 x i8> %b) nounwind { define <4 x i8> @xor_v4i8_as_i32(<4 x i8> %a, <4 x i8> %b) nounwind {
; X32-SSE-LABEL: xor_v4i8_as_i32: ; X32-SSE-LABEL: xor_v4i8_as_i32:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: subl $12, %esp ; X32-SSE-NEXT: xorps %xmm1, %xmm0
; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = <0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u>
; X32-SSE-NEXT: pshufb %xmm2, %xmm1
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: pshufb %xmm2, %xmm0
; X32-SSE-NEXT: movd %xmm0, %ecx
; X32-SSE-NEXT: xorl %eax, %ecx
; X32-SSE-NEXT: movd %ecx, %xmm0
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; X32-SSE-NEXT: addl $12, %esp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: xor_v4i8_as_i32: ; X64-SSE-LABEL: xor_v4i8_as_i32:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movdqa {{.*#+}} xmm2 = <0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u> ; X64-SSE-NEXT: xorps %xmm1, %xmm0
; X64-SSE-NEXT: pshufb %xmm2, %xmm1
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: pshufb %xmm2, %xmm0
; X64-SSE-NEXT: movd %xmm0, %ecx
; X64-SSE-NEXT: xorl %eax, %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast <4 x i8> %a to i32 %1 = bitcast <4 x i8> %a to i32
%2 = bitcast <4 x i8> %b to i32 %2 = bitcast <4 x i8> %b to i32
%3 = xor i32 %1, %2 %3 = xor i32 %1, %2
%4 = bitcast i32 %3 to <4 x i8> %4 = bitcast i32 %3 to <4 x i8>
ret <4 x i8> %4 ret <4 x i8> %4
} }
define <4 x i8> @or_v4i8_as_i32(<4 x i8> %a, <4 x i8> %b) nounwind { define <4 x i8> @or_v4i8_as_i32(<4 x i8> %a, <4 x i8> %b) nounwind {
; X32-SSE-LABEL: or_v4i8_as_i32: ; X32-SSE-LABEL: or_v4i8_as_i32:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: subl $12, %esp ; X32-SSE-NEXT: orps %xmm1, %xmm0
; X32-SSE-NEXT: movdqa {{.*#+}} xmm2 = <0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u>
; X32-SSE-NEXT: pshufb %xmm2, %xmm1
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: pshufb %xmm2, %xmm0
; X32-SSE-NEXT: movd %xmm0, %ecx
; X32-SSE-NEXT: orl %eax, %ecx
; X32-SSE-NEXT: movd %ecx, %xmm0
; X32-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; X32-SSE-NEXT: addl $12, %esp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: or_v4i8_as_i32: ; X64-SSE-LABEL: or_v4i8_as_i32:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: movdqa {{.*#+}} xmm2 = <0,4,8,12,u,u,u,u,u,u,u,u,u,u,u,u> ; X64-SSE-NEXT: orps %xmm1, %xmm0
; X64-SSE-NEXT: pshufb %xmm2, %xmm1
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: pshufb %xmm2, %xmm0
; X64-SSE-NEXT: movd %xmm0, %ecx
; X64-SSE-NEXT: orl %eax, %ecx
; X64-SSE-NEXT: movd %ecx, %xmm0
; X64-SSE-NEXT: pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast <4 x i8> %a to i32 %1 = bitcast <4 x i8> %a to i32
%2 = bitcast <4 x i8> %b to i32 %2 = bitcast <4 x i8> %b to i32
%3 = or i32 %1, %2 %3 = or i32 %1, %2
%4 = bitcast i32 %3 to <4 x i8> %4 = bitcast i32 %3 to <4 x i8>
ret <4 x i8> %4 ret <4 x i8> %4
} }
; ;
; AND/XOR/OR v8i4 as i32 ; AND/XOR/OR v8i4 as i32
; ;
define <8 x i4> @and_v8i4_as_i32(<8 x i4> %a, <8 x i4> %b) nounwind { define <8 x i4> @and_v8i4_as_i32(<8 x i4> %a, <8 x i4> %b) nounwind {
; X32-SSE-LABEL: and_v8i4_as_i32: ; X32-SSE-LABEL: and_v8i4_as_i32:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pushl %ebp ; X32-SSE-NEXT: andps %xmm1, %xmm0
; X32-SSE-NEXT: movl %esp, %ebp
; X32-SSE-NEXT: andl $-8, %esp
; X32-SSE-NEXT: subl $24, %esp
; X32-SSE-NEXT: pextrw $7, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $6, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $5, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $4, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $3, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $2, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $1, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movd %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $7, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $6, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $5, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $4, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $3, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $2, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $1, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: andl (%esp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $4, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $15, %edx
; X32-SSE-NEXT: movd %edx, %xmm0
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $8, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $16, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $20, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $5, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $24, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $6, %ecx, %xmm0
; X32-SSE-NEXT: shrl $28, %eax
; X32-SSE-NEXT: pinsrw $7, %eax, %xmm0
; X32-SSE-NEXT: movl %ebp, %esp
; X32-SSE-NEXT: popl %ebp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: and_v8i4_as_i32: ; X64-SSE-LABEL: and_v8i4_as_i32:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pextrw $7, %xmm0, %eax ; X64-SSE-NEXT: andps %xmm1, %xmm0
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $7, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: andl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $4, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: movl %eax, %edx
; X64-SSE-NEXT: andl $15, %edx
; X64-SSE-NEXT: movd %edx, %xmm0
; X64-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $8, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $12, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $16, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $20, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: pinsrw $5, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $24, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: pinsrw $6, %ecx, %xmm0
; X64-SSE-NEXT: shrl $28, %eax
; X64-SSE-NEXT: pinsrw $7, %eax, %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast <8 x i4> %a to i32 %1 = bitcast <8 x i4> %a to i32
%2 = bitcast <8 x i4> %b to i32 %2 = bitcast <8 x i4> %b to i32
%3 = and i32 %1, %2 %3 = and i32 %1, %2
%4 = bitcast i32 %3 to <8 x i4> %4 = bitcast i32 %3 to <8 x i4>
ret <8 x i4> %4 ret <8 x i4> %4
} }
define <8 x i4> @xor_v8i4_as_i32(<8 x i4> %a, <8 x i4> %b) nounwind { define <8 x i4> @xor_v8i4_as_i32(<8 x i4> %a, <8 x i4> %b) nounwind {
; X32-SSE-LABEL: xor_v8i4_as_i32: ; X32-SSE-LABEL: xor_v8i4_as_i32:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pushl %ebp ; X32-SSE-NEXT: xorps %xmm1, %xmm0
; X32-SSE-NEXT: movl %esp, %ebp
; X32-SSE-NEXT: andl $-8, %esp
; X32-SSE-NEXT: subl $24, %esp
; X32-SSE-NEXT: pextrw $7, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $6, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $5, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $4, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $3, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $2, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $1, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movd %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $7, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $6, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $5, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $4, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $3, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $2, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $1, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: xorl (%esp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $4, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $15, %edx
; X32-SSE-NEXT: movd %edx, %xmm0
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $8, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $16, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $20, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $5, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $24, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $6, %ecx, %xmm0
; X32-SSE-NEXT: shrl $28, %eax
; X32-SSE-NEXT: pinsrw $7, %eax, %xmm0
; X32-SSE-NEXT: movl %ebp, %esp
; X32-SSE-NEXT: popl %ebp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: xor_v8i4_as_i32: ; X64-SSE-LABEL: xor_v8i4_as_i32:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pextrw $7, %xmm0, %eax ; X64-SSE-NEXT: xorps %xmm1, %xmm0
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $7, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: xorl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $4, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: movl %eax, %edx
; X64-SSE-NEXT: andl $15, %edx
; X64-SSE-NEXT: movd %edx, %xmm0
; X64-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $8, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $12, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $16, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $20, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: pinsrw $5, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $24, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: pinsrw $6, %ecx, %xmm0
; X64-SSE-NEXT: shrl $28, %eax
; X64-SSE-NEXT: pinsrw $7, %eax, %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast <8 x i4> %a to i32 %1 = bitcast <8 x i4> %a to i32
%2 = bitcast <8 x i4> %b to i32 %2 = bitcast <8 x i4> %b to i32
%3 = xor i32 %1, %2 %3 = xor i32 %1, %2
%4 = bitcast i32 %3 to <8 x i4> %4 = bitcast i32 %3 to <8 x i4>
ret <8 x i4> %4 ret <8 x i4> %4
} }
define <8 x i4> @or_v8i4_as_i32(<8 x i4> %a, <8 x i4> %b) nounwind { define <8 x i4> @or_v8i4_as_i32(<8 x i4> %a, <8 x i4> %b) nounwind {
; X32-SSE-LABEL: or_v8i4_as_i32: ; X32-SSE-LABEL: or_v8i4_as_i32:
; X32-SSE: # BB#0: ; X32-SSE: # BB#0:
; X32-SSE-NEXT: pushl %ebp ; X32-SSE-NEXT: orps %xmm1, %xmm0
; X32-SSE-NEXT: movl %esp, %ebp
; X32-SSE-NEXT: andl $-8, %esp
; X32-SSE-NEXT: subl $24, %esp
; X32-SSE-NEXT: pextrw $7, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $6, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $5, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $4, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $3, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $2, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $1, %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: movd %xmm0, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, {{[0-9]+}}(%esp)
; X32-SSE-NEXT: pextrw $7, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $6, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $5, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $4, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $3, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $2, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: pextrw $1, %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movd %xmm1, %eax
; X32-SSE-NEXT: andl $15, %eax
; X32-SSE-NEXT: movb %al, (%esp)
; X32-SSE-NEXT: movl {{[0-9]+}}(%esp), %eax
; X32-SSE-NEXT: orl (%esp), %eax
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $4, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: movl %eax, %edx
; X32-SSE-NEXT: andl $15, %edx
; X32-SSE-NEXT: movd %edx, %xmm0
; X32-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $8, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $12, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $16, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $20, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $5, %ecx, %xmm0
; X32-SSE-NEXT: movl %eax, %ecx
; X32-SSE-NEXT: shrl $24, %ecx
; X32-SSE-NEXT: andl $15, %ecx
; X32-SSE-NEXT: pinsrw $6, %ecx, %xmm0
; X32-SSE-NEXT: shrl $28, %eax
; X32-SSE-NEXT: pinsrw $7, %eax, %xmm0
; X32-SSE-NEXT: movl %ebp, %esp
; X32-SSE-NEXT: popl %ebp
; X32-SSE-NEXT: retl ; X32-SSE-NEXT: retl
; ;
; X64-SSE-LABEL: or_v8i4_as_i32: ; X64-SSE-LABEL: or_v8i4_as_i32:
; X64-SSE: # BB#0: ; X64-SSE: # BB#0:
; X64-SSE-NEXT: pextrw $7, %xmm0, %eax ; X64-SSE-NEXT: orps %xmm1, %xmm0
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm0, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $7, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $6, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $5, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $4, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $3, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $2, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: pextrw $1, %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movd %xmm1, %eax
; X64-SSE-NEXT: andl $15, %eax
; X64-SSE-NEXT: movb %al, -{{[0-9]+}}(%rsp)
; X64-SSE-NEXT: movl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: orl -{{[0-9]+}}(%rsp), %eax
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $4, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: movl %eax, %edx
; X64-SSE-NEXT: andl $15, %edx
; X64-SSE-NEXT: movd %edx, %xmm0
; X64-SSE-NEXT: pinsrw $1, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $8, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: pinsrw $2, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $12, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: pinsrw $3, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $16, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: pinsrw $4, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $20, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: pinsrw $5, %ecx, %xmm0
; X64-SSE-NEXT: movl %eax, %ecx
; X64-SSE-NEXT: shrl $24, %ecx
; X64-SSE-NEXT: andl $15, %ecx
; X64-SSE-NEXT: pinsrw $6, %ecx, %xmm0
; X64-SSE-NEXT: shrl $28, %eax
; X64-SSE-NEXT: pinsrw $7, %eax, %xmm0
; X64-SSE-NEXT: retq ; X64-SSE-NEXT: retq
%1 = bitcast <8 x i4> %a to i32 %1 = bitcast <8 x i4> %a to i32
%2 = bitcast <8 x i4> %b to i32 %2 = bitcast <8 x i4> %b to i32
%3 = or i32 %1, %2 %3 = or i32 %1, %2
%4 = bitcast i32 %3 to <8 x i4> %4 = bitcast i32 %3 to <8 x i4>
ret <8 x i4> %4 ret <8 x i4> %4
} }