This is an archive of the discontinued LLVM Phabricator instance.

Differential D18665

[AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth()
ClosedPublic

Authored by junbuml on Mar 31 2016, 12:47 PM.

Details

Reviewers
t.p.northover
jmolloy
mcrosier
Commits
rG760afcb3383a: [AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth()
rL265051: [AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth()
Summary

This change will allow loads with imp-def to be clustered in machine-scheduler pass.
areMemAccessesTriviallyDisjoint() can also handle loads with imp-def.

Diff Detail

Repository
rL LLVM

Event Timeline

junbuml updated this revision to Diff 52261.Mar 31 2016, 12:47 PM
junbuml retitled this revision from to [AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth().
junbuml updated this object.
junbuml added reviewers: mcrosier, t.p.northover, jmolloy.
junbuml added a subscriber: llvm-commits.
Herald added subscribers: mcrosier, rengolin, aemerson. · View Herald TranscriptMar 31 2016, 12:47 PM
t.p.northover edited edge metadata.Mar 31 2016, 12:54 PM

Hi Jun,

I think you should probably be checking MI->getNumExplicitOperands() instead. Other than that it looks like a reasonable change to me.

Tim.

junbuml updated this revision to Diff 52271.Mar 31 2016, 1:17 PM
junbuml edited edge metadata.

Use getNumExplicitOperands() as Tim suggested.
Thanks Tim for the review.

t.p.northover accepted this revision.Mar 31 2016, 1:17 PM
t.p.northover edited edge metadata.

Looks good to me. Thanks for updating!

Tim.

This revision is now accepted and ready to land.Mar 31 2016, 1:17 PM
Closed by commit rL265051: [AArch64] Allow loads with imp-def to be handled in getMemOpBaseRegImmOfsWidth() (authored by junbuml). · Explain WhyMar 31 2016, 1:59 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AArch64/
2 lines
test/
CodeGen/
AArch64/
2 lines
MIR/
AArch64/
35 lines

Diff 52282

llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp

Show First 20 Lines • Show All 1,398 Lines • ▼ Show 20 Linesbool AArch64InstrInfo::getMemOpBaseRegImmOfs(
}; };
} }
bool AArch64InstrInfo::getMemOpBaseRegImmOfsWidth( bool AArch64InstrInfo::getMemOpBaseRegImmOfsWidth(
MachineInstr *LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width, MachineInstr *LdSt, unsigned &BaseReg, int64_t &Offset, unsigned &Width,
const TargetRegisterInfo *TRI) const { const TargetRegisterInfo *TRI) const {
assert(LdSt->mayLoadOrStore() && "Expected a memory operation."); assert(LdSt->mayLoadOrStore() && "Expected a memory operation.");
// Handle only loads/stores with base register followed by immediate offset. // Handle only loads/stores with base register followed by immediate offset.
if (LdSt->getNumOperands() != 3) if (LdSt->getNumExplicitOperands() != 3)
return false; return false;
if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm()) if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm())
return false; return false;
// Offset is calculated as the immediate operand multiplied by the scaling factor. // Offset is calculated as the immediate operand multiplied by the scaling factor.
// Unscaled instructions have scaling factor set to 1. // Unscaled instructions have scaling factor set to 1.
unsigned Scale = 0; unsigned Scale = 0;
switch (LdSt->getOpcode()) { switch (LdSt->getOpcode()) {
▲ Show 20 Lines • Show All 1,836 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AArch64/arm64-abi-varargs.ll

Show First 20 Lines • Show All 119 Lines • ▼ Show 20 Lines; CHECK: ldr {{q[0-9]+}}, [x[[ADDR]]]
%1 = va_arg i8** %args, <4 x i32> %1 = va_arg i8** %args, <4 x i32>
store <4 x i32> %1, <4 x i32>* %vv, align 16 store <4 x i32> %1, <4 x i32>* %vv, align 16
ret void ret void
} }
define void @bar(i32 %x, <4 x i32> %y) nounwind { define void @bar(i32 %x, <4 x i32> %y) nounwind {
entry: entry:
; CHECK-LABEL: bar: ; CHECK-LABEL: bar:
; CHECK: str {{q[0-9]+}}, [sp, #16] ; CHECK: stp {{q[0-9]+}}, {{q[0-9]+}}, [sp, #16]
; CHECK: str {{x[0-9]+}}, [sp] ; CHECK: str {{x[0-9]+}}, [sp]
%x.addr = alloca i32, align 4 %x.addr = alloca i32, align 4
%y.addr = alloca <4 x i32>, align 16 %y.addr = alloca <4 x i32>, align 16
store i32 %x, i32* %x.addr, align 4 store i32 %x, i32* %x.addr, align 4
store <4 x i32> %y, <4 x i32>* %y.addr, align 16 store <4 x i32> %y, <4 x i32>* %y.addr, align 16
%0 = load i32, i32* %x.addr, align 4 %0 = load i32, i32* %x.addr, align 4
%1 = load <4 x i32>, <4 x i32>* %y.addr, align 16 %1 = load <4 x i32>, <4 x i32>* %y.addr, align 16
call void (i8*, ...) @foo(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %0, <4 x i32> %1) call void (i8*, ...) @foo(i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i32 %0, <4 x i32> %1)
▲ Show 20 Lines • Show All 55 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/MIR/AArch64/machine-scheduler.mir

# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-scheduler -verify-machineinstrs -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i64 @load_imp-def(i64* nocapture %P, i32 %v) {
entry:
%0 = bitcast i64* %P to i32*
%1 = load i32, i32* %0
%conv = zext i32 %1 to i64
%arrayidx19 = getelementptr inbounds i64, i64* %P, i64 1
%arrayidx1 = bitcast i64* %arrayidx19 to i32*
store i32 %v, i32* %arrayidx1
%2 = load i64, i64* %arrayidx19
%and = and i64 %2, 4294967295
%add = add nuw nsw i64 %and, %conv
ret i64 %add
}
...
---
# CHECK-LABEL: name: load_imp-def
# CHECK: bb.0.entry:
# CHECK: LDRWui %x0, 0
# CHECK: LDRWui %x0, 1
# CHECK: STRWui %w1, %x0, 2
name: load_imp-def
isSSA: true
body: |
bb.0.entry:
liveins: %w1, %x0
%w8 = LDRWui %x0, 1, implicit-def %x8 :: (load 4 from %ir.0)
STRWui killed %w1, %x0, 2 :: (store 4 into %ir.arrayidx1)
%w9 = LDRWui killed %x0, 0, implicit-def %x9 :: (load 4 from %ir.arrayidx19, align 8)
%x0 = ADDXrr killed %x9, killed %x8
RET_ReallyLR implicit %x0
...