Set MaxAtomicInlineWidth properly for i386, i486, and x86-64 cpus without cmpxchg16b.

[jyknight]

Summary

Also, remove all the manual definition of
GCC_HAVE_SYNC_COMPARE_AND_SWAP_* macros. Instead, define it based on
MaxAtomicInlineWidth, just like the GCC_ATOMIC_*_LOCK_FREE macros.

Previously, the __GCC_HAVE_SYNC_COMPARE_AND_SWAP_* defines had been
computed separately, and *were* being set appropriately for older x86
targets, while MaxAtomicInlineWidth was not.

(Note the one FIXME comment: __GCC_ATOMIC_LLONG_LOCK_FREE is (still) set
improperly for i586, due to checking alignment where it ought not to.)

Test changes of note:

A few test invocations of clang -cc1 needed to have a "-target-cpu i686"
argument added -- the Driver would do so automatically based on the
"i686" in the triple, but in the tests cases cc1 invocations, it was
missing.

Some of the OpenMP tests needed a "-target-cpu core2" added: they were
assuming that cmpxchg16b was available, even though it's not in the base
x86_64 architecture.

An ARM test was asserting that V8M doesn't have
__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1. This was wrong: V8M *does* support
atomic operations.

[jyknight]

Ping.

[rsmith]

lib/Basic/Targets.cpp

4083

... where by 64, you mean 8, right? :)

test/CodeGen/atomic-ops.c

1

Why do you need a -target-cpu i686 in addition to the i686 triple?

test/Preprocessor/arm-target-features.c

87–103

Maybe drop the #define on these lines for consistency with the surrounding tests?

test/Preprocessor/init.c

3327

Can you add a MIPSN32BE-NOT: for the 16 byte form? Likewise for the below cases.

[jyknight]

test/CodeGen/atomic-ops.c

1

The Driver code is what's responsible for parsing the default target cpu out of the triple. So if you invoke CC1 yourself, and don't pass -target-cpu, it treats i686-* triples as still targeting i386.

test/Preprocessor/arm-target-features.c

87–103

Did the inverse (cleaned up the surrounding lines) in r265187.

test/Preprocessor/init.c

3327

Done here and everywhere.

[jyknight]

Review tweaks.

[majnemer]

lib/Basic/Targets.cpp

2565–2577

Might be easier to read if we go from increasing strength:

void setAtomic() {
  MaxAtomicInlineWidth = 0;
  if (CPU >= CK_i486)
    MaxAtomicInlineWidth = 32;
  if (CPU >= CK_i586)
    MaxAtomicInlineWidth = 64;
  if (getTriple().getArch() == llvm::Triple::x86_64) {
    MaxAtomicInlineWidth = 64;
    if (HasCX16)
      MaxAtomicInlineWidth = 128;
  }
}

Either works for me.

[dsanders]

test/Preprocessor/init.c

3327

I've just noticed that we only check the '__GCC_*' macros for the 64-bit ABI's (N32/N64). I'm not sure why the 32-bit (O32) checks are missing.

The O32 cases are the same as N32 except that __GCC_ATOMIC_LLONG_LOCK_FREE is 1 and __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 is not defined.
Could you add:

// MIPS32LE: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
// MIPS32LE: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
// MIPS32LE: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
// MIPS32LE: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
// MIPS32LE: #define __GCC_ATOMIC_INT_LOCK_FREE 2
// MIPS32LE: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
// MIPS32LE: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
// MIPS32LE: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
// MIPS32LE: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
// MIPS32LE: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
// MIPS32LE: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
// MIPS32LE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
// MIPS32LE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
// MIPS32LE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
// MIPS32LE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
// MIPS32LE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16

and the same for the MIPS32BE case?

[jyknight]

review fixes

[jyknight]

Done and done.

[jyknight]

ping.

[jyknight]

ping again.

lib/Basic/Targets.cpp

if (HasVSX)
     Builder.defineMacro("__VSX__");
   if (HasP8Vector)
     Builder.defineMacro("__POWER8_VECTOR__");
   if (HasP8Crypto)
     Builder.defineMacro("__CRYPTO__");
   if (HasHTM)
     Builder.defineMacro("__HTM__");
 
-  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
-  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
-  Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
-  if (PointerWidth == 64)
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
-
   // FIXME: The following are not yet generated here by Clang, but are
   //        generated by GCC:
   //
   //   _SOFT_FLOAT_
   //   __RECIP_PRECISION__
   //   __APPLE_ALTIVEC__
   //   __RECIP__
   //   __RECIPF__
if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX)
       return "avx";
     if (getTriple().getArch() == llvm::Triple::x86 &&
              MMX3DNowLevel == NoMMX3DNow)
       return "no-mmx";
     return "";
   }
   bool setCPU(const std::string &Name) override {
     CPU = getCPUKind(Name);
+    setAtomic();
 
     // Perform any per-CPU checks necessary to determine if this CPU is
     // acceptable.
     // FIXME: This results in terrible diagnostics. Clang just says the CPU is
     // invalid without explaining *why*.
     switch (CPU) {
     case CK_Generic:
       // No processor selected!
public:
 
   CallingConv getDefaultCallingConv(CallingConvMethodType MT) const override {
     return MT == CCMT_Member ? CC_X86ThisCall : CC_C;
   }
 
   bool hasSjLjLowering() const override {
     return true;
   }
+  void setAtomic() {
+    MaxAtomicInlineWidth = 0;
+    if (CPU >= CK_i486)
+      MaxAtomicInlineWidth = 32;
+    if (CPU >= CK_i586)
+      MaxAtomicInlineWidth = 64;
+    if (getTriple().getArch() == llvm::Triple::x86_64) {
+      MaxAtomicInlineWidth = 64;
+      if (HasCX16)
+        MaxAtomicInlineWidth = 128;
+    }
+  }
 };
 
 bool X86TargetInfo::setFPMath(StringRef Name) {
   if (Name == "387") {
     FPMath = FP_387;
     return true;
   }
   if (Name == "sse") {
     FPMath = FP_SSE;
     return true;
if ((FPMath == FP_SSE && SSELevel < SSE1) ||
       (FPMath == FP_387 && SSELevel >= SSE1)) {
     Diags.Report(diag::err_target_unsupported_fpmath) <<
       (FPMath == FP_SSE ? "sse" : "387");
     return false;
   }
 
   SimdDefaultAlign =
       hasFeature("avx512f") ? 512 : hasFeature("avx") ? 256 : 128;
+
+  setAtomic();
+
   return true;
 }
 
 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro
 /// definitions for this particular subtarget.
 void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
                                      MacroBuilder &Builder) const {
   // Target identification.
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
   if (HasXSAVEOPT)
     Builder.defineMacro("__XSAVEOPT__");
   if (HasXSAVEC)
     Builder.defineMacro("__XSAVEC__");
   if (HasXSAVES)
     Builder.defineMacro("__XSAVES__");
   if (HasPKU)
     Builder.defineMacro("__PKU__");
-  if (HasCX16)
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
 
   // Each case falls through to the previous one here.
   switch (SSELevel) {
   case AVX512F:
     Builder.defineMacro("__AVX512F__");
   case AVX2:
     Builder.defineMacro("__AVX2__");
   case AVX:
case AMD3DNowAthlon:
     Builder.defineMacro("__3dNOW_A__");
   case AMD3DNow:
     Builder.defineMacro("__3dNOW__");
   case MMX:
     Builder.defineMacro("__MMX__");
   case NoMMX3DNow:
     break;
   }
-
-  if (CPU >= CK_i486) {
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
-  }
-  if (CPU >= CK_i586)
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
 }
 
 bool X86TargetInfo::hasFeature(StringRef Feature) const {
   return llvm::StringSwitch<bool>(Feature)
       .Case("aes", HasAES)
       .Case("avx", SSELevel >= AVX)
       .Case("avx2", SSELevel >= AVX2)
       .Case("avx512f", SSELevel >= AVX512F)
X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
     IntPtrType = SignedInt;
     RegParmMax = 3;
 
     // Use fpret for all types.
     RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) |
                              (1 << TargetInfo::Double) |
                              (1 << TargetInfo::LongDouble));
 
-    // x86-32 has atomics up to 8 bytes
-    // FIXME: Check that we actually have cmpxchg8b before setting
-    // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.)
-    MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64;
+    // x86-32 has atomics up to 8 bytes, depending on CPU.
+    MaxAtomicPromoteWidth = 64;
+    setAtomic();
   }
   BuiltinVaListKind getBuiltinVaListKind() const override {
     return TargetInfo::CharPtrBuiltinVaList;
   }
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {
     if (RegNo == 0) return 0;
     if (RegNo == 1) return 2;
X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) {
     RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble);
 
     // Use fp2ret for _Complex long double.
     ComplexLongDoubleUsesFP2Ret = true;
 
     // Make __builtin_ms_va_list available.
     HasBuiltinMSVaList = true;
 
-    // x86-64 has atomics up to 16 bytes.
+    // x86-64 has atomics up to 16 bytes, when the HasCX16 target
+    // feature is enabled, 8 otherwise.
     MaxAtomicPromoteWidth = 128;
-    MaxAtomicInlineWidth = 128;
+    setAtomic();
   }
   BuiltinVaListKind getBuiltinVaListKind() const override {
     return TargetInfo::X86_64ABIBuiltinVaList;
   }
 
   int getEHDataRegisterNumber(unsigned RegNo) const override {
     if (RegNo == 0) return 0;
     if (RegNo == 1) return 1;
class ARMTargetInfo : public TargetInfo {
 
   void setAtomic() {
     // when triple does not specify a sub arch,
     // then we are not using inline atomics
     bool ShouldUseInlineAtomic =
                    (ArchISA == llvm::ARM::IK_ARM   && ArchVersion >= 6) ||
                    (ArchISA == llvm::ARM::IK_THUMB && ArchVersion >= 7);
     // Cortex M does not support 8 byte atomics, while general Thumb2 does.
+    if (!ShouldUseInlineAtomic)
+      MaxAtomicInlineWidth = 0;
     if (ArchProfile == llvm::ARM::PK_M) {
       MaxAtomicPromoteWidth = 32;
       if (ShouldUseInlineAtomic)
         MaxAtomicInlineWidth = 32;
     }
     else {
       MaxAtomicPromoteWidth = 64;
       if (ShouldUseInlineAtomic)
void getTargetDefines(const LangOptions &Opts,
     }
 
     Builder.defineMacro("__ARM_SIZEOF_WCHAR_T",
                         Opts.ShortWChar ? "2" : "4");
 
     Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM",
                         Opts.ShortEnums ? "1" : "4");
 
-    if (ArchVersion >= 6 && CPUAttr != "6M" && CPUAttr != "8M_BASE") {
-      Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
-      Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
-      Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
-      Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
-    }
-
     // ACLE 6.4.7 DSP instructions
     if (DSP) {
       Builder.defineMacro("__ARM_FEATURE_DSP", "1");
     }
 
     // ACLE 6.4.8 Saturation instructions
     bool SAT = false;
     if ((ArchVersion == 6 && CPUProfile != "M") || ArchVersion > 6 ) {
if (Crypto)
       Builder.defineMacro("__ARM_FEATURE_CRYPTO", "1");
 
     if (Unaligned)
       Builder.defineMacro("__ARM_FEATURE_UNALIGNED", "1");
 
     if (V8_1A)
       Builder.defineMacro("__ARM_FEATURE_QRDMX", "1");
 
-    // All of the __sync_(bool|val)_compare_and_swap_(1|2|4|8) builtins work.
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
   }
 
   ArrayRef<Builtin::Info> getTargetBuiltins() const override {
     return llvm::makeArrayRef(BuiltinInfo,
                        clang::AArch64::LastTSBuiltin - Builtin::FirstTSBuiltin);
   }
 
   bool hasFeature(StringRef Feature) const override {
public:
   }
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override {
     Builder.defineMacro("__s390__");
     Builder.defineMacro("__s390x__");
     Builder.defineMacro("__zarch__");
     Builder.defineMacro("__LONG_DOUBLE_128__");
 
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
-
     if (HasTransactionalExecution)
       Builder.defineMacro("__HTM__");
     if (Opts.ZVector)
       Builder.defineMacro("__VEC__", "10301");
   }
   ArrayRef<Builtin::Info> getTargetBuiltins() const override {
     return llvm::makeArrayRef(BuiltinInfo,
                          clang::SystemZ::LastTSBuiltin-Builtin::FirstTSBuiltin);
if (HasMSA)
       Builder.defineMacro("__mips_msa", Twine(1));
 
     Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0)));
     Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth()));
     Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth()));
 
     Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\"");
     Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper());
-
-    // These shouldn't be defined for MIPS-I but there's no need to check
-    // for that since MIPS-I isn't supported.
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
   }
 
   ArrayRef<Builtin::Info> getTargetBuiltins() const override {
     return llvm::makeArrayRef(BuiltinInfo,
                           clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin);
   }
   bool hasFeature(StringRef Feature) const override {
     return llvm::StringSwitch<bool>(Feature)

 class Mips32TargetInfoBase : public MipsTargetInfoBase {
 public:
   Mips32TargetInfoBase(const llvm::Triple &Triple)
       : MipsTargetInfoBase(Triple, "o32", "mips32r2") {
     SizeType = UnsignedInt;
     PtrDiffType = SignedInt;
     Int64Type = SignedLongLong;
     IntMaxType = Int64Type;
+    // Atomics aren't supported for MIPS-I, but there's no need to
+    // check for that since MIPS-I isn't supported.
     MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32;
   }
   bool setABI(const std::string &Name) override {
     if (Name == "o32" || Name == "eabi") {
       ABI = Name;
       return true;
     }
     return false;
void getTargetDefines(const LangOptions &Opts,
     }
     else if (ABI == "n64") {
       Builder.defineMacro("__mips_n64");
       Builder.defineMacro("_ABI64", "3");
       Builder.defineMacro("_MIPS_SIM", "_ABI64");
     }
     else
       llvm_unreachable("Invalid ABI for Mips64.");
-
-    Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
   }
   ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
     static const TargetInfo::GCCRegAlias GCCRegAliases[] = {
       { { "at" },  "$1" },
       { { "v0" },  "$2" },
       { { "v1" },  "$3" },
       { { "a0" },  "$4" },
       { { "a1" },  "$5" },

lib/Frontend/InitPreprocessor.cpp

if (!LangOpts.MSVCCompat) {
     else
       Builder.defineMacro("__GNUC_STDC_INLINE__");
 
     // The value written by __atomic_test_and_set.
     // FIXME: This is target-dependent.
     Builder.defineMacro("__GCC_ATOMIC_TEST_AND_SET_TRUEVAL", "1");
 
     // Used by libc++ and libstdc++ to implement ATOMIC_<foo>_LOCK_FREE.
-    unsigned InlineWidthBits = TI.getMaxAtomicInlineWidth();
-#define DEFINE_LOCK_FREE_MACRO(TYPE, Type) \
-    Builder.defineMacro("__GCC_ATOMIC_" #TYPE "_LOCK_FREE", \
-                        getLockFreeValue(TI.get##Type##Width(), \
-                                         TI.get##Type##Align(), \
-                                         InlineWidthBits));
+    unsigned AtomicInlineWidthBits = TI.getMaxAtomicInlineWidth();
+#define DEFINE_LOCK_FREE_MACRO(TYPE, Type)                                     \
+  Builder.defineMacro("__GCC_ATOMIC_" #TYPE "_LOCK_FREE",                      \
+                      getLockFreeValue(TI.get##Type##Width(),                  \
+                                       TI.get##Type##Align(),                  \
+                                       AtomicInlineWidthBits));
     DEFINE_LOCK_FREE_MACRO(BOOL, Bool);
     DEFINE_LOCK_FREE_MACRO(CHAR, Char);
     DEFINE_LOCK_FREE_MACRO(CHAR16_T, Char16);
     DEFINE_LOCK_FREE_MACRO(CHAR32_T, Char32);
     DEFINE_LOCK_FREE_MACRO(WCHAR_T, WChar);
     DEFINE_LOCK_FREE_MACRO(SHORT, Short);
     DEFINE_LOCK_FREE_MACRO(INT, Int);
     DEFINE_LOCK_FREE_MACRO(LONG, Long);
     DEFINE_LOCK_FREE_MACRO(LLONG, LongLong);
     Builder.defineMacro("__GCC_ATOMIC_POINTER_LOCK_FREE",
                         getLockFreeValue(TI.getPointerWidth(0),
                                          TI.getPointerAlign(0),
-                                         InlineWidthBits));
+                                         AtomicInlineWidthBits));
 #undef DEFINE_LOCK_FREE_MACRO
+
+    if (AtomicInlineWidthBits >= 8)
+      Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
+    if (AtomicInlineWidthBits >= 16)
+      Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
+    if (AtomicInlineWidthBits >= 32)
+      Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
+    if (AtomicInlineWidthBits >= 64)
+      Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
+    if (AtomicInlineWidthBits >= 128)
+      Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16");
   }
 
   if (LangOpts.NoInlineDefine)
     Builder.defineMacro("__NO_INLINE__");
 
   if (unsigned PICLevel = LangOpts.PICLevel) {
     Builder.defineMacro("__PIC__", Twine(PICLevel));
     Builder.defineMacro("__pic__", Twine(PICLevel));

test/CodeGen/atomic-ops.c

-// RUN: %clang_cc1 %s -emit-llvm -o - -ffreestanding -ffake-address-space-map -triple=i686-apple-darwin9 | FileCheck %s
+// RUN: %clang_cc1 %s -emit-llvm -o - -ffreestanding -ffake-address-space-map -triple=i686-apple-darwin9 -target-cpu i686 | FileCheck %s
 // REQUIRES: x86-registered-target
 
 // Also test serialization of atomic operations here, to avoid duplicating the
 // test.
-// RUN: %clang_cc1 %s -emit-pch -o %t -ffreestanding -ffake-address-space-map -triple=i686-apple-darwin9
-// RUN: %clang_cc1 %s -include-pch %t -ffreestanding -ffake-address-space-map -triple=i686-apple-darwin9 -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 %s -emit-pch -o %t -ffreestanding -ffake-address-space-map -triple=i686-apple-darwin9 -target-cpu i686
+// RUN: %clang_cc1 %s -include-pch %t -ffreestanding -ffake-address-space-map -triple=i686-apple-darwin9 -target-cpu i686 -emit-llvm -o - | FileCheck %s
 #ifndef ALREADY_INCLUDED
 #define ALREADY_INCLUDED
 
 #include <stdatomic.h>
 
 // Basic IRGen tests for __c11_atomic_* and GNU __atomic_*
 
 int fi1(_Atomic(int) *i) {

test/CodeGen/ms-volatile.c

-// RUN: %clang_cc1 -triple i386-pc-win32 -fms-extensions -emit-llvm -fms-volatile -o - < %s | FileCheck %s
+// RUN: %clang_cc1 -triple i686-pc-win32 -target-cpu i686 -fms-extensions -emit-llvm -fms-volatile -o - < %s | FileCheck %s
 struct foo {
   volatile int x;
 };
 struct bar {
   int x;
 };
 typedef _Complex float __declspec(align(8)) baz;
 

test/CodeGenCXX/atomicinit.cpp

-// RUN: %clang_cc1 %s -emit-llvm -O1 -o - -triple=i686-apple-darwin9 -std=c++11 | FileCheck %s
+// RUN: %clang_cc1 %s -emit-llvm -O1 -o - -triple=i686-apple-darwin9 -target-cpu i686 -std=c++11 | FileCheck %s
 
 // CHECK-DAG: @PR22043 = global i32 0, align 4
 typedef _Atomic(int) AtomicInt;
 AtomicInt PR22043 = AtomicInt();
 
 // CHECK-DAG: @_ZN7PR180978constant1aE = global { i16, i8 } { i16 1, i8 6 }, align 4
 // CHECK-DAG: @_ZN7PR180978constant1bE = global { i16, i8 } { i16 2, i8 6 }, align 4
 // CHECK-DAG: @_ZN7PR180978constant1cE = global { i16, i8 } { i16 3, i8 6 }, align 4

test/OpenMP/atomic_capture_codegen.cpp

-// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s
-// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s
+// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s
 // expected-no-diagnostics
 // REQUIRES: x86-registered-target
 #ifndef HEADER
 #define HEADER
 
 _Bool bv, bx;
 char cv, cx;
 unsigned char ucv, ucx;

test/OpenMP/atomic_read_codegen.c

-// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s
-// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s
+// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s
 // expected-no-diagnostics
 // REQUIRES: x86-registered-target
 #ifndef HEADER
 #define HEADER
 
 _Bool bv, bx;
 char cv, cx;
 unsigned char ucv, ucx;

test/OpenMP/atomic_update_codegen.cpp

-// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s
-// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s
+// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s
 // expected-no-diagnostics
 // REQUIRES: x86-registered-target
 #ifndef HEADER
 #define HEADER
 
 _Bool bv, bx;
 char cv, cx;
 unsigned char ucv, ucx;

test/OpenMP/atomic_write_codegen.c

-// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s
-// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -emit-pch -o %t %s
-// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s
+// RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -target-cpu core2 -fopenmp -x c -emit-llvm %s -o - | FileCheck %s
+// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -emit-pch -o %t %s
+// RUN: %clang_cc1 -fopenmp -x c -triple x86_64-apple-darwin10 -target-cpu core2 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s
 // expected-no-diagnostics
 // REQUIRES: x86-registered-target
 #ifndef HEADER
 #define HEADER
 
 _Bool bv, bx;
 char cv, cx;
 unsigned char ucv, ucx;

test/Preprocessor/arm-target-features.c

 // V8M_BASELINE: #define __ARM_ARCH_8M_BASE__ 1
 // V8M_BASELINE: #define __ARM_ARCH_EXT_IDIV__ 1
 // V8M_BASELINE-NOT: __ARM_ARCH_ISA_ARM
 // V8M_BASELINE: #define __ARM_ARCH_ISA_THUMB 1
 // V8M_BASELINE: #define __ARM_ARCH_PROFILE 'M'
 // V8M_BASELINE-NOT: __ARM_FEATURE_CRC32
 // V8M_BASELINE-NOT: __ARM_FEATURE_DSP
 // V8M_BASELINE-NOT: __ARM_FP 0x{{.*}}
-// V8M_BASELINE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1
+// V8M_BASELINE: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// V8M_BASELINE: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// V8M_BASELINE: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
+// V8M_BASELINE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
+// V8M_BASELINE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
+// V8M_BASELINE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
+// V8M_BASELINE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+// V8M_BASELINE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 
 // RUN: %clang -target armv8m.main-none-linux-gnu -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=V8M_MAINLINE %s
 // V8M_MAINLINE: #define __ARM_ARCH 8
 // V8M_MAINLINE: #define __ARM_ARCH_8M_MAIN__ 1
 // V8M_MAINLINE: #define __ARM_ARCH_EXT_IDIV__ 1
 // V8M_MAINLINE-NOT: __ARM_ARCH_ISA_ARM
 // V8M_MAINLINE: #define __ARM_ARCH_ISA_THUMB 2
 // V8M_MAINLINE: #define __ARM_ARCH_PROFILE 'M'
 // V8M_MAINLINE-NOT: __ARM_FEATURE_CRC32
 // V8M_MAINLINE-NOT: __ARM_FEATURE_DSP
 // V8M_MAINLINE: #define __ARM_FP 0xE
+// V8M_MAINLINE: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// V8M_MAINLINE: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// V8M_MAINLINE: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// V8M_MAINLINE: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// V8M_MAINLINE: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// V8M_MAINLINE: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// V8M_MAINLINE: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// V8M_MAINLINE: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// V8M_MAINLINE: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// V8M_MAINLINE: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// V8M_MAINLINE: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
 // V8M_MAINLINE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
+// V8M_MAINLINE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
+// V8M_MAINLINE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
+// V8M_MAINLINE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+// V8M_MAINLINE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 
 // RUN: %clang -target arm-none-linux-gnu -march=armv8-m.main+dsp -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=V8M_MAINLINE_DSP %s
 // V8M_MAINLINE_DSP: #define __ARM_ARCH 8
 // V8M_MAINLINE_DSP: #define __ARM_ARCH_8M_MAIN__ 1
 // V8M_MAINLINE_DSP: #define __ARM_ARCH_EXT_IDIV__ 1
 // V8M_MAINLINE_DSP-NOT: __ARM_ARCH_ISA_ARM
 // V8M_MAINLINE_DSP: #define __ARM_ARCH_ISA_THUMB 2
 // V8M_MAINLINE_DSP: #define __ARM_ARCH_PROFILE 'M'
 // V8M_MAINLINE_DSP-NOT: __ARM_FEATURE_CRC32
 // V8M_MAINLINE_DSP: #define __ARM_FEATURE_DSP 1
 // V8M_MAINLINE_DSP: #define __ARM_FP 0xE
+// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// V8M_MAINLINE_DSP: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
 // V8M_MAINLINE_DSP: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
+// V8M_MAINLINE_DSP: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
+// V8M_MAINLINE_DSP: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
+// V8M_MAINLINE_DSP-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+// V8M_MAINLINE_DSP-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 
 // RUN: %clang -target arm-none-linux-gnu -x c -E -dM %s -o - | FileCheck -match-full-lines --check-prefix=CHECK-DEFS %s
 // CHECK-DEFS:#define __ARM_PCS 1
 // CHECK-DEFS:#define __ARM_SIZEOF_MINIMAL_ENUM 4
 // CHECK-DEFS:#define __ARM_SIZEOF_WCHAR_T 4
 
 // RUN: %clang -target arm-none-linux-gnu -fno-math-errno -fno-signed-zeros\
 // RUN:        -fno-trapping-math -fassociative-math -freciprocal-math\

test/Preprocessor/init.c

 // MIPS32BE:#define __FLT_MANT_DIG__ 24
 // MIPS32BE:#define __FLT_MAX_10_EXP__ 38
 // MIPS32BE:#define __FLT_MAX_EXP__ 128
 // MIPS32BE:#define __FLT_MAX__ 3.40282347e+38F
 // MIPS32BE:#define __FLT_MIN_10_EXP__ (-37)
 // MIPS32BE:#define __FLT_MIN_EXP__ (-125)
 // MIPS32BE:#define __FLT_MIN__ 1.17549435e-38F
 // MIPS32BE:#define __FLT_RADIX__ 2
+// MIPS32BE:#define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// MIPS32BE:#define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// MIPS32BE:#define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// MIPS32BE:#define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// MIPS32BE:#define __GCC_ATOMIC_INT_LOCK_FREE 2
+// MIPS32BE:#define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// MIPS32BE:#define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// MIPS32BE:#define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// MIPS32BE:#define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// MIPS32BE:#define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// MIPS32BE:#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
+// MIPS32BE:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
+// MIPS32BE:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
+// MIPS32BE:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
+// MIPS32BE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+// MIPS32BE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 // MIPS32BE:#define __INT16_C_SUFFIX__
 // MIPS32BE:#define __INT16_FMTd__ "hd"
 // MIPS32BE:#define __INT16_FMTi__ "hi"
 // MIPS32BE:#define __INT16_MAX__ 32767
 // MIPS32BE:#define __INT16_TYPE__ short
 // MIPS32BE:#define __INT32_C_SUFFIX__
 // MIPS32BE:#define __INT32_FMTd__ "d"
 // MIPS32BE:#define __INT32_FMTi__ "i"

 // MIPS32EL:#define __FLT_MANT_DIG__ 24
 // MIPS32EL:#define __FLT_MAX_10_EXP__ 38
 // MIPS32EL:#define __FLT_MAX_EXP__ 128
 // MIPS32EL:#define __FLT_MAX__ 3.40282347e+38F
 // MIPS32EL:#define __FLT_MIN_10_EXP__ (-37)
 // MIPS32EL:#define __FLT_MIN_EXP__ (-125)
 // MIPS32EL:#define __FLT_MIN__ 1.17549435e-38F
 // MIPS32EL:#define __FLT_RADIX__ 2
+// MIPS32EL:#define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// MIPS32EL:#define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// MIPS32EL:#define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// MIPS32EL:#define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// MIPS32EL:#define __GCC_ATOMIC_INT_LOCK_FREE 2
+// MIPS32EL:#define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// MIPS32EL:#define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// MIPS32EL:#define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// MIPS32EL:#define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// MIPS32EL:#define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// MIPS32EL:#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
+// MIPS32EL:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
+// MIPS32EL:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
+// MIPS32EL:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
+// MIPS32EL-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+// MIPS32EL-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 // MIPS32EL:#define __INT16_C_SUFFIX__
 // MIPS32EL:#define __INT16_FMTd__ "hd"
 // MIPS32EL:#define __INT16_FMTi__ "hi"
 // MIPS32EL:#define __INT16_MAX__ 32767
 // MIPS32EL:#define __INT16_TYPE__ short
 // MIPS32EL:#define __INT32_C_SUFFIX__
 // MIPS32EL:#define __INT32_FMTd__ "d"
 // MIPS32EL:#define __INT32_FMTi__ "i"

 // MIPSN32BE: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
 // MIPSN32BE: #define __GCC_ATOMIC_INT_LOCK_FREE 2
 // MIPSN32BE: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2
 // MIPSN32BE: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
 // MIPSN32BE: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
 // MIPSN32BE: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
 // MIPSN32BE: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
 // MIPSN32BE: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
+// MIPSN32BE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
+// MIPSN32BE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
+// MIPSN32BE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
+// MIPSN32BE: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
+// MIPSN32BE-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 // MIPSN32BE: #define __GNUC_MINOR__ 2
 // MIPSN32BE: #define __GNUC_PATCHLEVEL__ 1
 // MIPSN32BE: #define __GNUC_STDC_INLINE__ 1
 // MIPSN32BE: #define __GNUC__ 4
 // MIPSN32BE: #define __GXX_ABI_VERSION 1002
 // MIPSN32BE: #define __ILP32__ 1
 // MIPSN32BE: #define __INT16_C_SUFFIX__
 // MIPSN32BE: #define __INT16_FMTd__ "hd"

 // MIPSN32EL: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
 // MIPSN32EL: #define __GCC_ATOMIC_INT_LOCK_FREE 2
 // MIPSN32EL: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2
 // MIPSN32EL: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
 // MIPSN32EL: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
 // MIPSN32EL: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
 // MIPSN32EL: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
 // MIPSN32EL: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
+// MIPSN32EL: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
+// MIPSN32EL: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
+// MIPSN32EL: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
+// MIPSN32EL: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
+// MIPSN32EL-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 // MIPSN32EL: #define __GNUC_MINOR__ 2
 // MIPSN32EL: #define __GNUC_PATCHLEVEL__ 1
 // MIPSN32EL: #define __GNUC_STDC_INLINE__ 1
 // MIPSN32EL: #define __GNUC__ 4
 // MIPSN32EL: #define __GXX_ABI_VERSION 1002
 // MIPSN32EL: #define __ILP32__ 1
 // MIPSN32EL: #define __INT16_C_SUFFIX__
 // MIPSN32EL: #define __INT16_FMTd__ "hd"

 // X86_64-CLOUDABI:#define __GCC_ATOMIC_CHAR_LOCK_FREE 2
 // X86_64-CLOUDABI:#define __GCC_ATOMIC_INT_LOCK_FREE 2
 // X86_64-CLOUDABI:#define __GCC_ATOMIC_LLONG_LOCK_FREE 2
 // X86_64-CLOUDABI:#define __GCC_ATOMIC_LONG_LOCK_FREE 2
 // X86_64-CLOUDABI:#define __GCC_ATOMIC_POINTER_LOCK_FREE 2
 // X86_64-CLOUDABI:#define __GCC_ATOMIC_SHORT_LOCK_FREE 2
 // X86_64-CLOUDABI:#define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
 // X86_64-CLOUDABI:#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
+// X86_64-CLOUDABI:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
+// X86_64-CLOUDABI:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
+// X86_64-CLOUDABI:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
+// X86_64-CLOUDABI:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
+// X86_64-CLOUDABI-NOT:__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 // X86_64-CLOUDABI:#define __GNUC_MINOR__ 2
 // X86_64-CLOUDABI:#define __GNUC_PATCHLEVEL__ 1
 // X86_64-CLOUDABI:#define __GNUC_STDC_INLINE__ 1
 // X86_64-CLOUDABI:#define __GNUC__ 4
 // X86_64-CLOUDABI:#define __GXX_ABI_VERSION 1002
 // X86_64-CLOUDABI:#define __INT16_C_SUFFIX__
 // X86_64-CLOUDABI:#define __INT16_FMTd__ "hd"
 // X86_64-CLOUDABI:#define __INT16_FMTi__ "hi"

 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_CHAR_LOCK_FREE 2
 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_INT_LOCK_FREE 2
 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_LLONG_LOCK_FREE 1
 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_LONG_LOCK_FREE 2
 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_POINTER_LOCK_FREE 2
 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_SHORT_LOCK_FREE 2
 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
 // WEBASSEMBLY32-NEXT:#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
+// WEBASSEMBLY32-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
+// WEBASSEMBLY32-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
+// WEBASSEMBLY32-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
+// WEBASSEMBLY32-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+// WEBASSEMBLY32-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 // WEBASSEMBLY32-NEXT:#define __GNUC_MINOR__ {{.*}}
 // WEBASSEMBLY32-NEXT:#define __GNUC_PATCHLEVEL__ {{.*}}
 // WEBASSEMBLY32-NEXT:#define __GNUC_STDC_INLINE__ 1
 // WEBASSEMBLY32-NEXT:#define __GNUC__ {{.*}}
 // WEBASSEMBLY32-NEXT:#define __GXX_ABI_VERSION 1002
 // WEBASSEMBLY32-NEXT:#define __ILP32__ 1
 // WEBASSEMBLY32-NEXT:#define __INT16_C_SUFFIX__
 // WEBASSEMBLY32-NEXT:#define __INT16_FMTd__ "hd"

 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_CHAR_LOCK_FREE 2
 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_INT_LOCK_FREE 2
 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_LLONG_LOCK_FREE 2
 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_LONG_LOCK_FREE 2
 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_POINTER_LOCK_FREE 2
 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_SHORT_LOCK_FREE 2
 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
 // WEBASSEMBLY64-NEXT:#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
+// WEBASSEMBLY64-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
+// WEBASSEMBLY64-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
+// WEBASSEMBLY64-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
+// WEBASSEMBLY64-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
+// WEBASSEMBLY64-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 // WEBASSEMBLY64-NEXT:#define __GNUC_MINOR__ {{.*}}
 // WEBASSEMBLY64-NEXT:#define __GNUC_PATCHLEVEL__ {{.*}}
 // WEBASSEMBLY64-NEXT:#define __GNUC_STDC_INLINE__ 1
 // WEBASSEMBLY64-NEXT:#define __GNUC__ {{.}}
 // WEBASSEMBLY64-NEXT:#define __GXX_ABI_VERSION 1002
 // WEBASSEMBLY64-NOT:#define __ILP32__
 // WEBASSEMBLY64-NEXT:#define __INT16_C_SUFFIX__
 // WEBASSEMBLY64-NEXT:#define __INT16_FMTd__ "hd"

 // WEBASSEMBLY64-NEXT:#define __wasm64__ 1
 // WEBASSEMBLY64-NEXT:#define __wasm__ 1
 
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple i686-windows-cygnus < /dev/null | FileCheck -match-full-lines -check-prefix CYGWIN-X32 %s
 // CYGWIN-X32: #define __USER_LABEL_PREFIX__ _
 
 // RUN: %clang_cc1 -E -dM -ffreestanding -triple x86_64-windows-cygnus < /dev/null | FileCheck -match-full-lines -check-prefix CYGWIN-X64 %s
 // CYGWIN-X64: #define __USER_LABEL_PREFIX__
-

test/Preprocessor/predefined-arch-macros.c

 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_GCC_ATOMICS
 // RUN: %clang -mcpu=pwr8 -E -dM %s -o - 2>&1 \
 // RUN:     -target powerpc64-unknown-unknown \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_GCC_ATOMICS
 // RUN: %clang -E -dM %s -o - 2>&1 \
 // RUN:     -target powerpc64le-unknown-linux \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_PPC_GCC_ATOMICS
 //
+// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2
+// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// CHECK_PPC_GCC_ATOMICS: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
 // CHECK_PPC_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
 // CHECK_PPC_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
 // CHECK_PPC_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
 // CHECK_PPC_GCC_ATOMICS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
+// CHECK_PPC_GCC_ATOMICS-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 //
 // End PPC/GCC/Linux tests ------------------
 
 // Begin Sparc/GCC/Linux tests ----------------
 //
 // RUN: %clang -E -dM %s -o - 2>&1 \
 // RUN:     -target sparc-unknown-linux \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_SPARC

 // CHECK_SPARCV9: #define __sparcv9__ 1
 
 // Begin SystemZ/GCC/Linux tests ----------------
 //
 // RUN: %clang -march=z10 -E -dM %s -o - 2>&1 \
 // RUN:     -target s390x-unknown-linux \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_Z10
 //
+// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2
+// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// CHECK_SYSTEMZ_Z10: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
 // CHECK_SYSTEMZ_Z10: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
 // CHECK_SYSTEMZ_Z10: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
 // CHECK_SYSTEMZ_Z10: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
 // CHECK_SYSTEMZ_Z10: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
+// CHECK_SYSTEMZ_Z10-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 // CHECK_SYSTEMZ_Z10: #define __LONG_DOUBLE_128__ 1
 // CHECK_SYSTEMZ_Z10: #define __s390__ 1
 // CHECK_SYSTEMZ_Z10: #define __s390x__ 1
 // CHECK_SYSTEMZ_Z10: #define __zarch__ 1
 //
 // RUN: %clang -march=zEC12 -E -dM %s -o - 2>&1 \
 // RUN:     -target s390x-unknown-linux \
 // RUN:   | FileCheck -match-full-lines %s -check-prefix=CHECK_SYSTEMZ_ZEC12
 //
+// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2
+// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// CHECK_SYSTEMZ_ZEC12: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
 // CHECK_SYSTEMZ_ZEC12: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
 // CHECK_SYSTEMZ_ZEC12: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
 // CHECK_SYSTEMZ_ZEC12: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
 // CHECK_SYSTEMZ_ZEC12: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
+// CHECK_SYSTEMZ_ZEC12-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 // CHECK_SYSTEMZ_ZEC12: #define __HTM__ 1
 // CHECK_SYSTEMZ_ZEC12: #define __LONG_DOUBLE_128__ 1
 // CHECK_SYSTEMZ_ZEC12: #define __s390__ 1
 // CHECK_SYSTEMZ_ZEC12: #define __s390x__ 1
 // CHECK_SYSTEMZ_ZEC12: #define __zarch__ 1
 //
 // RUN: %clang -mhtm -E -dM %s -o - 2>&1 \
 // RUN:     -target s390x-unknown-linux \

test/Preprocessor/predefined-macros.c

 //
 // RUN: %clang_cc1 %s -E -dM -o - \
 // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-FINITE-MATH-FLAG-UNDEFINED
 // CHECK-FINITE-MATH-FLAG-UNDEFINED: #define __FINITE_MATH_ONLY__ 0
 //
 // RUN: %clang_cc1 %s -E -dM -o - -triple i686 -target-cpu i386 \
 // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_I386
 // CHECK-SYNC_CAS_I386-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP
+// CHECK-SYNC_CAS_I386-NOT: __GCC_ATOMIC_{{.*}}_LOCK_FREE 2
 //
 // RUN: %clang_cc1 %s -E -dM -o - -triple i686 -target-cpu i486 \
 // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_I486
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// CHECK-SYNC_CAS_I486: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
 // CHECK-SYNC_CAS_I486: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
 // CHECK-SYNC_CAS_I486: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
 // CHECK-SYNC_CAS_I486: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
 // CHECK-SYNC_CAS_I486-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
+// CHECK-SYNC_CAS_I486-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 //
+
+// FIXME: The value of LLONG_LOCK_FREE on i586 is wrong: clang is
+// using the alignment of "long long" (only 32bit for a 64bit value)
+// to disqualify it from being lock free. But the semantics of this
+// define are supposed to tell you if "_Atomic long long" is lock free
+// -- and it is.
+
 // RUN: %clang_cc1 %s -E -dM -o - -triple i686 -target-cpu i586 \
 // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_I586
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// CHECK-SYNC_CAS_I586: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
 // CHECK-SYNC_CAS_I586: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
 // CHECK-SYNC_CAS_I586: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
 // CHECK-SYNC_CAS_I586: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
 // CHECK-SYNC_CAS_I586: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
+// CHECK-SYNC_CAS_I586-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 //
 // RUN: %clang_cc1 %s -E -dM -o - -triple armv6 -target-cpu arm1136j-s \
 // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_ARM
+// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// CHECK-SYNC_CAS_ARM: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
 // CHECK-SYNC_CAS_ARM: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
 // CHECK-SYNC_CAS_ARM: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
 // CHECK-SYNC_CAS_ARM: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
 // CHECK-SYNC_CAS_ARM: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
+// CHECK-SYNC_CAS_ARM-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 //
 // RUN: %clang_cc1 %s -E -dM -o - -triple armv7 -target-cpu cortex-a8 \
 // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_ARMv7
+// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// CHECK-SYNC_CAS_ARMV7: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
 // CHECK-SYNC_CAS_ARMv7: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
 // CHECK-SYNC_CAS_ARMv7: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
 // CHECK-SYNC_CAS_ARMv7: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
 // CHECK-SYNC_CAS_ARMv7: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
+// CHECK-SYNC_CAS_ARMv7-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
 //
-// RUN: %clang_cc1 %s -E -dM -o - -triple armv6 -target-cpu cortex-m0 \
+// RUN: %clang_cc1 %s -E -dM -o - -triple thumbv6m-- -target-cpu cortex-m0 \
 // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_ARMv6
 // CHECK-SYNC_CAS_ARMv6-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP
+// CHECK-SYNC_CAS_ARMv6-NOT: __GCC_ATOMIC_{{.*}}_LOCK_FREE 2
 //
 // RUN: %clang_cc1 %s -E -dM -o - -triple mips -target-cpu mips2 \
 // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_MIPS \
 // RUN:         --check-prefix=CHECK-SYNC_CAS_MIPS32
 // RUN: %clang_cc1 %s -E -dM -o - -triple mips64 -target-cpu mips3 \
 // RUN:   | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_MIPS \
 // RUN:         --check-prefix=CHECK-SYNC_CAS_MIPS64
+// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_BOOL_LOCK_FREE 2
+// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_CHAR16_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_CHAR32_T_LOCK_FREE 2
+// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_CHAR_LOCK_FREE 2
+// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_INT_LOCK_FREE 2
+// CHECK-SYNC_CAS_MIPS32: #define __GCC_ATOMIC_LLONG_LOCK_FREE 1
+// CHECK-SYNC_CAS_MIPS64: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2
+// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_LONG_LOCK_FREE 2
+// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_POINTER_LOCK_FREE 2
+// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_SHORT_LOCK_FREE 2
+// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1
+// CHECK-SYNC_CAS_MIPS: #define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2
 // CHECK-SYNC_CAS_MIPS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1
 // CHECK-SYNC_CAS_MIPS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1
 // CHECK-SYNC_CAS_MIPS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1
 // CHECK-SYNC_CAS_MIPS32-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8
 // CHECK-SYNC_CAS_MIPS64: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_8 1
+// CHECK-SYNC_CAS_MIPS-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16

test/Preprocessor/x86_target_features.c

 // RUN: %clang -target i386-unknown-unknown -march=atom -mtbm -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=TBM %s
 
 // TBM: #define __TBM__ 1
 
 // RUN: %clang -target i386-unknown-unknown -march=bdver2 -mno-tbm -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOTBM %s
 
 // NOTBM-NOT: #define __TBM__ 1
 
-// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mcx16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MCX16 %s
+// RUN: %clang -target i386-unknown-unknown -march=pentiumpro -mcx16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MCX16-386 %s
 
+// MCX16-386-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16
+
+// RUN: %clang -target x86_64-unknown-unknown -mcx16 -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=MCX16 %s
+
+// MCX16: #define __GCC_ATOMIC_LLONG_LOCK_FREE 2
 // MCX16: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1
 
 // RUN: %clang -target i386-unknown-unknown -march=atom -mprfchw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=PRFCHW %s
 
 // PRFCHW: #define __PRFCHW__ 1
 
 // RUN: %clang -target i386-unknown-unknown -march=btver2 -mno-prfchw -x c -E -dM -o - %s | FileCheck -match-full-lines --check-prefix=NOPRFCHW %s
 

test/Sema/atomic-ops.c

-// RUN: %clang_cc1 %s -verify -ffreestanding -fsyntax-only -triple=i686-linux-gnu -std=c11
+// RUN: %clang_cc1 %s -verify -ffreestanding -fsyntax-only -triple=i686-linux-gnu -target-cpu i686 -std=c11
 
 // Basic parsing/Sema tests for __c11_atomic_*
 
 #include <stdatomic.h>
 
 struct S { char c[3]; };
 
 _Static_assert(__GCC_ATOMIC_BOOL_LOCK_FREE == 2, "");
void memory_checks(_Atomic(int) *Ap, int *p, int val) {
 
   (void)__atomic_compare_exchange_n(p, p, val, 0, memory_order_relaxed, memory_order_relaxed);
   (void)__atomic_compare_exchange_n(p, p, val, 0, memory_order_acquire, memory_order_relaxed);
   (void)__atomic_compare_exchange_n(p, p, val, 0, memory_order_consume, memory_order_relaxed);
   (void)__atomic_compare_exchange_n(p, p, val, 0, memory_order_release, memory_order_relaxed);
   (void)__atomic_compare_exchange_n(p, p, val, 0, memory_order_acq_rel, memory_order_relaxed);
   (void)__atomic_compare_exchange_n(p, p, val, 0, memory_order_seq_cst, memory_order_relaxed);
 }
-
-