[Power9] Implement add-pc, multiply-add, modulo, extend-sign-shift, random number, set bool, and dfp test significance

[cycheng]

Summary

This patch implement the following instructions:

• addpcis subpcis
• maddhd maddhdu maddld
• modsw moduw modsd modud
• darn
• extswsli extswsli.
• setb
• dtstsfi dtstsfiq

Total 15 instructions

[nemanjai]

lib/Target/PowerPC/PPCInstr64Bit.td

1276

Please move this definition up to PPCInstrFormats.td since it is used not only in this file, but in PPCInstInfo.td. I realize that everything defined here is available in PPCInstrInfo.td after the include line but nonetheless, I feel that common definitions should go in the common file.

lib/Target/PowerPC/PPCInstrInfo.td

4198

I'm just curious why the decision to provide one extended mnemonic (subpcis) but not the other (lnia).

4208

How does this encode the floating register pair? Actually, I just noticed that you have a comment regarding this in the README. SystemZ has already done something like this (the FP128 and GR128 register classes). Perhaps we should do something along those lines.

This will also help us implement the instructions that are missing from previous versions of the ISA (lq, lfdp, lqarx, et. al.).

[cycheng]

lib/Target/PowerPC/PPCInstrInfo.td

4198

I missed it, thanks : P
That means gcc also forgot to implement it @@

4208

Thanks your guide, I found useful information from SystemZ and Sparc.

I did something like this, passed building, but not as my expectation:

// Paired F8RC
def subreg_l64   : SubRegIndex<64, 0>;
def subreg_h64   : SubRegIndex<64, 64>;

class DQPR<FPR even, FPR odd, string n> : PPCReg<n> {
  let HWEncoding = even.HWEncoding;
  let SubRegs = [even, odd];
  let SubRegIndices = [subreg_l64, subreg_h64];
}

foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] in {
  def DQ#!srl(Index, 1) :
    DQPR<!cast<FPR>("F"#Index), !cast<FPR>("F"#!add(Index, 1)), "f"#Index>;
}

def F8PRC : RegisterClass<"PPC", [f128], 128, (add (sequence "DQ%u",  0, 6),
                                                   (sequence "DQ%u", 15, 7))>;
def PPCRegQFRCAsmOperand : AsmOperandClass {
  let Name = "RegF8PRC"; let PredicateMethod = "isRegNumber";
}
def f8prc : RegisterOperand<F8PRC> {
  let ParserMatchClass = PPCRegQFRCAsmOperand;
}

[nemanjai]

I think we probably want to ensure we emit these instructions only when targeting Power 9 processors. So we should probably have some "Requires" in here for things that will be defined on Power9 and later only. Sure it doesn't matter now, but when we start adding SDAG patterns to these, we will be able to emit them on older processors, won't we?

[cycheng]

Fixed issues pointed out by nemanjai (http://reviews.llvm.org/D17885#369199)

• Implement lnia (extended mnemonic of addpcis)
• Implement floating register pair (but we need to write inline assembly code to test register allocation, later todo)
• Move X_BF3_IM6_RS5 to PPCInstrFormats.td

[cycheng]

Agree, something like Requires<[HasP9]>.

def FeatureP9 : SubtargetFeature<"power9", "HasP9", "true",
                                        "Enable POWER9 instructions",
                                        [FeatureP9Vector, Power9SpecificFeatures]>;

[nemanjai]

I agree that it should be rather general like your suggestion of the power9 feature. However, I really think we shouldn't focus this on the chip that implements the ISA but the ISA version itself. That way, other chips that implement the ISA do not have to pretend they're Power 9 chips. However, I don't feel all that strongly about this so I'd like some of the others to comment on this as well (maybe @hfinkel or @kbarton).

In review for the atomic instructions (http://reviews.llvm.org/D18032) I implemented what I thought might make sense, but in any case, we should come to a consensus.

[amehsan]

@nemanjai If I understand correctly you are saying a better name for P8Vector would have used ISA version instead of P8 in the feature name. Is that correct?

[amehsan]

I am asking because now I think for my implementation of P9 direct move, I may need to change the feature name from P9 to something that includes ISA version.

[nemanjai]

In D17885#372077, @amehsan wrote:

@nemanjai If I understand correctly you are saying a better name for P8Vector would have used ISA version instead of P8 in the feature name. Is that correct?

I don't think we need to change existing names even though I feel that referencing the chip in the feature name can be misleading. But when the feature is simply called "FeatureP9", I think that's a bit misleading if any other chips end up implementing ISA 3.0.
I think for specific subfeatures such as the direct moves, it is OK to continue to use the names we have been using. Then the ISA 3.0 feature (whatever we name it) will imply all of these Power 9 features.

[kbarton]

In D17885#372141, @nemanjai wrote:

In D17885#372077, @amehsan wrote:

@nemanjai If I understand correctly you are saying a better name for P8Vector would have used ISA version instead of P8 in the feature name. Is that correct?

I don't think we need to change existing names even though I feel that referencing the chip in the feature name can be misleading. But when the feature is simply called "FeatureP9", I think that's a bit misleading if any other chips end up implementing ISA 3.0.
I think for specific subfeatures such as the direct moves, it is OK to continue to use the names we have been using. Then the ISA 3.0 feature (whatever we name it) will imply all of these Power 9 features.

I agree with @nemanjai. Please use the ISA3.0 feature, from D18032 to guard these instructions.

[kbarton]

lib/Target/PowerPC/PPCInstr64Bit.td

1299

You can define both the base and the dot versions of a class at once. Look at the definition of Form_11R in PPCInstrInfo.td for an example.

[cycheng]

• Use ISA3.0 feature to guard new 3.0 instructions
• combine XS_RS5_RA5_SH5 and XS_RS5_RA5_SH5o into one single multi-class

[kbarton]

LGTM

[cycheng]

Committed r265505

lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp

if (!IsPPC64) {
         return true;
     }
     return false;
   }
   bool isCondBr() const { return Kind == Expression ||
                                  (Kind == Immediate && isInt<16>(getImm()) &&
                                   (getImm() & 3) == 0); }
   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
+  bool isD8RCRegNumber() const { return Kind == Immediate &&
+                                        isUInt<5>(getImm()) &&
+                                        // required even register id
+                                        !(getImm() & 0x1); }
   bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
   bool isCCRegNumber() const { return (Kind == Expression
                                        && isUInt<3>(getExprCRVal())) ||
                                       (Kind == Immediate
                                        && isUInt<3>(getImm())); }
   bool isCRBitNumber() const { return (Kind == Expression
                                        && isUInt<5>(getExprCRVal())) ||
                                       (Kind == Immediate
void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
   }
 
   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
   }
 
+  void addRegD8RCOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
+  }
+
   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
   }
 
   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
void PPCAsmParser::ProcessInstruction(MCInst &Inst,
   }
   case PPC::MFTB: {
     if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
       assert(Inst.getNumOperands() == 2 && "Expecting two operands");
       Inst.setOpcode(PPC::MFSPR);
     }
     break;
   }
+  // ISA3.0 Instructions:
+  case PPC::SUBPCIS:
+  case PPC::LNIA: {
+    MCInst TmpInst;
+    TmpInst.setOpcode(PPC::ADDPCIS);
+    TmpInst.addOperand(Inst.getOperand(0));
+    if (Opcode == PPC::SUBPCIS)
+      addNegOperand(TmpInst, Inst.getOperand(1), getContext());
+    else
+      TmpInst.addOperand(MCOperand::createImm(0));
+    Inst = TmpInst;
+    break;
+  }
   }
 }
 
 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                            OperandVector &Operands,
                                            MCStreamer &Out, uint64_t &ErrorInfo,
                                            bool MatchingInlineAsm) {
   MCInst Inst;

lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp

 }
 
 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const void *Decoder) {
   return decodeRegisterClass(Inst, RegNo, FRegs);
 }
 
+static DecodeStatus DecodeD8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder) {
+  return decodeRegisterClass(Inst, RegNo, FRegs);
+}
+
 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,
                                             const void *Decoder) {
   return decodeRegisterClass(Inst, RegNo, VRegs);
 }
 
 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
                                             uint64_t Address,

lib/Target/PowerPC/PPCInstr64Bit.td

def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
           (STDX $rS, xoaddr:$dst)>;
 
 // 64-bits atomic loads and stores
 def : Pat<(atomic_load_64 ixaddr:$src), (LD  memrix:$src)>;
 def : Pat<(atomic_load_64 xaddr:$src),  (LDX memrr:$src)>;
 
 def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD  g8rc:$val, memrix:$ptr)>;
 def : Pat<(atomic_store_64 xaddr:$ptr,  i64:$val), (STDX g8rc:$val, memrr:$ptr)>;
+
+let Predicates = [IsISA3_0] in {
+
+// [PO RT RA RB RC XO]
+class VA_RT5_RA5_RB5_RC5<bits<6> xo, string opc, InstrItinClass itin,
+                         list<dag> pattern>
+  : VAForm_1a<xo, (outs g8rc:$rD), (ins g8rc:$rA, g8rc:$rB, g8rc:$rC),
+              !strconcat(opc, " $rD, $rA, $rB, $rC"), itin, pattern>;
+
+// 64-bit Fixed-Point Multiply-Add High-DWord/High-DWord-Unsigned/Low-DWord
+def MADDHD  : VA_RT5_RA5_RB5_RC5<48, "maddhd" , IIC_IntGeneral, []>;
+def MADDHDU : VA_RT5_RA5_RB5_RC5<49, "maddhdu", IIC_IntGeneral, []>;
+def MADDLD  : VA_RT5_RA5_RB5_RC5<51, "maddld ", IIC_IntGeneral, []>;
+
+let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
+// Add PC Immediate Shifted
+def ADDPCIS8 : DX_RD5_IM16<19, 2, (outs g8rc:$rD), (ins s16imm:$IMM),
+                           "addpcis $rD, $IMM", IIC_IntSimple, []>;
+
+// Modulo {Signed/Unsigned}-Word
+def MODSW8 : X_RT5_RA5_RB5<779, "modsw", g8rc, IIC_IntDivW, []>;
+def MODUW8 : X_RT5_RA5_RB5<267, "moduw", g8rc, IIC_IntDivW, []>;
+}
+
+// Modulo {Signed/Unsigned}-DWord
+def MODSD  : X_RT5_RA5_RB5<777, "modsd", g8rc, IIC_IntDivW, []>;
+def MODUD  : X_RT5_RA5_RB5<265, "modud", g8rc, IIC_IntDivW, []>;
+
+// [PO RS RA sh XO sh Rc]
+multiclass XS_RS5_RA5_SH5r<bits<6> opcode, bits<9> xo, string opc,
+                           InstrItinClass itin, list<dag> pattern> {
+  let BaseName = opc in {
+    def NAME : XSForm_1<opcode, xo, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
+                        !strconcat(opc, " $rA, $rS, $SH"), itin, pattern>;
+    let Defs = [CR0] in
+    def o    : XSForm_1<opcode, xo, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
+                        !strconcat(opc, ". $rA, $rS, $SH"), itin, pattern>,
+               isDOT;
+  }
+}
+
+// Deliver A Random Number
+def DARN : X_RD5_L2<31, 755, (outs g8rc:$rD), (ins u2imm:$L), "darn $rD, $L",
+                    IIC_IntGeneral, []>;
+
+// Extend-Sign Word and Shift Left Immediate
+defm EXTSWSLI  : XS_RS5_RA5_SH5r<31, 445, "extswsli" , IIC_IntShift, []>;
+
+// Set Boolean
+def SETB : X_RD5_BFA3<31, 128, (outs g8rc:$rD), (ins u3imm:$BFA),
+                      "setb $rD, $BFA", IIC_IntGeneral, []>;
+
+// DFP Test Significance Immediate [Quad]
+def DTSTSFI  : X_BF3_IM6_RS5<59, 675,
+                             (outs crbitrc:$BF), (ins u6imm:$UIM, f8rc:$FRB),
+                             "dtstsfi $BF, $UIM, $FRB", IIC_FPGeneral, []>;
+def DTSTSFIQ : X_BF3_IM6_RS5<63,  675,
+                             (outs crbitrc:$BF), (ins u6imm:$UIM, d8rc:$FRBp),
+                             "dtstsfiq $BF, $UIM, $FRBp", IIC_FPGeneral, []>;
+} // IsISA3_0

lib/Target/PowerPC/PPCInstrFormats.td

class DQ_RD6_RS5_DQ12<bits<6> opcode, bits<3> xo, dag OOL, dag IOL,
 
   let Inst{6-10}  = XT{4-0};
   let Inst{11-15} = DS_RA{16-12};  // Register #
   let Inst{16-27} = DS_RA{11-0};   // Displacement.
   let Inst{28}    = XT{5};
   let Inst{29-31} = xo;
 }
 
+// DX-Form: [PO RT d1 d0 XO d2]
+class DX_RD5_IM16<bits<6> opcode, bits<5> xo, dag OOL, dag IOL, string asmstr,
+                  InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<5>  RD;
+  bits<16> IMM;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = RD;
+  // IMM = d0 || d1 || d2
+  let Inst{11-15} = IMM{5-1};   // d1
+  let Inst{16-25} = IMM{15-6};  // d0
+  let Inst{26-30} = xo;
+  let Inst{31}    = IMM{0};     // d2
+}
+
 // 1.7.6 X-Form
 class XForm_base_r3xo<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr, 
                       InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<5> RST;
   bits<5> A;
   bits<5> B;
 
class XForm_htm3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
   bit RC = 0;
 
   let Inst{6-8}   = BF;
   let Inst{9-20}  = 0;
   let Inst{21-30} = xo;
   let Inst{31}    = RC;
 }
 
+// [PO RT RA RB XO /]
+class X_RT5_RA5_RB5<bits<10> xo, string opc, RegisterOperand type,
+                    InstrItinClass itin, list<dag> pattern>
+  : XForm_base_r3xo<31, xo, (outs type:$rD), (ins type:$rA, type:$rB),
+                    !strconcat(opc, " $rD, $rA, $rB"), itin, pattern>;
+
 // e.g. [PO VRT XO VRB XO /] or [PO VRT XO VRB XO RO]
 class X_RD5_XO5_RS5<bits<6> opcode, bits<5> xo2, bits<10> xo, dag OOL, dag IOL,
                     string asmstr, InstrItinClass itin, list<dag> pattern>
   : XForm_base_r3xo<opcode, xo, OOL, IOL, asmstr, itin, pattern> {
   let A = xo2;
 }
 
+// [PO RT /// L /// XO /]
+class X_RD5_L2<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<5> RD;
+  bits<2> L;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = RD;
+  let Inst{11-13} = 0;
+  let Inst{14-15} = L;
+  let Inst{16-20} = 0;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
+}
+
+// [PO RT BFA // /// XO /]
+class X_RD5_BFA3<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+                 InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<5> RD;
+  bits<3> BFA;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = RD;
+  let Inst{11-13} = BFA;
+  let Inst{14-20} = 0;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
+}
+
+// [PO BF / UIM FRB XO /] or [PO BF / UIM FRBp XO /]
+class X_BF3_IM6_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+                    string asmstr, InstrItinClass itin, list<dag> pattern>
+  : I<opcode, OOL, IOL, asmstr, itin> {
+  bits<3> BF;
+  bits<6> UIM;
+  bits<5> FRB;
+
+  let Pattern = pattern;
+
+  let Inst{6-8}   = BF;
+  let Inst{9}     = 0;
+  let Inst{10-15} = UIM;
+  let Inst{16-20} = FRB;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
+}
+
 class X_BF3_DCMX7_RS5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
                       string asmstr, InstrItinClass itin, list<dag> pattern>
   : I<opcode, OOL, IOL, asmstr, itin> {
   bits<3> BF;
   bits<7> DCMX;
   bits<5> VB;
 
   let Pattern = pattern;

lib/Target/PowerPC/PPCInstrInfo.td

def f8rc : RegisterOperand<F8RC> {
   let ParserMatchClass = PPCRegF8RCAsmOperand;
 }
 def PPCRegF4RCAsmOperand : AsmOperandClass {
   let Name = "RegF4RC"; let PredicateMethod = "isRegNumber";
 }
 def f4rc : RegisterOperand<F4RC> {
   let ParserMatchClass = PPCRegF4RCAsmOperand;
 }
+def PPCRegD8RCAsmOperand : AsmOperandClass {
+  let Name = "RegD8RC"; let PredicateMethod = "isD8RCRegNumber";
+}
+def d8rc : RegisterOperand<D8RC> {
+  let ParserMatchClass = PPCRegD8RCAsmOperand;
+}
 def PPCRegVRRCAsmOperand : AsmOperandClass {
   let Name = "RegVRRC"; let PredicateMethod = "isRegNumber";
 }
 def vrrc : RegisterOperand<VRRC> {
   let ParserMatchClass = PPCRegVRRCAsmOperand;
 }
 def PPCRegCRBITRCAsmOperand : AsmOperandClass {
   let Name = "RegCRBITRC"; let PredicateMethod = "isCRBitNumber";

 
 // Atomic stores
 def : Pat<(atomic_store_8  iaddr:$ptr, i32:$val), (STB  gprc:$val, memri:$ptr)>;
 def : Pat<(atomic_store_16 iaddr:$ptr, i32:$val), (STH  gprc:$val, memri:$ptr)>;
 def : Pat<(atomic_store_32 iaddr:$ptr, i32:$val), (STW  gprc:$val, memri:$ptr)>;
 def : Pat<(atomic_store_8  xaddr:$ptr, i32:$val), (STBX gprc:$val, memrr:$ptr)>;
 def : Pat<(atomic_store_16 xaddr:$ptr, i32:$val), (STHX gprc:$val, memrr:$ptr)>;
 def : Pat<(atomic_store_32 xaddr:$ptr, i32:$val), (STWX gprc:$val, memrr:$ptr)>;
+
+let Predicates = [IsISA3_0] in {
+
+// Add PC Immediate Shifted
+def ADDPCIS : DX_RD5_IM16<19, 2, (outs gprc:$rD), (ins s16imm:$IMM),
+                          "addpcis $rD, $IMM", IIC_IntSimple, []>;
+// Extended Mnemonics of ADDPCIS
+def SUBPCIS : PPCAsmPseudo<"subpcis $rD, $IMM", (ins gprc:$rD, s16imm:$IMM)>;
+def LNIA    : PPCAsmPseudo<"lnia $rD",          (ins gprc:$rD)>;
+
+// Modulo {Signed/Unsigned}-Word
+def MODSW : X_RT5_RA5_RB5<779, "modsw", gprc, IIC_IntDivW, []>;
+def MODUW : X_RT5_RA5_RB5<267, "moduw", gprc, IIC_IntDivW, []>;
+
+} // IsISA3_0

lib/Target/PowerPC/PPCRegisterInfo.td

 let Namespace = "PPC" in {
 def sub_lt : SubRegIndex<1>;
 def sub_gt : SubRegIndex<1, 1>;
 def sub_eq : SubRegIndex<1, 2>;
 def sub_un : SubRegIndex<1, 3>;
 def sub_32 : SubRegIndex<32>;
 def sub_64 : SubRegIndex<64>;
 def sub_128 : SubRegIndex<128>;
+def subreg_l64 : SubRegIndex<64, 0>;
+def subreg_h64 : SubRegIndex<64, 64>;
 }
 
 
 class PPCReg<string n> : Register<n> {
   let Namespace = "PPC";
 }
 
 // We identify all our registers with a 5-bit ID, for consistency's sake.
class SPR<bits<10> num, string n> : PPCReg<n> {
   let HWEncoding{9-0} = num;
 }
 
 // FPR - One of the 32 64-bit floating-point registers
 class FPR<bits<5> num, string n> : PPCReg<n> {
   let HWEncoding{4-0} = num;
 }
 
+// DPR - One of the 16 128 bit floating-point registers
+// It is composed of FPR_even and FPR_odd
+class DPR<FPR even, FPR odd, string n> : PPCReg<n> {
+  let HWEncoding = even.HWEncoding;
+  let SubRegs = [even, odd];
+  let SubRegIndices = [subreg_l64, subreg_h64];
+}
+
 // QFPR - One of the 32 256-bit floating-point vector registers (used for QPX)
 class QFPR<FPR SubReg, string n> : PPCReg<n> {
   let HWEncoding = SubReg.HWEncoding;
   let SubRegs = [SubReg];
   let SubRegIndices = [sub_64];
 }
 
 // VF - One of the 32 64-bit floating-point subregisters of the vector

 }
 
 // Floating-point registers
 foreach Index = 0-31 in {
   def F#Index : FPR<Index, "f"#Index>,
                 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
 }
 
+// 128-bit Paired Floating-point registers
+foreach Index = 0-15 in {
+  def D#Index :
+    DPR<!cast<FPR>("F"#!shl(Index, 1)),
+        !cast<FPR>("F"#!add(!shl(Index, 1), 1)), "f"#!shl(Index, 1)>;
+}
+
 // Floating-point vector subregisters (for VSX)
 foreach Index = 0-31 in {
   def VF#Index : VF<Index, "vs" # !add(Index, 32)>;
 }
 
 // QPX Floating-point registers
 foreach Index = 0-31 in {
   def QF#Index : QFPR<!cast<FPR>("F"#Index), "q"#Index>,

 // register N is spilled to offset 8 * (32 - N) below the back chain word of the
 // previous stack frame. By allocating non-volatiles in reverse order we make
 // sure that the Floating-point register save area is always as small as
 // possible because there aren't any unused spill slots.
 def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
                                                 (sequence "F%u", 31, 14))>;
 def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
 
+def D8RC : RegisterClass<"PPC", [f128], 128, (add (sequence "D%u",  0, 6),
+                                                  (sequence "D%u", 15, 7))>;
+
 def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32], 128,
                          (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
                              V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
                              V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>;
 
 // VSX register classes (the allocation order mirrors that of the corresponding
 // subregister classes).
 def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,

lib/Target/PowerPC/README_P9.txt

 
 Load Doubleword Monitored (ldmx):
 - Investigate whether there are any uses for this. It seems to be related to
   Garbage Collection so it isn't likely to be all that useful for most
   languages we deal with.
 
 Move to CR from XER Extended (mcrxrx):
 - Is there a use for this in LLVM?
+
+Fixed Point Facility:
+- Add PC Immediate Shifted: addpcis subpcis
+  . Thinking to use it on PC relative addressing mode?
+
+- 64-bit Fixed-Point Multiply-Add Low DWord: maddld
+  . SDAG:
+    (set i64:$rD, (add (mul $rA, $rB), $rC))
+
+- 64-bit Fixed-Point Multiply-Add High-DWord/High-DWord-Unsigned: maddhd maddhdu
+  . Use intrinsic:
+    (set i64:$rD, (int_ppc_maddhd i64:$rA, i64:$rB), i64:$rC))
+    (set i64:$rD, (int_ppc_maddhdu i64:$rA, i64:$rB), i64:$rC))
+
+- Modulo {Signed/Unsigned}-{Word/DWord}: modsw moduw modsd modud
+  . Map modulo signed to llvm srem, modulo unsigned to urem because each pair
+    has same semantics, as follows:
+
+    llvm srem:
+    1. This instruction returns the remainder of a division (where the result is
+       either zero or has the same sign as the dividend, op1)
+    2. Undefined behavior:
+       - <anything> % 0
+       - Overflow: e.g. -2147483648 % -1
+         In this case, the remainder doesn’t actually overflow, but this rule
+         lets srem be implemented using instructions that return both the result
+         of the division and the remainder.
+
+    Modulo Signed:
+    1. remainder = dividend - (quotient × divisor)
+        where
+                    0 ≤ remainder < |divisor|, if the dividend ≥ 0
+           -|divisor| < remainder ≤  0       , if the dividend < 0
+
+    2. Undefined behavior:
+      - <anything> % 0
+      - 0x8000_0000 % -1
+
+  . SDAG:
+    (set i32:$rD, (srem i32:$rA, i32:$rB))  // modsw
+    (set i32:$rD, (urem i32:$rA, i32:$rB))  // moduw
+    (set i64:$rD, (srem i64:$rA, i64:$rB))  // modsd
+    (set i64:$rD, (urem i64:$rA, i64:$rB))  // modud
+
+  . Note:
+    The quotient is not supplied as a result in modulo word (32-bit)
+    instructions
+
+- Deliver A Random Number: darn
+  . Intrinsic?
+    (set i64:$rD, (int_ppc_darn i2:$L))
+
+  . Thinking for using it on c/c++ rand() implementation
+
+- Extend-Sign Word and Shift Left Immediate: extswsli extswsli.
+  . SDAG:
+    (set i64:$rA, shl((sext i32:$rS, i64), i6$SH))
+
+- Set Boolean: setb
+  . Thinking to use it on:
+
+    if (cond)
+      return true;
+    return false;
+
+  . Need Intrinsic?
+    (set i64:rD, (int_ppc_setb i3:$BFA))
+
+- DFP Test Significance Immediate [Quad]: dtstsfi dtstsfiq
+  . Need write inline assembly to test paired floating point register
+    allocation for dtstsfiq
+
+  . Intrinsics:
+    (set i1:$BF, (int_ppc_dtstsfi i6:$UIM, f64:$FRB))
+    (set i1:$BF, (int_ppc_dtstsfiq i6:$UIM, f128:$FRBp))
 No newline at end of file

test/MC/Disassembler/PowerPC/ppc64-encoding.txt

 # CHECK: mcrxrx 7
 0x7f 0x80 0x04 0x80
 
 # CHECK: mtsrin 10, 12
 0x7d 0x40 0x61 0xe4
 
 # CHECK: mfsrin 10, 12
 0x7d 0x40 0x65 0x26
+
+# ISA3.0 Instructions:
+
+# CHECK: addpcis 1, -12345
+0x4c 0x23 0xcf 0xc5
+
+# CHECK: maddhd 30, 27, 7, 2
+0x13 0xdb 0x38 0xb0
+
+# CHECK: maddhdu 15, 12, 1, 3
+0x11 0xec 0x08 0xf1
+
+# CHECK: maddld 13, 10, 6, 4
+0x11 0xaa 0x31 0x33
+
+# CHECK: modsw 2, 3, 4
+0x7c 0x43 0x26 0x16
+
+# CHECK: moduw 3, 7, 5
+0x7c 0x67 0x2a 0x16
+
+# CHECK: modsd 10, 13, 14
+0x7d 0x4d 0x76 0x12
+
+# CHECK: modud 21, 15, 27
+0x7e 0xaf 0xda 0x12
+
+# CHECK: darn 31, 2
+0x7f 0xe2 0x05 0xe6
+
+# CHECK: extswsli 15, 18, 63
+0x7e 0x4f 0xfe 0xf6
+
+# CHECK: extswsli. 11, 27, 31
+0x7f 0x6b 0xfe 0xf5
+
+# CHECK: setb 2, 7
+0x7c 0x5c 0x01 0x00
+
+# CHECK: dtstsfi 7, 63, 1
+0xef 0xbf 0x0d 0x46
+
+# CHECK: dtstsfiq 4, 63, 4
+0xfe 0x3f 0x25 0x46

test/MC/PowerPC/ppc64-encoding-ext.s

 # CHECK-LE: stdcix 21, 5, 7                  # encoding: [0xea,0x3f,0xa5,0x7e]
             stdcix 21, 5, 7
 
 # Processor-Specific Instructions
 # CHECK-BE: attn                             # encoding: [0x00,0x00,0x02,0x00]
 # CHECK-LE: attn                             # encoding: [0x00,0x02,0x00,0x00]
             attn
 
+# ISA3.0 Instructions:
+# Extended Mnemonics of ADDPCIS
+# CHECK-BE: addpcis 1, -12345                  # encoding: [0x4c,0x23,0xcf,0xc5]
+# CHECK-LE: addpcis 1, -12345                  # encoding: [0xc5,0xcf,0x23,0x4c]
+            subpcis 1, 12345
+# CHECK-BE: addpcis 12, 0                      # encoding: [0x4d,0x80,0x00,0x04]
+# CHECK-LE: addpcis 12, 0                      # encoding: [0x04,0x00,0x80,0x4d]
+            lnia 12

test/MC/PowerPC/ppc64-encoding.s

# CHECK-LE: mfsr    10, 12                    # encoding: [0xa6,0x04,0x4c,0x7d]
             mfsr    %r10,12
 
 # CHECK-BE: mtsrin  10, 12                    # encoding: [0x7d,0x40,0x61,0xe4]
 # CHECK-LE: mtsrin  10, 12                    # encoding: [0xe4,0x61,0x40,0x7d]
             mtsrin  %r10,%r12
 # CHECK-BE: mfsrin  10, 12                    # encoding: [0x7d,0x40,0x65,0x26]
 # CHECK-LE: mfsrin  10, 12                    # encoding: [0x26,0x65,0x40,0x7d]
             mfsrin  %r10,%r12
+
+# ISA3.0 Instructions:
+
+# Add PC Immediate Shifted
+# CHECK-BE: addpcis 1, -12345                  # encoding: [0x4c,0x23,0xcf,0xc5]
+# CHECK-LE: addpcis 1, -12345                  # encoding: [0xc5,0xcf,0x23,0x4c]
+            addpcis 1, -12345
+
+# 64-bit Fixed-Point Multiply-Add High-DWord/High-DWord-Unsigned/Low-DWord
+# CHECK-BE: maddhd 30, 27, 7, 2                # encoding: [0x13,0xdb,0x38,0xb0]
+# CHECK-LE: maddhd 30, 27, 7, 2                # encoding: [0xb0,0x38,0xdb,0x13]
+            maddhd 30, 27, 7, 2
+# CHECK-BE: maddhdu 15, 12, 1, 3               # encoding: [0x11,0xec,0x08,0xf1]
+# CHECK-LE: maddhdu 15, 12, 1, 3               # encoding: [0xf1,0x08,0xec,0x11]
+            maddhdu 15, 12, 1, 3
+# CHECK-BE: maddld 13, 10, 6, 4                # encoding: [0x11,0xaa,0x31,0x33]
+# CHECK-LE: maddld 13, 10, 6, 4                # encoding: [0x33,0x31,0xaa,0x11]
+            maddld 13, 10, 6, 4
+
+# Modulo {Signed/Unsigned}-{Word/DWord}
+# CHECK-BE: modsw 2, 3, 4                      # encoding: [0x7c,0x43,0x26,0x16]
+# CHECK-LE: modsw 2, 3, 4                      # encoding: [0x16,0x26,0x43,0x7c]
+            modsw 2, 3, 4
+# CHECK-BE: moduw 3, 7, 5                      # encoding: [0x7c,0x67,0x2a,0x16]
+# CHECK-LE: moduw 3, 7, 5                      # encoding: [0x16,0x2a,0x67,0x7c]
+            moduw 3, 7, 5
+# CHECK-BE: modsd 10, 13, 14                   # encoding: [0x7d,0x4d,0x76,0x12]
+# CHECK-LE: modsd 10, 13, 14                   # encoding: [0x12,0x76,0x4d,0x7d]
+            modsd 10, 13, 14
+# CHECK-BE: modud 21, 15, 27                   # encoding: [0x7e,0xaf,0xda,0x12]
+# CHECK-LE: modud 21, 15, 27                   # encoding: [0x12,0xda,0xaf,0x7e]
+            modud 21, 15, 27
+
+# Deliver A Random Number
+# CHECK-BE: darn 31, 2                         # encoding: [0x7f,0xe2,0x05,0xe6]
+# CHECK-LE: darn 31, 2                         # encoding: [0xe6,0x05,0xe2,0x7f]
+            darn 31, 2
+
+# Extend-Sign Word and Shift Left Immediate
+# CHECK-BE: extswsli 15, 18, 63                # encoding: [0x7e,0x4f,0xfe,0xf6]
+# CHECK-LE: extswsli 15, 18, 63                # encoding: [0xf6,0xfe,0x4f,0x7e]
+            extswsli 15, 18, 63
+# CHECK-BE: extswsli. 11, 27, 31               # encoding: [0x7f,0x6b,0xfe,0xf5]
+# CHECK-LE: extswsli. 11, 27, 31               # encoding: [0xf5,0xfe,0x6b,0x7f]
+            extswsli. 11, 27, 31
+
+# Set Boolean
+# CHECK-BE: setb 2, 7                          # encoding: [0x7c,0x5c,0x01,0x00]
+# CHECK-LE: setb 2, 7                          # encoding: [0x00,0x01,0x5c,0x7c]
+            setb 2, 7
+
+# DFP Test Significance Immediate [Quad]
+# CHECK-BE: dtstsfi 7, 63, 1                   # encoding: [0xef,0xbf,0x0d,0x46]
+# CHECK-LE: dtstsfi 7, 63, 1                   # encoding: [0x46,0x0d,0xbf,0xef]
+            dtstsfi 7, 63, 1
+# CHECK-BE: dtstsfiq 4, 63, 4                  # encoding: [0xfe,0x3f,0x25,0x46]
+# CHECK-LE: dtstsfiq 4, 63, 4                  # encoding: [0x46,0x25,0x3f,0xfe]
+            dtstsfiq 4, 63, 4