[AArch64] Allocate the modified and used regs once per function.

[mcrosier]

Summary

Rather than once per load/store in the function. NFC, but hopefully this has a non-trivial improvement on compile-time.

Chad

[junbuml]

Looks good to me.

[mgrang]

lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

1020

Can you please update these comments to reflect that the bitfield trackers are being reset here?

[mcrosier]

In D16787#341146, @junbuml wrote:

Looks good to me.

[mcrosier]

Committed r259510.

lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

1020

Sure, Mandeep. I think the call to reset makes it pretty clear we're resetting the vector at this point, so I didn't add a comment here. However, I did add an additional comment where the vectors are being resized.

lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

   const TargetRegisterInfo *TRI;
   const AArch64Subtarget *Subtarget;
 
+  // Track which registers have been modified and used.
+  BitVector ModifiedRegs, UsedRegs;
+
   // Scan the instructions looking for a load/store that can be combined
   // with the current instruction into a load/store pair.
   // Return the matching instruction if one is found, else MBB->end().

 
   // Track which registers have been modified and used between the first insn
   // and the second insn.
-  BitVector ModifiedRegs, UsedRegs;
-  ModifiedRegs.resize(TRI->getNumRegs());
-  UsedRegs.resize(TRI->getNumRegs());
+  ModifiedRegs.reset();
+  UsedRegs.reset();
 
   for (unsigned Count = 0; MBBI != E && Count < Limit;) {
     --MBBI;

 
   // Track which registers have been modified and used between the first insn
   // (inclusive) and the second insn.
-  BitVector ModifiedRegs, UsedRegs;
-  ModifiedRegs.resize(TRI->getNumRegs());
-  UsedRegs.resize(TRI->getNumRegs());
+  ModifiedRegs.reset();
+  UsedRegs.reset();
 
   // Remember any instructions that read/write memory between FirstMI and MI.
   SmallVector<MachineInstr *, 4> MemInsns;

 
   // Track which registers have been modified and used between the first insn
   // (inclusive) and the second insn.
-  BitVector ModifiedRegs, UsedRegs;
-  ModifiedRegs.resize(TRI->getNumRegs());
-  UsedRegs.resize(TRI->getNumRegs());
+  ModifiedRegs.reset();
+  UsedRegs.reset();
   ++MBBI;
   for (; MBBI != E; ++MBBI) {
     MachineInstr *MI = MBBI;

 
   // Track which registers have been modified and used between the first insn
   // (inclusive) and the second insn.
-  BitVector ModifiedRegs, UsedRegs;
-  ModifiedRegs.resize(TRI->getNumRegs());
-  UsedRegs.resize(TRI->getNumRegs());
+  ModifiedRegs.reset();
+  UsedRegs.reset();
   --MBBI;
   for (; MBBI != B; --MBBI) {
     MachineInstr *MI = MBBI;

   TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo());
   TRI = Subtarget->getRegisterInfo();
 
+  // Resize the modified and used register bitfield trackers.
+  ModifiedRegs.resize(TRI->getNumRegs());
+  UsedRegs.resize(TRI->getNumRegs());
+
   bool Modified = false;
   bool enableNarrowLdOpt = enableNarrowLdMerge(Fn);
   for (auto &MBB : Fn)