AMDGPU: Make workgroup id z imply y is enabled

[arsenm]

Summary

According to the HSA ABI document, this is also the case with
the workgroup id as well as the workitem id.

[• tstellarAMD]

Does this actually fix anything? I think it may be a typo in the document.

[arsenm]

In D16698#339637, @tstellarAMD wrote:

Does this actually fix anything? I think it may be a typo in the document.

I don't think so, I'm just trying to match the documentation. It's probably a weird situation nobody uses to use z and not y

[• tstellarAMD]

I think we should get confirmation from someone that this is actually a requirement. I suspect a typo in the document.

lib/Target/AMDGPU/SIMachineFunctionInfo.cpp

SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
   const MachineFrameInfo *FrameInfo = MF.getFrameInfo();
 
   if (getShaderType() == ShaderType::COMPUTE)
     KernargSegmentPtr = true;
 
   if (F->hasFnAttribute("amdgpu-work-group-id-y"))
     WorkGroupIDY = true;
 
-  if (F->hasFnAttribute("amdgpu-work-group-id-z"))
+  if (F->hasFnAttribute("amdgpu-work-group-id-z")) {
+    // Z implies Y is enabled.
+    WorkGroupIDY = true;
     WorkGroupIDZ = true;
+  }
 
   if (F->hasFnAttribute("amdgpu-work-item-id-y"))
     WorkItemIDY = true;
 
   if (F->hasFnAttribute("amdgpu-work-item-id-z"))
     WorkItemIDZ = true;
 
   bool MaySpill = ST.isVGPRSpillingEnabled(this);

test/CodeGen/AMDGPU/work-item-intrinsics.ll

entry:
   %0 = call i32 @llvm.r600.read.tgid.y() #0
   store i32 %0, i32 addrspace(1)* %out
   ret void
 }
 
 ; FUNC-LABEL: {{^}}tgid_z:
 ; HSA: compute_pgm_rsrc2_user_sgpr = 6
 ; HSA: compute_pgm_rsrc2_tgid_x_en = 1
-; HSA: compute_pgm_rsrc2_tgid_y_en = 0
+; HSA: compute_pgm_rsrc2_tgid_y_en = 1
 ; HSA: compute_pgm_rsrc2_tgid_z_en = 1
 ; HSA: compute_pgm_rsrc2_tg_size_en = 0
 ; HSA: compute_pgm_rsrc2_tidig_comp_cnt = 0
 ; HSA: enable_sgpr_private_segment_buffer = 1
 ; HSA: enable_sgpr_dispatch_ptr = 0
 ; HSA: enable_sgpr_queue_ptr = 0
 ; HSA: enable_sgpr_kernarg_segment_ptr = 1
 ; HSA: enable_sgpr_dispatch_id = 0
 ; HSA: enable_sgpr_flat_scratch_init = 0
 ; HSA: enable_sgpr_private_segment_size = 0
 ; HSA: enable_sgpr_grid_workgroup_count_x = 0
 ; HSA: enable_sgpr_grid_workgroup_count_y = 0
 ; HSA: enable_sgpr_grid_workgroup_count_z = 0
 
-; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s3{{$}}
-; HSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s7{{$}}
+; GCN-NOHSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s4{{$}}
+; HSA: v_mov_b32_e32 [[VVAL:v[0-9]+]], s8{{$}}
 ; GCN-NOHSA: buffer_store_dword [[VVAL]]
 ; HSA: flat_store_dword [[VVAL]]
 
 ; HSA: COMPUTE_PGM_RSRC2:USER_SGPR: 6
 ; GCN-NOHSA: COMPUTE_PGM_RSRC2:USER_SGPR: 2
 ; GCN: COMPUTE_PGM_RSRC2:TGID_X_EN: 1
-; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 0
+; GCN: COMPUTE_PGM_RSRC2:TGID_Y_EN: 1
 ; GCN: COMPUTE_PGM_RSRC2:TGID_Z_EN: 1
 ; GCN: COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: 0
 define void @tgid_z(i32 addrspace(1)* %out) {
 entry:
   %0 = call i32 @llvm.r600.read.tgid.z() #0
   store i32 %0, i32 addrspace(1)* %out
   ret void
 }