[ARMv8-M] [5/9] Add B.W and CBZ instructions to ARMv8-M Baseline

[bsmith]

Summary

This patch forms part of the ARMv8-M Baseline/Mainline support, allowing the use of wide branch and CBZ instructions in ARMv8-M Baseline.

[bsmith]

Rebase onto changes done in D15275.

[bsmith]

Rebase patch against latest trunk changes.

[t.p.northover]

One minor comment on the logic here (though I don't think it would ever make a difference in practice):

lib/Target/ARM/ARMSubtarget.cpp

237

Isn't the logic here really "!isThumb() || hasV8MBaselineOps()"? The Feature check part of isThumb1Only seems to be redundant since any T2-capable processor will have 8M baseline.

Or am I misunderstanding?

[bsmith]

Remove redundancy in condition check !isThumb1Only() && hasV8MBaselineOps(), all Thumb-2 targets will have hasV8MBaselineOps() set, so the first condition can simply be !isThumb().

[t.p.northover]

Thanks Bradley, this looks fine now.

Tim.

[bsmith]

Thanks, committed as r257881.

lib/Target/ARM/ARMConstantIslandPass.cpp

if (BRChange && ++NoBRIters > 30)
       report_fatal_error("Branch Fix Up pass failed to converge!");
     DEBUG(dumpBBs());
 
     if (!CPChange && !BRChange)
       break;
     MadeChange = true;
   }
 
-  // Shrink 32-bit Thumb2 branch, load, and store instructions.
+  // Shrink 32-bit Thumb2 load and store instructions.
   if (isThumb2 && !STI->prefers32BitThumb())
     MadeChange |= optimizeThumb2Instructions();
 
+  // Shrink 32-bit branch instructions.
+  if (isThumb && STI->hasV8MBaselineOps())
+    MadeChange |= optimizeThumb2Branches();
+
+  // Optimize jump tables using TBB / TBH.
+  if (isThumb2)
+    MadeChange |= optimizeThumb2JumpTables();
+
   // After a while, this might be made debug-only, but it is not expensive.
   verify();
 
   // If LR has been forced spilled and no far jump (i.e. BL) has been issued,
   // undo the spill / restore of LR if possible.
   if (isThumb && !HasFarJump && AFI->isLRSpilledForFarJump())
     MadeChange |= undoLRSpillRestore();
 
if (isCPEntryInRange(U.MI, UserOffset, U.CPEMI, MaxOffs, false, true)) {
       MachineBasicBlock *MBB = U.MI->getParent();
       BBInfo[MBB->getNumber()].Size -= 2;
       adjustBBOffsetsAfter(MBB);
       ++NumT2CPShrunk;
       MadeChange = true;
     }
   }
 
-  MadeChange |= optimizeThumb2Branches();
-  MadeChange |= optimizeThumb2JumpTables();
   return MadeChange;
 }
 
 bool ARMConstantIslands::optimizeThumb2Branches() {
   bool MadeChange = false;
 
   // The order in which branches appear in ImmBranches is approximately their
   // order within the function body. By visiting later branches first, we reduce

lib/Target/ARM/ARMInstrThumb2.td

def t2LDMIA_RET: t2PseudoExpand<(outs GPR:$wb), (ins GPR:$Rn, pred:$p,
                               4, IIC_iLoad_mBr, [],
             (t2LDMIA_UPD GPR:$wb, GPR:$Rn, pred:$p, reglist:$regs)>,
                          RegConstraint<"$Rn = $wb">;
 
 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
 let isPredicable = 1 in
 def t2B   : T2I<(outs), (ins uncondbrtarget:$target), IIC_Br,
                  "b", ".w\t$target",
-                 [(br bb:$target)]>, Sched<[WriteBr]> {
+                 [(br bb:$target)]>, Sched<[WriteBr]>,
+                 Requires<[IsThumb, HasV8MBaseline]> {
   let Inst{31-27} = 0b11110;
   let Inst{15-14} = 0b10;
   let Inst{12} = 1;
 
   bits<24> target;
   let Inst{26} = target{23};
   let Inst{13} = target{22};
   let Inst{11} = target{21};
def t2BXJ : T2I<(outs), (ins GPRnopc:$func), NoItinerary, "bxj", "\t$func", []>,
   let Inst{15-0} = 0b1000111100000000;
 }
 
 // Compare and branch on zero / non-zero
 let isBranch = 1, isTerminator = 1 in {
   def tCBZ  : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
                   "cbz\t$Rn, $target", []>,
               T1Misc<{0,0,?,1,?,?,?}>,
-              Requires<[IsThumb2]>, Sched<[WriteBr]> {
+              Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> {
     // A8.6.27
     bits<6> target;
     bits<3> Rn;
     let Inst{9}   = target{5};
     let Inst{7-3} = target{4-0};
     let Inst{2-0} = Rn;
   }
 
   def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
                   "cbnz\t$Rn, $target", []>,
               T1Misc<{1,0,?,1,?,?,?}>,
-              Requires<[IsThumb2]>, Sched<[WriteBr]> {
+              Requires<[IsThumb, HasV8MBaseline]>, Sched<[WriteBr]> {
     // A8.6.27
     bits<6> target;
     bits<3> Rn;
     let Inst{9}   = target{5};
     let Inst{7-3} = target{4-0};
     let Inst{2-0} = Rn;
   }
 }

lib/Target/ARM/ARMSubtarget.cpp

void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   // generate the tail call here and turn it back into CALL/RET in
   // emitEpilogue if LR is used.
 
   // Thumb1 PIC calls to external symbols use BX, so they can be tail calls,
   // but we need to make sure there are enough registers; the only valid
   // registers are the 4 used for parameters.  We don't currently do this
   // case.
 
-  SupportsTailCall = !isThumb1Only();
+  SupportsTailCall = !isThumb() || hasV8MBaselineOps();
 
   if (isTargetMachO() && isTargetIOS() && getTargetTriple().isOSVersionLT(5, 0))
     SupportsTailCall = false;
 
   switch (IT) {
   case DefaultIT:
     RestrictIT = hasV8Ops();
     break;

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

bool hasV6MOps() const {
     return getSTI().getFeatureBits()[ARM::HasV6MOps];
   }
   bool hasV7Ops() const {
     return getSTI().getFeatureBits()[ARM::HasV7Ops];
   }
   bool hasV8Ops() const {
     return getSTI().getFeatureBits()[ARM::HasV8Ops];
   }
+  bool hasV8MBaseline() const {
+    return getSTI().getFeatureBits()[ARM::HasV8MBaselineOps];
+  }
   bool hasARM() const {
     return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
   }
   bool hasDSP() const {
     return getSTI().getFeatureBits()[ARM::FeatureDSP];
   }
   bool hasD16() const {
     return getSTI().getFeatureBits()[ARM::FeatureD16];
if(inITBlock()) {
     }
   }
 
   // now decide on encoding size based on branch target range
   switch(Inst.getOpcode()) {
     // classify tB as either t2B or t1B based on range of immediate operand
     case ARM::tB: {
       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
-      if (!op.isSignedOffset<11, 1>() && isThumbTwo())
+      if (!op.isSignedOffset<11, 1>() && isThumb() && hasV8MBaseline())
         Inst.setOpcode(ARM::t2B);
       break;
     }
     // classify tBcc as either t2Bcc or t1Bcc based on range of immediate operand
     case ARM::tBcc: {
       ARMOperand &op = static_cast<ARMOperand &>(*Operands[ImmOp]);
-      if (!op.isSignedOffset<8, 1>() && isThumbTwo())
+      if (!op.isSignedOffset<8, 1>() && isThumb() && hasV8MBaseline())
         Inst.setOpcode(ARM::t2Bcc);
       break;
     }
   }
   ((ARMOperand &)*Operands[ImmOp]).addImmOperands(Inst, 1);
   ((ARMOperand &)*Operands[CondOp]).addCondCodeOperands(Inst, 2);
 }
 

lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp

case MCAF_Code32:
     setIsThumb(false);
     break;
   }
 }
 } // end anonymous namespace
 
 unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op) const {
   bool HasThumb2 = STI->getFeatureBits()[ARM::FeatureThumb2];
+  bool HasV8MBaselineOps = STI->getFeatureBits()[ARM::HasV8MBaselineOps];
 
   switch (Op) {
   default:
     return Op;
   case ARM::tBcc:
     return HasThumb2 ? (unsigned)ARM::t2Bcc : Op;
   case ARM::tLDRpci:
     return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op;
   case ARM::tADR:
     return HasThumb2 ? (unsigned)ARM::t2ADR : Op;
   case ARM::tB:
-    return HasThumb2 ? (unsigned)ARM::t2B : Op;
+    return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op;
   case ARM::tCBZ:
     return ARM::tHINT;
   case ARM::tCBNZ:
     return ARM::tHINT;
   }
 }
 
 bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
unsigned ARMAsmBackend::adjustFixupValue(const MCFixup &Fixup, uint64_t Value,
   case ARM::fixup_arm_thumb_cb: {
     // Offset by 4 and don't encode the lower bit, which is always 0.
     // FIXME: diagnose if no Thumb2
     uint32_t Binary = (Value - 4) >> 1;
     return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3);
   }
   case ARM::fixup_arm_thumb_br:
     // Offset by 4 and don't encode the lower bit, which is always 0.
-    if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2]) {
+    if (Ctx && !STI->getFeatureBits()[ARM::FeatureThumb2] &&
+               !STI->getFeatureBits()[ARM::HasV8MBaselineOps]) {
       const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value);
       if (FixupDiagnostic) {
         Ctx->reportError(Fixup.getLoc(), FixupDiagnostic);
         return 0;
       }
     }
     return ((Value - 4) >> 1) & 0x7ff;
   case ARM::fixup_arm_thumb_bcc:

test/CodeGen/ARM/fast-tail-call.ll

 ; RUN: llc -mtriple=thumbv7-linux-gnueabi -O0 < %s | FileCheck %s
+; RUN: llc -mtriple=thumbv8m.base-arm-none-eabi -filetype=obj < %s
 
 ; Primarily a non-crash test: Thumbv7 Linux does not have FastISel support,
 ; which led (via a convoluted route) to DAG nodes after a TC_RETURN that
 ; couldn't possibly work.
 
 declare i8* @g(i8*)
 
 define i8* @f(i8* %a) {
 entry:
   %0 = tail call i8* @g(i8* %a)
   ret i8* %0
 ; CHECK: b g
 ; CHECK-NOT: ldr
 ; CHECK-NOT: str
 }

test/MC/ARM/thumb1-relax-8m-baseline.s

+@ RUN: not llvm-mc -triple thumbv6m-none-eabi -filetype=obj -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=CHECK-V6M
+@ RUN: llvm-mc -triple thumbv8m.base-none-eabi -filetype=obj -o /dev/null %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8MBASE --allow-empty
+
+@ CHECK-V8MBASE-NOT: out of range pc-relative fixup value
+@ CHECK-V6M: out of range pc-relative fixup value
+  b Lfar2
+
+  .space 2050
+Lfar2:
+  .word 42

test/MC/ARM/thumbv8m.s

 
 // 'Barrier instructions'
 
 // CHECK: isb sy              @ encoding: [0xbf,0xf3,0x6f,0x8f]
 isb sy
 
 // 'Code optimization'
 
+// CHECK: cbz r3, .Ltmp0      @ encoding: [0x03'A',0xb1'A']
+// CHECK-NEXT:                @   fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm_thumb_cb
+cbz r3, 1f
+
+// CHECK: cbnz r3, .Ltmp0     @ encoding: [0x03'A',0xb9'A']
+// CHECK-NEXT:                @   fixup A - offset: 0, value: .Ltmp0, kind: fixup_arm_thumb_cb
+cbnz r3, 1f
+
+// CHECK: b.w .Ltmp0          @ encoding: [A,0xf0'A',A,0x90'A']
+// CHECK-NEXT:                @   fixup A - offset: 0, value: .Ltmp0, kind: fixup_t2_uncondbranch
+b.w 1f
+
 // CHECK: sdiv r1, r2, r3     @ encoding: [0x92,0xfb,0xf3,0xf1]
 sdiv r1, r2, r3
 
 // CHECK: udiv r1, r2, r3     @ encoding: [0xb2,0xfb,0xf3,0xf1]
 udiv r1, r2, r3
 
 // 'XO generation'
 
 // CHECK: movw r1, #65535            @ encoding: [0x4f,0xf6,0xff,0x71]
 movw r1, #0xffff
 
 // CHECK: movt r1, #65535            @ encoding: [0xcf,0xf6,0xff,0x71]
 movt r1, #0xffff