[ARMv8-M] [3/9] Add MOVW/MOVT instructions to ARMv8-M Baseline/Mainline

[bsmith]

Summary

This patch forms part of the ARMv8-M Baseline/Mainline support, allowing the use of MOVW and MOVT in ARMv8-M Baseline

[bsmith]

Rebase onto changes done in D15275.

[bsmith]

Rebase patch against latest trunk changes.

[t.p.northover]

This looks fine to me.

Tim.

[bsmith]

Thanks, committed as r257879.

lib/Target/ARM/ARMInstrThumb2.td

 def : t2InstAlias<"mov${p}.w $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
                                                  pred:$p, zero_reg)>;
 def : t2InstAlias<"mov${p} $Rd, $imm", (t2MOVi rGPR:$Rd, t2_so_imm:$imm,
                                                pred:$p, zero_reg)>;
 
 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in
 def t2MOVi16 : T2I<(outs rGPR:$Rd), (ins imm0_65535_expr:$imm), IIC_iMOVi,
                    "movw", "\t$Rd, $imm",
-                   [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]> {
+                   [(set rGPR:$Rd, imm0_65535:$imm)]>, Sched<[WriteALU]>,
+                   Requires<[IsThumb, HasV8MBaseline]> {
   let Inst{31-27} = 0b11110;
   let Inst{25} = 1;
   let Inst{24-21} = 0b0010;
   let Inst{20} = 0; // The S bit.
   let Inst{15} = 0;
 
   bits<4> Rd;
   bits<16> imm;
 
   let Inst{11-8}  = Rd;
   let Inst{19-16} = imm{15-12};
   let Inst{26}    = imm{11};
   let Inst{14-12} = imm{10-8};
   let Inst{7-0}   = imm{7-0};
   let DecoderMethod = "DecodeT2MOVTWInstruction";
 }
 
-def : t2InstAlias<"mov${p} $Rd, $imm",
-                  (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p)>;
+def : InstAlias<"mov${p} $Rd, $imm",
+                (t2MOVi16 rGPR:$Rd, imm256_65535_expr:$imm, pred:$p)>,
+                Requires<[IsThumb, HasV8MBaseline]>;
 
 def t2MOVi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
                                 (ins i32imm:$addr, pclabel:$id), IIC_iMOVi, []>;
 
 let Constraints = "$src = $Rd" in {
 def t2MOVTi16 : T2I<(outs rGPR:$Rd),
                     (ins rGPR:$src, imm0_65535_expr:$imm), IIC_iMOVi,
                     "movt", "\t$Rd, $imm",
                     [(set rGPR:$Rd,
                           (or (and rGPR:$src, 0xffff), lo16AllZero:$imm))]>,
-                          Sched<[WriteALU]> {
+                          Sched<[WriteALU]>,
+                          Requires<[IsThumb, HasV8MBaseline]> {
   let Inst{31-27} = 0b11110;
   let Inst{25} = 1;
   let Inst{24-21} = 0b0110;
   let Inst{20} = 0; // The S bit.
   let Inst{15} = 0;
 
   bits<4> Rd;
   bits<16> imm;
 
   let Inst{11-8}  = Rd;
   let Inst{19-16} = imm{15-12};
   let Inst{26}    = imm{11};
   let Inst{14-12} = imm{10-8};
   let Inst{7-0}   = imm{7-0};
   let DecoderMethod = "DecodeT2MOVTWInstruction";
 }
 
 def t2MOVTi16_ga_pcrel : PseudoInst<(outs rGPR:$Rd),
                      (ins rGPR:$src, i32imm:$addr, pclabel:$id), IIC_iMOVi, []>,
-                     Sched<[WriteALU]>;
+                     Sched<[WriteALU]>, Requires<[IsThumb, HasV8MBaseline]>;
 } // Constraints
 
 def : T2Pat<(or rGPR:$src, 0xffff0000), (t2MOVTi16 rGPR:$src, 0xffff)>;
 
 //===----------------------------------------------------------------------===//
 //  Extend Instructions.
 //
 

 // Pseudo instruction that combines movw + movt + add pc (if pic).
 // It also makes it possible to rematerialize the instructions.
 // FIXME: Remove this when we can do generalized remat and when machine licm
 // can properly the instructions.
 let isReMaterializable = 1 in {
 def t2MOV_ga_pcrel : PseudoInst<(outs rGPR:$dst), (ins i32imm:$addr),
                                 IIC_iMOVix2addpc,
                           [(set rGPR:$dst, (ARMWrapperPIC tglobaladdr:$addr))]>,
-                          Requires<[IsThumb2, UseMovt]>;
+                          Requires<[IsThumb, HasV8MBaseline, UseMovt]>;
 
 }
 
 // ConstantPool, GlobalAddress, and JumpTable
 def : T2Pat<(ARMWrapper  tconstpool  :$dst), (t2LEApcrel tconstpool  :$dst)>;
 def : T2Pat<(ARMWrapper  tglobaladdr :$dst), (t2MOVi32imm tglobaladdr :$dst)>,
-           Requires<[IsThumb2, UseMovt]>;
+           Requires<[IsThumb, HasV8MBaseline, UseMovt]>;
 
 def : T2Pat<(ARMWrapperJT tjumptable:$dst),
             (t2LEApcrelJT tjumptable:$dst)>;
 
 // Pseudo instruction that combines ldr from constpool and add pc. This should
 // be expanded into two instructions late to allow if-conversion and
 // scheduling.
 let canFoldAsLoad = 1, isReMaterializable = 1 in

lib/Target/ARM/ARMSubtarget.cpp

bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
   // format which it's more important to get right.
   return isTargetWatchOS() || (isSwift() && !MF.getFunction()->optForMinSize());
 }
 
 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
   // immediates as it is inherently position independent, and may be out of
   // range otherwise.
-  return !NoMovt && hasV6T2Ops() &&
+  return !NoMovt && hasV8MBaselineOps() &&
          (isTargetWindows() || !MF.getFunction()->optForMinSize());
 }
 
 bool ARMSubtarget::useFastISel() const {
   // Enable fast-isel for any target, for testing only.
   if (ForceFastISel)
     return true;
 

lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp

if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(E)) {
         return (int32_t(Value) & 0x0000ffff);
       default: llvm_unreachable("Unsupported ARMFixup");
       }
     }
 
     switch (ARM16Expr->getKind()) {
     default: llvm_unreachable("Unsupported ARMFixup");
     case ARMMCExpr::VK_ARM_HI16:
-      Kind = MCFixupKind(isThumb2(STI) ? ARM::fixup_t2_movt_hi16
-                                       : ARM::fixup_arm_movt_hi16);
+      Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movt_hi16
       break;
     case ARMMCExpr::VK_ARM_LO16:
-      Kind = MCFixupKind(isThumb2(STI) ? ARM::fixup_t2_movw_lo16
-                                       : ARM::fixup_arm_movw_lo16);
+      Kind = MCFixupKind(isThumb(STI) ? ARM::fixup_t2_movw_lo16
       break;
     }
 
     Fixups.push_back(MCFixup::create(0, E, Kind, MI.getLoc()));
     return 0;
   }
   // If the expression doesn't have :upper16: or :lower16: on it,
   // it's just a plain immediate expression, previously those evaluated to

test/CodeGen/ARM/movt.ll

 ; RUN: llc -mtriple=arm-eabi -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - | FileCheck %s
 ; rdar://7317664
 
+; RUN: llc -mtriple=thumbv8m.base %s -o - | FileCheck %s
+
 define i32 @t(i32 %X) nounwind {
 ; CHECK-LABEL: t:
-; CHECK: movt r0, #65535
+; CHECK: movt r{{[0-9]}}, #65535
 entry:
   %0 = or i32 %X, -65536
   ret i32 %0
 }
 
 define i32 @t2(i32 %X) nounwind {
 ; CHECK-LABEL: t2:
-; CHECK: movt r0, #65534
+; CHECK: movt r{{[0-9]}}, #65534
 entry:
   %0 = or i32 %X, -131072
   %1 = and i32 %0, -65537
   ret i32 %1
 }

test/MC/ARM/thumb-movwt-reloc.s

+@ RUN: llvm-mc -triple thumbv8m.base-eabi -filetype asm -o - %s | FileCheck %s
+@ RUN: llvm-mc -triple thumbv8m.base-eabi -filetype obj -o - %s | llvm-readobj -r \
+@ RUN:   | FileCheck -check-prefix CHECK-RELOCATIONS %s
+
+  .syntax unified
+
+  .type function,%function
+function:
+  bx lr
+
+  .global external
+  .type external,%function
+
+  .type test,%function
+test:
+  movw r0, :lower16:function
+  movt r0, :upper16:function
+
+@ CHECK-LABEL: test:
+@ CHECK:  movw r0, :lower16:function
+@ CHECK:  movt r0, :upper16:function
+
+@ CHECK-RELOCATIONS: Relocations [
+@ CHECK-RELOCATIONS:   0x2 R_ARM_THM_MOVW_ABS_NC function 0x0
+@ CHECK-RELOCATIONS:   0x6 R_ARM_THM_MOVT_ABS function 0x0
+@ CHECK-RELOCATIONS: ]
+

test/MC/ARM/thumbv8m.s

 .arm
 
 // Instruction availibility checks
 
 // 'Barrier instructions'
 
 // CHECK: isb sy              @ encoding: [0xbf,0xf3,0x6f,0x8f]
 isb sy
+
+// 'XO generation'
+
+// CHECK: movw r1, #65535            @ encoding: [0x4f,0xf6,0xff,0x71]
+movw r1, #0xffff
+
+// CHECK: movt r1, #65535            @ encoding: [0xcf,0xf6,0xff,0x71]
+movt r1, #0xffff