[ARMv8-M] [1/9] Split out ARMv8-A semaphores and atomics and ARMv7-M exclusives as separate features

[bsmith]

Summary

This patch forms part of the ARMv8-M Baseline/Mainline support.

The thumb versions of the ARMv8-A semaphores and atomics and the ARMv7-M exclusives instructions are part of the new ARMv8-M architectures, as such we must split these instruction classes out into separate subtarget features so they can be used by ARMv8-M.

[bsmith]

Rebase patch against latest trunk changes.

[t.p.northover]

One tiny nit. Otherwise looks fine.

Tim.

lib/Target/ARM/ARM.td

79–80

This really does just seem to be clrex, so I'd be a bit more explicit about that rather than implying there are lots of them. FeatureV7Clrex maybe, to also point out that it's v7 that added it?

Also, typo in "excluisive".

[bsmith]

Thanks, committed as r257877.

lib/Target/ARM/ARM.td

def FeatureHWDiv  : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
                                      "Enable divide instructions">;
 def FeatureHWDivARM  : SubtargetFeature<"hwdiv-arm",
                                         "HasHardwareDivideInARM", "true",
                                       "Enable divide instructions in ARM mode">;
 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
                                  "Enable Thumb2 extract and pack instructions">;
 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
                                    "Has data barrier (dmb / dsb) instructions">;
+def FeatureV7Exclusives : SubtargetFeature<"v7exclusives", "HasV7Exclusives", "true",
+                                           "Has v7 excluisive (clrex) instructions">;
+def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
+                                             "HasAcquireRelease", "true",
+                         "Has v8 acquire/release (lda/ldaex etc) instructions">;
 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
                                          "FP compare + branch is slow">;
 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
                           "Floating point unit supports single precision only">;
 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
                            "Enable support for Performance Monitor extensions">;
 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
                           "Enable support for TrustZone security extensions">;

 def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
                                    "Support ARM v6k instructions",
                                    [HasV6Ops]>;
 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
                                    "Support ARM v6t2 instructions",
                                    [HasV6MOps, HasV6KOps, FeatureThumb2]>;
 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
                                    "Support ARM v7 instructions",
-                                   [HasV6T2Ops, FeaturePerfMon]>;
+                                   [HasV6T2Ops, FeaturePerfMon,
+                                    FeatureV7Exclusives]>;
 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
                                    "Support ARM v8 instructions",
-                                   [HasV7Ops]>;
+                                   [HasV7Ops, FeatureAcquireRelease]>;
 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
                                    "Support ARM v8.1a instructions",
                                    [HasV8Ops]>;
 def HasV8_2aOps   : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
                                    "Support ARM v8.2a instructions",
                                    [HasV8_1aOps]>;
 
 

 
 def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
                                    "Qualcomm ARM processors", []>;
 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
                                    "Swift ARM processors", []>;
 
 
 def ProcR4      : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
-                                    "Cortex-R4 ARM processors", []>;
 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
                                    "Cortex-R5 ARM processors", []>;
 def ProcR7      : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
                                    "Cortex-R7 ARM processors", []>;
 
 
 //===----------------------------------------------------------------------===//
 // ARM schedules.

lib/Target/ARM/ARMInstrFormats.td

class AIstrex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
   let Inst{15-12} = Rd;
 }
 
 // Exclusive load/store instructions
 
 class AIldaex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
               string opc, string asm, list<dag> pattern>
   : AIldr_ex_or_acq<opcod, 0b10, oops, iops, itin, opc, asm, pattern>,
-    Requires<[IsARM, HasV8]>;
+    Requires<[IsARM, HasAcquireRelease, HasV7Exclusives]>;
 
 class AIstlex<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
               string opc, string asm, list<dag> pattern>
   : AIstr_ex_or_rel<opcod, 0b10, oops, iops, itin, opc, asm, pattern>,
-    Requires<[IsARM, HasV8]> {
+    Requires<[IsARM, HasAcquireRelease, HasV7Exclusives]> {
   bits<4> Rd;
   let Inst{15-12} = Rd;
 }
 
 class AIswp<bit b, dag oops, dag iops, string opc, list<dag> pattern>
   : AI<oops, iops, MiscFrm, NoItinerary, opc, "\t$Rt, $Rt2, $addr", pattern> {
   bits<4> Rt;
   bits<4> Rt2;
   bits<4> addr;
   let Inst{27-23} = 0b00010;
   let Inst{22} = b;
   let Inst{21-20} = 0b00;
   let Inst{19-16} = addr;
   let Inst{15-12} = Rt;
   let Inst{11-4} = 0b00001001;
   let Inst{3-0} = Rt2;
 
   let Unpredictable{11-8} = 0b1111;
   let DecoderMethod = "DecodeSwap";
 }
 // Acquire/Release load/store instructions
 class AIldracq<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
               string opc, string asm, list<dag> pattern>
   : AIldr_ex_or_acq<opcod, 0b00, oops, iops, itin, opc, asm, pattern>,
-    Requires<[IsARM, HasV8]>;
+    Requires<[IsARM, HasAcquireRelease]>;
 
 class AIstrrel<bits<2> opcod, dag oops, dag iops, InstrItinClass itin,
               string opc, string asm, list<dag> pattern>
   : AIstr_ex_or_rel<opcod, 0b00, oops, iops, itin, opc, asm, pattern>,
-    Requires<[IsARM, HasV8]> {
+    Requires<[IsARM, HasAcquireRelease]> {
   let Inst{15-12}   = 0b1111;
 }
 
 // addrmode1 instructions
 class AI1<bits<4> opcod, dag oops, dag iops, Format f, InstrItinClass itin,
           string opc, string asm, list<dag> pattern>
   : I<oops, iops, AddrMode1, 4, IndexModeNone, f, itin,
       opc, asm, "", pattern> {

lib/Target/ARM/ARMInstrInfo.td

 def HasT2ExtractPack : Predicate<"Subtarget->hasT2ExtractPack()">,
                                  AssemblerPredicate<"FeatureT2XtPk",
                                                      "pack/extract">;
 def HasDSP           : Predicate<"Subtarget->hasDSP()">,
                                  AssemblerPredicate<"FeatureDSP", "dsp">;
 def HasDB            : Predicate<"Subtarget->hasDataBarrier()">,
                                  AssemblerPredicate<"FeatureDB",
                                                     "data-barriers">;
+def HasV7Exclusives  : Predicate<"Subtarget->hasV7Exclusives()">,
+                                 AssemblerPredicate<"FeatureV7Exclusives",
+                                                    "v7 exclusives">;
+def HasAcquireRelease : Predicate<"Subtarget->hasAcquireRelease()">,
+                                  AssemblerPredicate<"FeatureAcquireRelease",
+                                                     "acquire/release">;
 def HasMP            : Predicate<"Subtarget->hasMPExtension()">,
                                  AssemblerPredicate<"FeatureMP",
                                                     "mp-extensions">;
 def HasVirtualization: Predicate<"false">,
                                  AssemblerPredicate<"FeatureVirtualization",
                                                    "virtualization-extensions">;
 def HasTrustZone     : Predicate<"Subtarget->hasTrustZone()">,
                                  AssemblerPredicate<"FeatureTrustZone",

lib/Target/ARM/ARMInstrThumb2.td

 def t2LDRBT  : T2IldT<0, 0b00, "ldrbt", IIC_iLoad_bh_i>;
 def t2LDRHT  : T2IldT<0, 0b01, "ldrht", IIC_iLoad_bh_i>;
 def t2LDRSBT : T2IldT<1, 0b00, "ldrsbt", IIC_iLoad_bh_i>;
 def t2LDRSHT : T2IldT<1, 0b01, "ldrsht", IIC_iLoad_bh_i>;
 
 class T2Ildacq<bits<4> bits23_20, bits<2> bit54, dag oops, dag iops,
                string opc, string asm, list<dag> pattern>
   : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary,
-            opc, asm, "", pattern>, Requires<[IsThumb, HasV8]> {
+            opc, asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]> {
   bits<4> Rt;
   bits<4> addr;
 
   let Inst{31-27} = 0b11101;
   let Inst{26-24} = 0b000;
   let Inst{23-20} = bits23_20;
   let Inst{11-6} = 0b111110;
   let Inst{5-4} = bit54;
def t2STRD_POST : T2Ii8s4post<0, 1, 0, (outs GPR:$wb),
                  (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr,
                       t2am_imm8s4_offset:$imm),
                  IIC_iStore_d_ru, "strd", "\t$Rt, $Rt2, $addr$imm",
                  "$addr.base = $wb", []>;
 
 class T2Istrrel<bits<2> bit54, dag oops, dag iops,
                 string opc, string asm, list<dag> pattern>
   : Thumb2I<oops, iops, AddrModeNone, 4, NoItinerary, opc,
-            asm, "", pattern>, Requires<[IsThumb, HasV8]> {
+            asm, "", pattern>, Requires<[IsThumb, HasAcquireRelease]> {
   bits<4> Rt;
   bits<4> addr;
 
   let Inst{31-27} = 0b11101;
   let Inst{26-20} = 0b0001100;
   let Inst{11-6} = 0b111110;
   let Inst{5-4} = bit54;
   let Inst{3-0} = 0b1111;
def t2LDREXD : T2I_ldrex<0b0111, (outs rGPR:$Rt, rGPR:$Rt2),
                Requires<[IsThumb2, IsNotMClass]> {
   bits<4> Rt2;
   let Inst{11-8} = Rt2;
 }
 def t2LDAEXB : T2I_ldrex<0b1100, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "ldaexb", "\t$Rt, $addr", "",
                          [(set rGPR:$Rt, (ldaex_1 addr_offset_none:$addr))]>,
-               Requires<[IsThumb, HasV8]>;
+               Requires<[IsThumb, HasAcquireRelease, HasV7Exclusives]>;
 def t2LDAEXH : T2I_ldrex<0b1101, (outs rGPR:$Rt), (ins addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "ldaexh", "\t$Rt, $addr", "",
                          [(set rGPR:$Rt, (ldaex_2 addr_offset_none:$addr))]>,
-               Requires<[IsThumb, HasV8]>;
+               Requires<[IsThumb, HasAcquireRelease, HasV7Exclusives]>;
 def t2LDAEX  : Thumb2I<(outs rGPR:$Rt), (ins addr_offset_none:$addr),
                        AddrModeNone, 4, NoItinerary,
                        "ldaex", "\t$Rt, $addr", "",
                          [(set rGPR:$Rt, (ldaex_4 addr_offset_none:$addr))]>,
-               Requires<[IsThumb, HasV8]> {
+               Requires<[IsThumb, HasAcquireRelease, HasV7Exclusives]> {
   bits<4> Rt;
   bits<4> addr;
   let Inst{31-27} = 0b11101;
   let Inst{26-20} = 0b0001101;
   let Inst{19-16} = addr;
   let Inst{15-12} = Rt;
   let Inst{11-8} = 0b1111;
   let Inst{7-0} = 0b11101111;
 }
 let hasExtraDefRegAllocReq = 1 in
 def t2LDAEXD : T2I_ldrex<0b1111, (outs rGPR:$Rt, rGPR:$Rt2),
                          (ins addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "ldaexd", "\t$Rt, $Rt2, $addr", "",
-                         [], {?, ?, ?, ?}>, Requires<[IsThumb, HasV8]> {
+                         [], {?, ?, ?, ?}>, Requires<[IsThumb,
+                         HasAcquireRelease, HasV7Exclusives, IsNotMClass]> {
   bits<4> Rt2;
   let Inst{11-8} = Rt2;
 
   let Inst{7} = 1;
 }
 }
 
 let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
def t2STREXD : T2I_strex<0b0111, (outs rGPR:$Rd),
   let Inst{11-8} = Rt2;
 }
 def t2STLEXB : T2I_strex<0b1100, (outs rGPR:$Rd),
                          (ins rGPR:$Rt, addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "stlexb", "\t$Rd, $Rt, $addr", "",
                          [(set rGPR:$Rd,
                                (stlex_1 rGPR:$Rt, addr_offset_none:$addr))]>,
-                         Requires<[IsThumb, HasV8]>;
+                         Requires<[IsThumb, HasAcquireRelease,
+                                   HasV7Exclusives]>;
 
 def t2STLEXH : T2I_strex<0b1101, (outs rGPR:$Rd),
                          (ins rGPR:$Rt, addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "stlexh", "\t$Rd, $Rt, $addr", "",
                          [(set rGPR:$Rd,
                                (stlex_2 rGPR:$Rt, addr_offset_none:$addr))]>,
-                         Requires<[IsThumb, HasV8]>;
+                         Requires<[IsThumb, HasAcquireRelease,
+                                   HasV7Exclusives]>;
 
 def t2STLEX  : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
                              addr_offset_none:$addr),
                   AddrModeNone, 4, NoItinerary,
                   "stlex", "\t$Rd, $Rt, $addr", "",
                   [(set rGPR:$Rd,
                         (stlex_4 rGPR:$Rt, addr_offset_none:$addr))]>,
-                  Requires<[IsThumb, HasV8]> {
+                  Requires<[IsThumb, HasAcquireRelease, HasV7Exclusives]> {
   bits<4> Rd;
   bits<4> Rt;
   bits<4> addr;
   let Inst{31-27} = 0b11101;
   let Inst{26-20} = 0b0001100;
   let Inst{19-16} = addr;
   let Inst{15-12} = Rt;
   let Inst{11-4}  = 0b11111110;
   let Inst{3-0}   = Rd;
 }
 let hasExtraSrcRegAllocReq = 1 in
 def t2STLEXD : T2I_strex<0b1111, (outs rGPR:$Rd),
                          (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
                          AddrModeNone, 4, NoItinerary,
                          "stlexd", "\t$Rd, $Rt, $Rt2, $addr", "", [],
-                         {?, ?, ?, ?}>, Requires<[IsThumb, HasV8]> {
+                         {?, ?, ?, ?}>, Requires<[IsThumb, HasAcquireRelease,
+                         HasV7Exclusives, IsNotMClass]> {
   bits<4> Rt2;
   let Inst{11-8} = Rt2;
 }
 }
 
 def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", [(int_arm_clrex)]>,
-            Requires<[IsThumb2, HasV7]>  {
+            Requires<[IsThumb, HasV7Exclusives]>  {
   let Inst{31-16} = 0xf3bf;
   let Inst{15-14} = 0b10;
   let Inst{13} = 0;
   let Inst{12} = 0;
   let Inst{11-8} = 0b1111;
   let Inst{7-4} = 0b0010;
   let Inst{3-0} = 0b1111;
 }
 
 def : T2Pat<(and (ldrex_1 addr_offset_none:$addr), 0xff),
             (t2LDREXB addr_offset_none:$addr)>;
 def : T2Pat<(and (ldrex_2 addr_offset_none:$addr), 0xffff),
             (t2LDREXH addr_offset_none:$addr)>;
 def : T2Pat<(strex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
             (t2STREXB GPR:$Rt, addr_offset_none:$addr)>;
 def : T2Pat<(strex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
             (t2STREXH GPR:$Rt, addr_offset_none:$addr)>;
 
 def : T2Pat<(and (ldaex_1 addr_offset_none:$addr), 0xff),
-            (t2LDAEXB addr_offset_none:$addr)>;
+            (t2LDAEXB addr_offset_none:$addr)>,
+            Requires<[IsThumb, HasAcquireRelease, HasV7Exclusives]>;
 def : T2Pat<(and (ldaex_2 addr_offset_none:$addr), 0xffff),
-            (t2LDAEXH addr_offset_none:$addr)>;
+            (t2LDAEXH addr_offset_none:$addr)>,
+            Requires<[IsThumb, HasAcquireRelease, HasV7Exclusives]>;
 def : T2Pat<(stlex_1 (and GPR:$Rt, 0xff), addr_offset_none:$addr),
-            (t2STLEXB GPR:$Rt, addr_offset_none:$addr)>;
+            (t2STLEXB GPR:$Rt, addr_offset_none:$addr)>,
+            Requires<[IsThumb, HasAcquireRelease, HasV7Exclusives]>;
 def : T2Pat<(stlex_2 (and GPR:$Rt, 0xffff), addr_offset_none:$addr),
-            (t2STLEXH GPR:$Rt, addr_offset_none:$addr)>;
+            (t2STLEXH GPR:$Rt, addr_offset_none:$addr)>,
+            Requires<[IsThumb, HasAcquireRelease, HasV7Exclusives]>;
 
 //===----------------------------------------------------------------------===//
 // SJLJ Exception handling intrinsics
 //   eh_sjlj_setjmp() is an instruction sequence to store the return
 //   address and save #0 in R0 for the non-longjmp case.
 //   Since by its nature we may be coming from some other function to get
 //   here, and we're using the stack frame for the containing function to
 //   save/restore registers, we can't keep anything live in regs across

lib/Target/ARM/ARMSubtarget.h

protected:
   /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
   /// instructions.
   bool HasT2ExtractPack;
 
   /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
   /// instructions.
   bool HasDataBarrier;
 
+  /// HasV7Exclusives - True if the subtarget supports CLREX instructions
+  bool HasV7Exclusives;
+
+  /// HasAcquireRelease - True if the subtarget supports v8 atomics (LDA/LDAEX etc)
+  /// instructions
+  bool HasAcquireRelease;
+
   /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
   /// over 16-bit ones.
   bool Pref32BitThumb;
 
   /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
   /// that partially update CPSR and add false dependency on the previous
   /// CPSR setting instruction.
   bool AvoidCPSRPartialUpdate;
public:
   bool useNEONForSinglePrecisionFP() const {
     return hasNEON() && UseNEONForSinglePrecisionFP;
   }
 
   bool hasDivide() const { return HasHardwareDivide; }
   bool hasDivideInARMMode() const { return HasHardwareDivideInARM; }
   bool hasT2ExtractPack() const { return HasT2ExtractPack; }
   bool hasDataBarrier() const { return HasDataBarrier; }
+  bool hasV7Exclusives() const { return HasV7Exclusives; }
+  bool hasAcquireRelease() const { return HasAcquireRelease; }
   bool hasAnyDataBarrier() const {
     return HasDataBarrier || (hasV6Ops() && !isThumb());
   }
   bool useMulOps() const { return UseMulOps; }
   bool useFPVMLx() const { return !SlowFPVMLx; }
   bool hasVMLxForwarding() const { return HasVMLxForwarding; }
   bool isFPBrccSlow() const { return SlowFPBrcc; }
   bool isFPOnlySP() const { return FPOnlySP; }

lib/Target/ARM/ARMSubtarget.cpp

void ARMSubtarget::initializeEnvironment() {
   HasCrypto = false;
   HasCRC = false;
   HasZeroCycleZeroing = false;
   StrictAlign = false;
   HasDSP = false;
   UseNaClTrap = false;
   GenLongCalls = false;
   UnsafeFPMath = false;
+  HasV7Exclusives = false;
+  HasAcquireRelease = false;
 
   // MCAsmInfo isn't always present (e.g. in opt) so we can't initialize this
   // directly from it, but we can try to make sure they're consistent when both
   // available.
   UseSjLjEH = isTargetDarwin() && !isTargetWatchOS();
   assert((!TM.getMCAsmInfo() ||
           (TM.getMCAsmInfo()->getExceptionHandlingType() ==
            ExceptionHandling::SjLj) == UseSjLjEH) &&

test/MC/ARM/arm11-hint-instr.s

 @------------------------------------------------------------------------------
 @ v6T2 using THUMB encoding (thumb triple)
 @------------------------------------------------------------------------------
 @ CHECK-THUMB: nop                             @ encoding: [0x00,0xbf]
 @ CHECK-THUMB: yield                           @ encoding: [0x10,0xbf]
 @ CHECK-THUMB: wfe                             @ encoding: [0x20,0xbf]
 @ CHECK-THUMB: wfi                             @ encoding: [0x30,0xbf]
 @ CHECK-THUMB: sev                             @ encoding: [0x40,0xbf]
-@ CHECK-ERROR-THUMB: error: instruction requires: armv7
+@ CHECK-ERROR-THUMB: error: instruction requires: v7 exclusives
 @ CHECK-ERROR-THUMB: clrex
 @ CHECK-ERROR-THUMB: ^
 
 @------------------------------------------------------------------------------
 @ v6M using THUMB encoding
 @------------------------------------------------------------------------------
 @ CHECK-V6M: nop                             @ encoding: [0x00,0xbf]
 @ CHECK-V6M: yield                           @ encoding: [0x10,0xbf]
 @ CHECK-V6M: wfe                             @ encoding: [0x20,0xbf]
 @ CHECK-V6M: wfi                             @ encoding: [0x30,0xbf]
 @ CHECK-V6M: sev                             @ encoding: [0x40,0xbf]
-@ CHECK-ERROR-V6M: error: instruction requires: armv7
+@ CHECK-ERROR-V6M: error: instruction requires: v7 exclusives
 @ CHECK-ERROR-V6M: clrex
 @ CHECK-ERROR-V6M: ^

test/MC/ARM/load-store-acquire-release-v8-thumb.s

 @ RUN: llvm-mc -triple=thumbv8 -show-encoding < %s | FileCheck %s
 @ RUN: not llvm-mc -triple=thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
         ldaexb  r3, [r4]
         ldaexh  r2, [r5]
         ldaex  r1, [r7]
         ldaexd  r6, r7, [r8]
 
 @ CHECK:  ldaexb  r3, [r4]                @ encoding: [0xd4,0xe8,0xcf,0x3f]
 @ CHECK:  ldaexh  r2, [r5]                @ encoding: [0xd5,0xe8,0xdf,0x2f]
 @ CHECK:  ldaex  r1, [r7]                @ encoding: [0xd7,0xe8,0xef,0x1f]
 @ CHECK:  ldaexd  r6, r7, [r8]            @ encoding: [0xd8,0xe8,0xff,0x67]
-@ CHECK-V7: error: instruction requires: armv8
-@ CHECK-V7: error: instruction requires: armv8
-@ CHECK-V7: error: instruction requires: armv8
-@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: acquire/release
+@ CHECK-V7: error: instruction requires: acquire/release
+@ CHECK-V7: error: instruction requires: acquire/release
+@ CHECK-V7: error: instruction requires: acquire/release
 
         stlexb  r1, r3, [r4]
         stlexh  r4, r2, [r5]
         stlex  r2, r1, [r7]
         stlexd  r6, r2, r3, [r8]
 @ CHECK: stlexb r1, r3, [r4]            @ encoding: [0xc4,0xe8,0xc1,0x3f]
 @ CHECK: stlexh r4, r2, [r5]            @ encoding: [0xc5,0xe8,0xd4,0x2f]
 @ CHECK: stlex r2, r1, [r7]            @ encoding: [0xc7,0xe8,0xe2,0x1f]
 @ CHECK: stlexd r6, r2, r3, [r8]        @ encoding: [0xc8,0xe8,0xf6,0x23]
-@ CHECK-V7: error: instruction requires: armv8
-@ CHECK-V7: error: instruction requires: armv8
-@ CHECK-V7: error: instruction requires: armv8
-@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: acquire/release
+@ CHECK-V7: error: instruction requires: acquire/release
+@ CHECK-V7: error: instruction requires: acquire/release
+@ CHECK-V7: error: instruction requires: acquire/release
 
          lda r5, [r6]
          ldab r5, [r6]
          ldah r12, [r9]
 @ CHECK: lda r5, [r6]                   @ encoding: [0xd6,0xe8,0xaf,0x5f]
 @ CHECK: ldab r5, [r6]                  @ encoding: [0xd6,0xe8,0x8f,0x5f]
 @ CHECK: ldah r12, [r9]                 @ encoding: [0xd9,0xe8,0x9f,0xcf]
-@ CHECK-V7: error: instruction requires: armv8
-@ CHECK-V7: error: instruction requires: armv8
-@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: acquire/release
+@ CHECK-V7: error: instruction requires: acquire/release
+@ CHECK-V7: error: instruction requires: acquire/release
 
          stl r3, [r0]
          stlb r2, [r1]
          stlh r2, [r3]
 @ CHECK: stl r3, [r0]                   @ encoding: [0xc0,0xe8,0xaf,0x3f]
 @ CHECK: stlb r2, [r1]                  @ encoding: [0xc1,0xe8,0x8f,0x2f]
 @ CHECK: stlh r2, [r3]                  @ encoding: [0xc3,0xe8,0x9f,0x2f]
-@ CHECK-V7: error: instruction requires: armv8
-@ CHECK-V7: error: instruction requires: armv8
-@ CHECK-V7: error: instruction requires: armv8
+@ CHECK-V7: error: instruction requires: acquire/release
+@ CHECK-V7: error: instruction requires: acquire/release
+@ CHECK-V7: error: instruction requires: acquire/release

test/MC/ARM/load-store-acquire-release-v8.s

 @ RUN: llvm-mc -triple=armv8 -show-encoding < %s | FileCheck %s
 @ RUN: not llvm-mc -triple=armv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
         ldaexb  r3, [r4]
         ldaexh  r2, [r5]
         ldaex  r1, [r7]
         ldaexd  r6, r7, [r8]
 
 @ CHECK: ldaexb r3, [r4]                @ encoding: [0x9f,0x3e,0xd4,0xe1]
 @ CHECK: ldaexh r2, [r5]                @ encoding: [0x9f,0x2e,0xf5,0xe1]
 @ CHECK: ldaex r1, [r7]                @ encoding: [0x9f,0x1e,0x97,0xe1]
 @ CHECK: ldaexd r6, r7, [r8]            @ encoding: [0x9f,0x6e,0xb8,0xe1]
-@ CHECK-V7: instruction requires: armv8
-@ CHECK-V7: instruction requires: armv8
-@ CHECK-V7: instruction requires: armv8
-@ CHECK-V7: instruction requires: armv8
+@ CHECK-V7: instruction requires: acquire/release
+@ CHECK-V7: instruction requires: acquire/release
+@ CHECK-V7: instruction requires: acquire/release
+@ CHECK-V7: instruction requires: acquire/release
 
         stlexb  r1, r3, [r4]
         stlexh  r4, r2, [r5]
         stlex  r2, r1, [r7]
         stlexd  r6, r2, r3, [r8]
 @ CHECK: stlexb r1, r3, [r4]            @ encoding: [0x93,0x1e,0xc4,0xe1]
 @ CHECK: stlexh r4, r2, [r5]            @ encoding: [0x92,0x4e,0xe5,0xe1]
 @ CHECK: stlex r2, r1, [r7]            @ encoding: [0x91,0x2e,0x87,0xe1]
 @ CHECK: stlexd r6, r2, r3, [r8]        @ encoding: [0x92,0x6e,0xa8,0xe1]
-@ CHECK-V7: instruction requires: armv8
-@ CHECK-V7: instruction requires: armv8
-@ CHECK-V7: instruction requires: armv8
-@ CHECK-V7: instruction requires: armv8
+@ CHECK-V7: instruction requires: acquire/release
+@ CHECK-V7: instruction requires: acquire/release
+@ CHECK-V7: instruction requires: acquire/release
+@ CHECK-V7: instruction requires: acquire/release
 
          lda r5, [r6]
          ldab r5, [r6]
          ldah r12, [r9]
 @ CHECK: lda r5, [r6]                   @ encoding: [0x9f,0x5c,0x96,0xe1]
 @ CHECK: ldab r5, [r6]                  @ encoding: [0x9f,0x5c,0xd6,0xe1]
 @ CHECK: ldah r12, [r9]                 @ encoding: [0x9f,0xcc,0xf9,0xe1]
-@ CHECK-V7: instruction requires: armv8
-@ CHECK-V7: instruction requires: armv8
-@ CHECK-V7: instruction requires: armv8
+@ CHECK-V7: instruction requires: acquire/release
+@ CHECK-V7: instruction requires: acquire/release
+@ CHECK-V7: instruction requires: acquire/release
 
          stl r3, [r0]
          stlb r2, [r1]
          stlh r2, [r3]
 @ CHECK: stl r3, [r0]                   @ encoding: [0x93,0xfc,0x80,0xe1]
 @ CHECK: stlb r2, [r1]                  @ encoding: [0x92,0xfc,0xc1,0xe1]
 @ CHECK: stlh r2, [r3]                  @ encoding: [0x92,0xfc,0xe3,0xe1]
-@ CHECK-V7: instruction requires: armv8
-@ CHECK-V7: instruction requires: armv8
-@ CHECK-V7: instruction requires: armv8
+@ CHECK-V7: instruction requires: acquire/release
+@ CHECK-V7: instruction requires: acquire/release
+@ CHECK-V7: instruction requires: acquire/release