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Wrong FNSTSW size operator.
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Authored by m_zuckerman on Nov 24 2015, 7:01 AM.

Details

Summary

By intel spec

9B DD /7FSTSW m2byteValid Valid Store FPU status word at m2byteafter checking for pending unmasked floating-point exceptions.
9B DF E0FSTSW AXValid Valid Store FPU status word in AX register after checking for pending unmasked floating-point exceptions.
DD /7FNSTSW *m2byteValid Valid Store FPU status word at m2bytewithout checking for pending unmasked floating-point exceptions.
DF E0FNSTSW *AXValid Valid Store FPU status word in AX register without checking for pending unmasked floating-point exceptions

m2byte is word register, and therefor instruction operand need to be change from f32mem to i16mem.

Diff Detail

Event Timeline

m_zuckerman retitled this revision from to Wrong FNSTSW size operator. .
m_zuckerman updated this object.
m_zuckerman added reviewers: atrick, enderby, spyffe.
craig.topper accepted this revision.Dec 1 2015, 8:15 AM
craig.topper added a reviewer: craig.topper.
craig.topper added a subscriber: craig.topper.

LGTM

This revision is now accepted and ready to land.Dec 1 2015, 8:15 AM
Closed by commit rL254512: By intel spec (authored by mzuckerm). · Explain WhyDec 2 2015, 6:37 AM
This revision was automatically updated to reflect the committed changes.

Is there no way to test this?

m_zuckerman added a child revision: Restricted Differential Revision.Dec 2 2015, 8:13 AM
m_zuckerman updated this revision to Diff 41636.Dec 2 2015, 8:52 AM
m_zuckerman edited edge metadata.
m_zuckerman removed rL LLVM as the repository for this revision.