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Differential D14953

Wrong FNSTSW size operator.
ClosedPublic

Authored by m_zuckerman on Nov 24 2015, 7:01 AM.

Details

Reviewers
spyffe
enderby
atrick
craig.topper
Commits
rG15152a5c4142: By intel spec
rL254512: By intel spec
Summary

By intel spec

9B DD /7FSTSW m2byteValid Valid Store FPU status word at m2byteafter checking for pending unmasked floating-point exceptions.
9B DF E0FSTSW AXValid Valid Store FPU status word in AX register after checking for pending unmasked floating-point exceptions.
DD /7FNSTSW *m2byteValid Valid Store FPU status word at m2bytewithout checking for pending unmasked floating-point exceptions.
DF E0FNSTSW *AXValid Valid Store FPU status word in AX register without checking for pending unmasked floating-point exceptions

m2byte is word register, and therefor instruction operand need to be change from f32mem to i16mem.

Diff Detail

Event Timeline

m_zuckerman updated this revision to Diff 41038.Nov 24 2015, 7:01 AM
m_zuckerman retitled this revision from to Wrong FNSTSW size operator. .
m_zuckerman updated this object.
m_zuckerman added reviewers: atrick, enderby, spyffe.
m_zuckerman added a subscriber: llvm-commits.Dec 1 2015, 6:50 AM

PING

craig.topper accepted this revision.Dec 1 2015, 8:15 AM
craig.topper added a reviewer: craig.topper.
craig.topper added a subscriber: craig.topper.

LGTM

This revision is now accepted and ready to land.Dec 1 2015, 8:15 AM
Closed by commit rL254512: By intel spec (authored by mzuckerm). · Explain WhyDec 2 2015, 6:37 AM
This revision was automatically updated to reflect the committed changes.
mcrosier added a subscriber: mcrosier.Dec 2 2015, 6:55 AM

Is there no way to test this?

m_zuckerman added a child revision: Restricted Differential Revision.Dec 2 2015, 8:13 AM
m_zuckerman added a child revision: D15155: Adding test for fnstsw .Dec 2 2015, 8:33 AM
m_zuckerman updated this revision to Diff 41636.Dec 2 2015, 8:52 AM
m_zuckerman edited edge metadata.
m_zuckerman removed rL LLVM as the repository for this revision.
jevinskie added a subscriber: jevinskie.Dec 2 2015, 11:30 AM

Revision Contents

PathSize
test/
MC/
X86/
2 lines

Diff 41636

test/MC/X86/intel-syntax.s

Show First 20 Lines • Show All 483 Lines • ▼ Show 20 Lines
test [ECX], AX test [ECX], AX
test AL, [ECX] test AL, [ECX]
test [ECX], AL test [ECX], AL
// CHECK: fnstsw %ax // CHECK: fnstsw %ax
// CHECK: fnstsw %ax // CHECK: fnstsw %ax
// CHECK: fnstsw %ax // CHECK: fnstsw %ax
// CHECK: fnstsw %ax // CHECK: fnstsw %ax
// CHECK: fnstsw (%eax)
fnstsw fnstsw
fnstsw AX fnstsw AX
fnstsw EAX fnstsw EAX
fnstsw AL fnstsw AL
fnstsw WORD PTR [EAX]
// CHECK: faddp %st(1) // CHECK: faddp %st(1)
// CHECK: fmulp %st(1) // CHECK: fmulp %st(1)
// CHECK: fsubrp %st(1) // CHECK: fsubrp %st(1)
// CHECK: fsubp %st(1) // CHECK: fsubp %st(1)
// CHECK: fdivrp %st(1) // CHECK: fdivrp %st(1)
// CHECK: fdivp %st(1) // CHECK: fdivp %st(1)
faddp ST(1), ST(0) faddp ST(1), ST(0)
▲ Show 20 Lines • Show All 221 Lines • Show Last 20 Lines