[x86] translating "fp" (floating point) instructions from {fadd,fdiv,fmul,fsub,fsubr,fdivr} to {faddp,fdivp,fmulp,fsubp,fsubrp,fdivrp}

[m_zuckerman]

Summary

LLVM Missing the following instructions: fadd\fdiv\fmul\fsub\fsubr\fdivr.
GAS and MS supporting this instruction and lowering them in to a faddp\fdivp\fmulp\fsubp\fsubrp\fdivrp instructions.

[rnk]

This seems no worse than what we already do. I'm fine with it.

lib/Target/X86/AsmParser/X86AsmParser.cpp

2221 ↗

(On Diff #38850)

Please put spaces between the comment and the start of the text.

2227 ↗

(On Diff #38850)

Please use clang-format here.

[m_zuckerman]

ping

[m_zuckerman]

ping

[rnk]

lgtm

llvm/trunk/lib/Target/X86/AsmParser/X86AsmParser.cpp

if (getLexer().isNot(AsmToken::EndOfStatement))
                                   "unexpected token in argument list");
    }
 
   // Consume the EndOfStatement or the prefix separator Slash
   if (getLexer().is(AsmToken::EndOfStatement) ||
       (isPrefix && getLexer().is(AsmToken::Slash)))
     Parser.Lex();
 
+  // This is for gas compatibility and cannot be done in td.
+  // Adding "p" for some floating point with no argument.
+  // For example: fsub --> fsubp
+  bool IsFp =
+    Name == "fsub" || Name == "fdiv" || Name == "fsubr" || Name == "fdivr";
+  if (IsFp && Operands.size() == 1) {
+    const char *Repl = StringSwitch<const char *>(Name)
+      .Case("fsub", "fsubp")
+      .Case("fdiv", "fdivp")
+      .Case("fsubr", "fsubrp")
+      .Case("fdivr", "fdivrp");
+    static_cast<X86Operand &>(*Operands[0]).setTokenValue(Repl);
+  }
+
   // This is a terrible hack to handle "out[bwl]? %al, (%dx)" ->
   // "outb %al, %dx".  Out doesn't take a memory form, but this is a widely
   // documented form in various unofficial manuals, so a lot of code uses it.
   if ((Name == "outb" || Name == "outw" || Name == "outl" || Name == "out") &&
       Operands.size() == 3) {
     X86Operand &Op = (X86Operand &)*Operands.back();
     if (Op.isMem() && Op.Mem.SegReg == 0 &&
         isa<MCConstantExpr>(Op.Mem.Disp) &&

llvm/trunk/lib/Target/X86/X86InstrInfo.td

 def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>;
 def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>;
 
 
 
 // Various unary fpstack operations default to operating on on ST1.
 // For example, "fxch" -> "fxch %st(1)"
 def : InstAlias<"faddp",        (ADD_FPrST0  ST1), 0>;
+def:  InstAlias<"fadd",         (ADD_FPrST0  ST1), 0>;
 def : InstAlias<"fsub{|r}p",    (SUBR_FPrST0 ST1), 0>;
 def : InstAlias<"fsub{r|}p",    (SUB_FPrST0  ST1), 0>;
+def : InstAlias<"fmul",         (MUL_FPrST0  ST1), 0>;
 def : InstAlias<"fmulp",        (MUL_FPrST0  ST1), 0>;
 def : InstAlias<"fdiv{|r}p",    (DIVR_FPrST0 ST1), 0>;
 def : InstAlias<"fdiv{r|}p",    (DIV_FPrST0  ST1), 0>;
 def : InstAlias<"fxch",         (XCH_F       ST1), 0>;
 def : InstAlias<"fcom",         (COM_FST0r   ST1), 0>;
 def : InstAlias<"fcomp",        (COMP_FST0r  ST1), 0>;
 def : InstAlias<"fcomi",        (COM_FIr     ST1), 0>;
 def : InstAlias<"fcompi",       (COM_FIPr    ST1), 0>;

llvm/trunk/test/MC/X86/intel-syntax-2.s

 
 _test2:
 .intel_syntax noprefix
   mov DWORD PTR [RSP - 4], 255
 // CHECK: movl  $255, -4(%rsp)
 .att_syntax prefix
   movl $255, -4(%rsp)
 // CHECK: movl  $255, -4(%rsp)
+
+_test3:
+fadd 
+// CHECK: faddp %st(1)
+fmul
+// CHECK: fmulp %st(1)
+fsub
+// CHECK: fsubp %st(1)
+fsubr
+// CHECK: fsubrp %st(1)
+fdiv
+// CHECK: fdivp %st(1)
+fdivr
+// CHECK: fdivrp %st(1)

llvm/trunk/test/MC/X86/intel-syntax.s

 // CHECK: fdivp %st(1)
 faddp ST(1)
 fmulp ST(1)
 fsubp ST(1)
 fsubrp ST(1)
 fdivp ST(1)
 fdivrp ST(1)
 
+
+// CHECK: faddp %st(1)
+// CHECK: fmulp %st(1)
+// CHECK: fsubrp %st(1)
+// CHECK: fsubp %st(1)
+// CHECK: fdivrp %st(1)
+// CHECK: fdivp %st(1)
+fadd 
+fmul
+fsub
+fsubr
+fdiv
+fdivr
+
 // CHECK: faddp %st(1)
 // CHECK: fmulp %st(1)
 // CHECK: fsubrp %st(1)
 // CHECK: fsubp %st(1)
 // CHECK: fdivrp %st(1)
 // CHECK: fdivp %st(1)
 faddp
 fmulp