[1/4] SP and PC as shifted-reg operands are unpredictable in ARMv7 Thumb

[rengolin]

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

8534 ↗

(On Diff #38638)

} else if (...) {

8656 ↗

(On Diff #38638)

This seems an awfully specific error message to this generic error.

So far, the only use in for SP, but if someone re-uses it for something else, the error message will be completely bogus.

test/MC/ARM/thumb2-diagnostics.s

95 ↗

(On Diff #38638)

Also add a test for SP on ARMv8.

[tyomitch]

test/MC/ARM/thumb2-diagnostics.s

95 ↗

(On Diff #38638)

Actually, I'm adding such a test in http://reviews.llvm.org/D14142#inline-115599 -- the motivation being that this test file checks encodings invalid both in ARMv7 and in ARMv8, while test/MC/ARM/basic-thumb2-instructions-v8.s checks encodings invalid in ARMv7 but valid in ARMv8.

Should I move that hunk into this patch?

[rengolin]

test/MC/ARM/thumb2-diagnostics.s

95 ↗

(On Diff #38638)

I think all patches could be merged together. Now that I have reviewed them all separately, I realised that they are very much entangled.

[tyomitch]

The four patches updated and merged.

[rengolin]

Thanks! LGTM.

llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp

#include "ARMGenAsmMatcher.inc"
   bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
 
 public:
   enum ARMMatchResultTy {
     Match_RequiresITBlock = FIRST_TARGET_MATCH_RESULT_TY,
     Match_RequiresNotITBlock,
     Match_RequiresV6,
     Match_RequiresThumb2,
+    Match_RequiresV8,
 #define GET_OPERAND_DIAGNOSTIC_TYPES
 #include "ARMGenAsmMatcher.inc"
 
   };
 
   ARMAsmParser(MCSubtargetInfo &STI, MCAsmParser &Parser,
                const MCInstrInfo &MII, const MCTargetOptions &Options)
       : MCTargetAsmParser(Options), STI(STI), MII(MII), UC(Parser) {
if (MCID.TSFlags & ARMII::ThumbArithFlagSetting) {
     // If we're parsing Thumb2, which form is legal depends on whether we're
     // in an IT block.
     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() != ARM::CPSR &&
         !inITBlock())
       return Match_RequiresITBlock;
     if (isThumbTwo() && Inst.getOperand(OpNo).getReg() == ARM::CPSR &&
         inITBlock())
       return Match_RequiresNotITBlock;
-  }
+  } else if (isThumbOne()) {
     // Some high-register supporting Thumb1 encodings only allow both registers
     // to be from r0-r7 when in Thumb2.
-  else if (Opc == ARM::tADDhirr && isThumbOne() && !hasV6MOps() &&
-           isARMLowRegister(Inst.getOperand(1).getReg()) &&
-           isARMLowRegister(Inst.getOperand(2).getReg()))
+    if (Opc == ARM::tADDhirr && !hasV6MOps() &&
       return Match_RequiresThumb2;
     // Others only require ARMv6 or later.
-  else if (Opc == ARM::tMOVr && isThumbOne() && !hasV6Ops() &&
+    else if (Opc == ARM::tMOVr && !hasV6Ops() &&
              isARMLowRegister(Inst.getOperand(0).getReg()) &&
              isARMLowRegister(Inst.getOperand(1).getReg()))
       return Match_RequiresV6;
+  }
+
+  for (unsigned I = 0; I < MCID.NumOperands; ++I)
+    if (MCID.OpInfo[I].RegClass == ARM::rGPRRegClassID) {
+      // rGPRRegClass excludes PC, and also excluded SP before ARMv8
+      if ((Inst.getOperand(I).getReg() == ARM::SP) && !hasV8Ops())
+        return Match_RequiresV8;
+      else if (Inst.getOperand(I).getReg() == ARM::PC)
+        return Match_InvalidOperand;
+    }
+
   return Match_Success;
 }
 
 namespace llvm {
 template <> inline bool IsCPSRDead<MCInst>(MCInst *Instr) {
   return true; // In an assembly source, no need to second-guess
 }
 }
bool ARMAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_RequiresNotITBlock:
     return Error(IDLoc, "flag setting instruction only valid outside IT block");
   case Match_RequiresITBlock:
     return Error(IDLoc, "instruction only valid inside IT block");
   case Match_RequiresV6:
     return Error(IDLoc, "instruction variant requires ARMv6 or later");
   case Match_RequiresThumb2:
     return Error(IDLoc, "instruction variant requires Thumb2");
+  case Match_RequiresV8:
+    return Error(IDLoc, "instruction variant requires ARMv8 or later");
   case Match_ImmRange0_15: {
     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
     return Error(ErrorLoc, "immediate operand must be in the range [0,15]");
   }
   case Match_ImmRange0_239: {
     SMLoc ErrorLoc = ((ARMOperand &)*Operands[ErrorInfo]).getStartLoc();
     if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
if (Op.isImm()) {
       const MCExpr *SOExpr = Op.getImm();
       int64_t Value;
       if (!SOExpr->evaluateAsAbsolute(Value))
         return Match_Success;
       assert((Value >= INT32_MIN && Value <= UINT32_MAX) &&
              "expression value must be representable in 32 bits");
     }
     break;
+  case MCK_rGPR:
+    if (hasV8Ops() && Op.isReg() && Op.getReg() == ARM::SP)
+      return Match_Success;
+    break;
   case MCK_GPRPair:
     if (Op.isReg() &&
         MRI->getRegClass(ARM::GPRRegClassID).contains(Op.getReg()))
       return Match_Success;
     break;
   }
   return Match_InvalidOperand;
 }

llvm/trunk/lib/Target/ARM/Disassembler/ARMDisassembler.cpp

static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
 
   Inst.addOperand(MCOperand::createReg(Register));
   return MCDisassembler::Success;
 }
 
 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
                                    uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
-  if (RegNo == 13 || RegNo == 15)
+
+  const FeatureBitset &featureBits =
+    ((const MCDisassembler*)Decoder)->getSubtargetInfo().getFeatureBits();
+
+  if ((RegNo == 13 && !featureBits[ARM::HasV8Ops]) || RegNo == 15)
     S = MCDisassembler::SoftFail;
+
   Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
   return S;
 }
 
 static const uint16_t SPRDecoderTable[] = {
      ARM::S0,  ARM::S1,  ARM::S2,  ARM::S3,
      ARM::S4,  ARM::S5,  ARM::S6,  ARM::S7,
      ARM::S8,  ARM::S9, ARM::S10, ARM::S11,
static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
                                uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
   unsigned Rm = fieldFromInstruction(Val, 0, 4);
   unsigned type = fieldFromInstruction(Val, 5, 2);
   unsigned imm = fieldFromInstruction(Val, 7, 5);
 
   // Register-immediate
-  if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
+  if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
     return MCDisassembler::Fail;
 
   ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
   switch (type) {
     case 0:
       Shift = ARM_AM::lsl;
       break;
     case 1:

llvm/trunk/test/MC/ARM/basic-thumb2-instructions-v8.s

 @ New ARMv8 T32 encodings
 
 @ RUN: llvm-mc -triple thumbv8 -show-encoding < %s | FileCheck %s --check-prefix=CHECK-V8
 @ RUN: not llvm-mc -triple thumbv7 -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V7
 
-@ HLT
+@ HLT (in ARMv8 only)
         hlt  #0
         hlt  #63
 @ CHECK-V8: hlt  #0                       @ encoding: [0x80,0xba]
 @ CHECK-V8: hlt  #63                      @ encoding: [0xbf,0xba]
 @ CHECK-V7: error: instruction requires: armv8
 @ CHECK-V7: error: instruction requires: armv8
 
 @ In IT block
         it pl
         hlt #24
 
 @ CHECK-V8: it pl                         @ encoding: [0x58,0xbf]
 @ CHECK-V8: hlt #24                       @ encoding: [0x98,0xba]
 @ CHECK-V7: error: instruction requires: armv8
 
-@ Can accept AL condition code
+@ Can accept AL condition code (in ARMv8 only)
         hltal #24
 @ CHECK-V8: hlt #24                       @ encoding: [0x98,0xba]
 @ CHECK-V7: error: instruction requires: armv8
 
-@ DCPS{1,2,3}
+@ Can accept SP as rGPR (in ARMv8 only)
+        sbc.w r6, r3, sp, asr #16
+        and.w r6, r3, sp, asr #16
+        and sp, r0, #0
+@ CHECK-V8: sbc.w r6, r3, sp, asr #16     @ encoding: [0x63,0xeb,0x2d,0x46]
+@ CHECK-V8: and.w r6, r3, sp, asr #16     @ encoding: [0x03,0xea,0x2d,0x46]
+@ CHECK-V8: and   sp, r0, #0              @ encoding: [0x00,0xf0,0x00,0x0d]
+@ CHECK-V7: error: instruction variant requires ARMv8 or later
+@ CHECK-V7: error: instruction variant requires ARMv8 or later
+@ CHECK-V7: error: invalid operand for instruction
+
+@ DCPS{1,2,3} (in ARMv8 only)
         dcps1
         dcps2
         dcps3
 @ CHECK-V8: dcps1                         @ encoding: [0x8f,0xf7,0x01,0x80]
 @ CHECK-V8: dcps2                         @ encoding: [0x8f,0xf7,0x02,0x80]
 @ CHECK-V8: dcps3                         @ encoding: [0x8f,0xf7,0x03,0x80]
 @ CHECK-V7: error: instruction requires: armv8
 @ CHECK-V7: error: instruction requires: armv8
 @ CHECK-V7: error: instruction requires: armv8
 
 @------------------------------------------------------------------------------
-@ DMB (v8 barriers)
+@ DMB (ARMv8-only barriers)
 @------------------------------------------------------------------------------
         dmb ishld
         dmb oshld
         dmb nshld
         dmb ld
 
 @ CHECK-V8: dmb ishld @ encoding: [0xbf,0xf3,0x59,0x8f]
 @ CHECK-V8: dmb oshld @ encoding: [0xbf,0xf3,0x51,0x8f]
 @ CHECK-V8: dmb nshld @ encoding: [0xbf,0xf3,0x55,0x8f]
 @ CHECK-V8: dmb ld @ encoding: [0xbf,0xf3,0x5d,0x8f]
 @ CHECK-V7: error: invalid operand for instruction
 @ CHECK-V7: error: invalid operand for instruction
 @ CHECK-V7: error: invalid operand for instruction
 @ CHECK-V7: error: invalid operand for instruction
 
 @------------------------------------------------------------------------------
-@ DSB (v8 barriers)
+@ DSB (ARMv8-only barriers)
 @------------------------------------------------------------------------------
         dsb ishld
         dsb oshld
         dsb nshld
         dsb ld
 
 @ CHECK-V8: dsb ishld @ encoding: [0xbf,0xf3,0x49,0x8f]
 @ CHECK-V8: dsb oshld @ encoding: [0xbf,0xf3,0x41,0x8f]
 @ CHECK-V8: dsb nshld @ encoding: [0xbf,0xf3,0x45,0x8f]
 @ CHECK-V8: dsb ld @ encoding: [0xbf,0xf3,0x4d,0x8f]
 @ CHECK-V7: error: invalid operand for instruction
 @ CHECK-V7: error: invalid operand for instruction
 @ CHECK-V7: error: invalid operand for instruction
 @ CHECK-V7: error: invalid operand for instruction
 
 @------------------------------------------------------------------------------
-@ SEVL
+@ SEVL (in ARMv8 only)
 @------------------------------------------------------------------------------
         sevl
         sevl.w
         it ge
         sevlge
 
 @ CHECK-V8: sevl @ encoding: [0x50,0xbf]
 @ CHECK-V8: sevl.w @ encoding: [0xaf,0xf3,0x05,0x80]
 @ CHECK-V8: it ge @ encoding: [0xa8,0xbf]
 @ CHECK-V8: sevlge @ encoding: [0x50,0xbf]
 @ CHECK-V7: error: instruction requires: armv8
 @ CHECK-V7: error: instruction requires: armv8
 @ CHECK-V7: error:
 @ CHECK-V7: error: instruction requires: armv8

llvm/trunk/test/MC/ARM/diagnostics.s

 @ RUN: not llvm-mc -triple=armv7-apple-darwin < %s 2> %t
-@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V7 < %t %s
 @ RUN: not llvm-mc -triple=armv8 < %s 2> %t
-@ RUN: FileCheck --check-prefix=CHECK-ERRORS-V8 < %t %s
+@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V8 < %t %s
 
 @ Check for various assembly diagnostic messages on invalid input.
 
 @ 's' bit on an instruction that can't accept it.
         mlss r1, r2, r3, r4
 @ CHECK-ERRORS: error: instruction 'mls' can not set flags,
 @ CHECK-ERRORS: but 's' suffix specified
 
@ CHECK-ERRORS:         pld r4, [r5, r6, rrx #0]
         @ Out of range 16-bit immediate on BKPT
         bkpt #65536
 
 @ CHECK-ERRORS: error: invalid operand for instruction
 
         @ Out of range immediates for v8 HLT instruction.
         hlt #65536
         hlt #-1
-@CHECK-ERRORS-V8: error: invalid operand for instruction
-@CHECK-ERRORS-V8:         hlt #65536
-@CHECK-ERRORS-V8:              ^
-@CHECK-ERRORS-V8: error: invalid operand for instruction
-@CHECK-ERRORS-V8:         hlt #-1
-@CHECK-ERRORS-V8:              ^
+@CHECK-ERRORS: error: invalid operand for instruction
+@CHECK-ERRORS:         hlt #65536
+@CHECK-ERRORS:              ^
+@CHECK-ERRORS: error: invalid operand for instruction
+@CHECK-ERRORS:         hlt #-1
+@CHECK-ERRORS:              ^
 
         @ Illegal condition code for v8 HLT instruction.
         hlteq #2
         hltlt #23
-@CHECK-ERRORS-V8: error: instruction 'hlt' is not predicable, but condition code specified
-@CHECK-ERRORS-V8:        hlteq #2
-@CHECK-ERRORS-V8:        ^
-@CHECK-ERRORS-V8: error: instruction 'hlt' is not predicable, but condition code specified
-@CHECK-ERRORS-V8:        hltlt #23
-@CHECK-ERRORS-V8:        ^
+@CHECK-ERRORS: error: instruction 'hlt' is not predicable, but condition code specified
+@CHECK-ERRORS:        hlteq #2
+@CHECK-ERRORS:        ^
+@CHECK-ERRORS: error: instruction 'hlt' is not predicable, but condition code specified
+@CHECK-ERRORS:        hltlt #23
+@CHECK-ERRORS:        ^
 
         @ Out of range 4 and 3 bit immediates on CDP[2]
 
         @ Out of range immediates for CDP/CDP2
         cdp  p7, #2, c1, c1, c1, #8
         cdp  p7, #1, c1, c1, c1, #8
         cdp2  p7, #2, c1, c1, c1, #8
         cdp2  p7, #1, c1, c1, c1, #8
@ CHECK-ERRORS: dbg #16
         mcr2  p7, #1, r5, c1, c1, #8
         mcrr  p7, #16, r5, r4, c1
         mcrr2  p7, #16, r5, r4, c1
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
-@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
+@ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15]
+@ CHECK-ERRORS-V8: error: invalid operand for instruction
 
         @ p10 and p11 are reserved for NEON
         mcr p10, #2, r5, c1, c1, #4
         mcrr p11, #8, r5, r4, c1
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: invalid operand for instruction
 
         @ Out of range immediate for MOV
@ CHECK-ERRORS: error: invalid operand for instruction
         mrc2  p14, #0, r1, c1, c2, #9
         mrrc  p7, #16, r5, r4, c1
         mrrc2  p7, #17, r5, r4, c1
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
-@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
+@ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15]
+@ CHECK-ERRORS-V8: error: invalid operand for instruction
 
         @ Shifter operand validation for PKH instructions.
         pkhbt r2, r2, r3, lsl #-1
         pkhbt r2, r2, r3, lsl #32
         pkhtb r2, r2, r3, asr #0
         pkhtb r2, r2, r3, asr #33
         pkhbt r2, r2, r3, asr #3
         pkhtb r2, r2, r3, lsl #3

 @ CHECK-ERRORS: error: non-contiguous register range
 @ CHECK-ERRORS:         vpush {s0, s3}
 @ CHECK-ERRORS:                    ^
 
         @ Out of range coprocessor option immediate.
         ldc2 p2, c8, [r1], { 256 }
         ldc2 p2, c8, [r1], { -1 }
 
-@ CHECK-ERRORS: error: coprocessor option must be an immediate in range [0, 255]
-@ CHECK-ERRORS:         ldc2 p2, c8, [r1], { 256 }
-@ CHECK-ERRORS:                              ^
-@ CHECK-ERRORS: error: coprocessor option must be an immediate in range [0, 255]
-@ CHECK-ERRORS:         ldc2 p2, c8, [r1], { -1 }
-@ CHECK-ERRORS:                              ^
+@ CHECK-ERRORS-V7: error: coprocessor option must be an immediate in range [0, 255]
+@ CHECK-ERRORS-V7:         ldc2 p2, c8, [r1], { 256 }
+@ CHECK-ERRORS-V7:                              ^
+@ CHECK-ERRORS-V8: error: register expected
+@ CHECK-ERRORS-V7: error: coprocessor option must be an immediate in range [0, 255]
+@ CHECK-ERRORS-V7:         ldc2 p2, c8, [r1], { -1 }
+@ CHECK-ERRORS-V7:                              ^
+@ CHECK-ERRORS-V8: error: register expected
 
         @ Bad CPS instruction format.
         cps f,#1
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS:         cps f,#1
 @ CHECK-ERRORS:               ^
 
         @ Bad operands for msr
@ CHECK-ERRORS: error: writeback register not allowed in register list
         vrintz.f32.f32 s0, s1
         vrintr.f32 s0, s1
         vrintx.f64.f64 d2, d5
         vrintz.f64 d10, d9
         vrinta.f32.f32 s6, s7
         vrintn.f32 s8, s9
         vrintp.f64.f64 d10, d11
         vrintm.f64 d12, d13
-@ CHECK-ERRORS: error: instruction requires: FPARMv8
-@ CHECK-ERRORS: error: instruction requires: FPARMv8
-@ CHECK-ERRORS: error: instruction requires: FPARMv8
-@ CHECK-ERRORS: error: instruction requires: FPARMv8
-@ CHECK-ERRORS: error: instruction requires: FPARMv8
-@ CHECK-ERRORS: error: instruction requires: FPARMv8
-@ CHECK-ERRORS: error: instruction requires: FPARMv8
-@ CHECK-ERRORS: error: instruction requires: FPARMv8
+@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
+@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
+@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
+@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
+@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
+@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
+@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
+@ CHECK-ERRORS-V7: error: instruction requires: FPARMv8
 
         stm sp!, {r0, pc}^
         ldm sp!, {r0}^
 @ CHECK-ERRORS: error: system STM cannot have writeback register
 @ CHECK-ERRORS: error: writeback register only allowed on system LDM if PC in register-list
 
 foo2:
         mov r0, foo2

llvm/trunk/test/MC/ARM/thumb-shift-encoding.s

 @ RUN: llvm-mc -mcpu=cortex-a8 -triple thumbv7 -show-encoding < %s | FileCheck %s
 
 @ Uses printT2SOOperand(), used by t2ADCrs t2ADDrs t2ANDrs t2BICrs t2EORrs
 @ t2ORNrs t2ORRrs t2RSBrs t2SBCrs t2SUBrs t2CMNzrs t2CMPrs t2MOVSsi t2MOVsi
 @ t2MVNs t2TEQrs t2TSTrs
 
   sbc.w r12, lr, r0
   sbc.w r1, r8, r9, lsr #32
-  sbc.w r2, r7, pc, lsr #16
+  sbc.w r2, r7, r10, lsr #16
   sbc.w r3, r6, r10, lsl #0
   sbc.w r4, r5, lr, lsl #16
   sbc.w r5, r4, r11, asr #32
-  sbc.w r6, r3, sp, asr #16
+  sbc.w r6, r3, r12, asr #16
   sbc.w r7, r2, r12, rrx
   sbc.w r8, r1, r0, ror #16
 
 @ CHECK: sbc.w r12, lr, r0          @ encoding: [0x6e,0xeb,0x00,0x0c]
 @ CHECK: sbc.w r1, r8, r9, lsr #32  @ encoding: [0x68,0xeb,0x19,0x01]
-@ CHECK: sbc.w r2, r7, pc, lsr #16  @ encoding: [0x67,0xeb,0x1f,0x42]
+@ CHECK: sbc.w r2, r7, r10, lsr #16 @ encoding: [0x67,0xeb,0x1a,0x42]
 @ CHECK: sbc.w r3, r6, r10          @ encoding: [0x66,0xeb,0x0a,0x03]
 @ CHECK: sbc.w r4, r5, lr, lsl #16  @ encoding: [0x65,0xeb,0x0e,0x44]
 @ CHECK: sbc.w r5, r4, r11, asr #32 @ encoding: [0x64,0xeb,0x2b,0x05]
-@ CHECK: sbc.w r6, r3, sp, asr #16  @ encoding: [0x63,0xeb,0x2d,0x46]
+@ CHECK: sbc.w r6, r3, r12, asr #16 @ encoding: [0x63,0xeb,0x2c,0x46]
 @ CHECK: sbc.w r7, r2, r12, rrx     @ encoding: [0x62,0xeb,0x3c,0x07]
 @ CHECK: sbc.w r8, r1, r0, ror #16  @ encoding: [0x61,0xeb,0x30,0x48]
 
   and.w r12, lr, r0
   and.w r1, r8, r9, lsr #32
-  and.w r2, r7, pc, lsr #16
+  and.w r2, r7, r10, lsr #16
   and.w r3, r6, r10, lsl #0
   and.w r4, r5, lr, lsl #16
   and.w r5, r4, r11, asr #32
-  and.w r6, r3, sp, asr #16
+  and.w r6, r3, r12, asr #16
   and.w r7, r2, r12, rrx
   and.w r8, r1, r0, ror #16
 
 @ CHECK: and.w r12, lr, r0          @ encoding: [0x0e,0xea,0x00,0x0c]
 @ CHECK: and.w r1, r8, r9, lsr #32  @ encoding: [0x08,0xea,0x19,0x01]
-@ CHECK: and.w r2, r7, pc, lsr #16  @ encoding: [0x07,0xea,0x1f,0x42]
+@ CHECK: and.w r2, r7, r10, lsr #16 @ encoding: [0x07,0xea,0x1a,0x42]
 @ CHECK: and.w r3, r6, r10          @ encoding: [0x06,0xea,0x0a,0x03]
 @ CHECK: and.w r4, r5, lr, lsl #16  @ encoding: [0x05,0xea,0x0e,0x44]
 @ CHECK: and.w r5, r4, r11, asr #32 @ encoding: [0x04,0xea,0x2b,0x05]
-@ CHECK: and.w r6, r3, sp, asr #16  @ encoding: [0x03,0xea,0x2d,0x46]
+@ CHECK: and.w r6, r3, r12, asr #16 @ encoding: [0x03,0xea,0x2c,0x46]
 @ CHECK: and.w r7, r2, r12, rrx     @ encoding: [0x02,0xea,0x3c,0x07]
 @ CHECK: and.w r8, r1, r0, ror #16  @ encoding: [0x01,0xea,0x30,0x48]

llvm/trunk/test/MC/ARM/thumb2-diagnostics.s

 @ RUN: not llvm-mc -triple=thumbv7-apple-darwin < %s 2> %t
-@ RUN: FileCheck --check-prefix=CHECK-ERRORS < %t %s
+@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V7 < %t %s
+
+@ RUN: not llvm-mc -triple=thumbv8-apple-darwin < %s 2> %t
+@ RUN: FileCheck --check-prefix=CHECK-ERRORS --check-prefix=CHECK-ERRORS-V8 < %t %s
 
 @ Ill-formed IT block instructions.
         itet eq
         addle r0, r1, r2
         nop
         it le
         iteeee gt
         ittfe le
@ CHECK-ERRORS:         ^
         mrc2  p14, #0, r1, c1, c2, #9
         mrrc  p7, #16, r5, r4, c1
         mrrc2  p7, #17, r5, r4, c1
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
-@ CHECK-ERRORS: error: immediate operand must be in the range [0,15]
+@ CHECK-ERRORS-V7: error: immediate operand must be in the range [0,15]
+@ CHECK-ERRORS-V8: error: invalid operand for instruction
 
         isb  #-1
         isb  #16
 @ CHECK-ERRORS: error: immediate value out of range
 @ CHECK-ERRORS: error: immediate value out of range
 
         itt eq
         bkpteq #1

 @ CHECK-ERRORS: error: immediate expression for mov requires :lower16: or :upper16
 @ CHECK-ERRORS:                  ^
 
         and sp, r1, #80008000
         and pc, r1, #80008000
 @ CHECK-ERRORS: error: invalid operand for instruction
 @ CHECK-ERRORS: error: invalid operand for instruction
 
         ssat r0, #1, r0, asr #32
         usat r0, #1, r0, asr #32
 @ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode
 @ CHECK-ERRORS: error: 'asr #32' shift amount not allowed in Thumb mode
+
+        @ PC is not valid as shifted-rGPR
+        sbc.w r2, r7, pc, lsr #16
+        and.w r2, r7, pc, lsr #16
+@ CHECK-ERRORS: error: invalid operand for instruction
+@ CHECK-ERRORS: error: invalid operand for instruction
+

llvm/trunk/test/MC/Disassembler/ARM/invalid-thumbv7.txt

-# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s
+# RUN: not llvm-mc -disassemble %s -mcpu cortex-a8 -triple thumbv7 2>&1 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-V7
+# RUN: not llvm-mc -disassemble %s -mcpu cortex-a53 -triple thumbv8 2>&1 | FileCheck %s
 
 # This file is checking Thumbv7 encodings which are globally invalid, usually due
 # to the constraints of the instructions not being met. For example invalid
 # combinations of registers.
 
 #------------------------------------------------------------------------------
 # Undefined encoding for b.cc
 #------------------------------------------------------------------------------

 
 #------------------------------------------------------------------------------
 # Unpredictable STMs
 #------------------------------------------------------------------------------
 
 # 32-bit Thumb STM instructions cannot have a writeback register which appears
 # in the list.
 
-[0xa1,0xe8,0x07,0x04]
+[0xa1 0xe8 0x07 0x04]
 # CHECK: warning: potentially undefined instruction encoding
-# CHECK-NEXT: [0xa1,0xe8,0x07,0x04]
+# CHECK-NEXT: [0xa1 0xe8 0x07 0x04]
 
-[0x21,0xe9,0x07,0x04]
+[0x21 0xe9 0x07 0x04]
 # CHECK: warning: potentially undefined instruction encoding
-# CHECK-NEXT: [0x21,0xe9,0x07,0x04]
+# CHECK-NEXT: [0x21 0xe9 0x07 0x04]
+
+#------------------------------------------------------------------------------
+# SP is invalid as rGPR before ARMv8
+#------------------------------------------------------------------------------
+
+[0x00 0xf0 0x00 0x0d]
+# CHECK-V7: warning: potentially undefined instruction encoding
+# CHECK-V7-NEXT: [0x00 0xf0 0x00 0x0d]
+
+[0x63 0xeb 0x2d 0x46]
+# CHECK-V7: warning: potentially undefined instruction encoding
+# CHECK-V7-NEXT: [0x63 0xeb 0x2d 0x46]

llvm/trunk/test/MC/Disassembler/ARM/thumb-v8.txt

-# RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+db -show-encoding < %s | FileCheck %s
+# RUN: llvm-mc -disassemble -triple thumbv8 -mattr=+db -show-encoding 2>%t < %s | FileCheck %s
+# RUN: FileCheck -allow-empty -check-prefix=STDERR < %t %s
 
 0x80 0xba
 # CHECK: hlt #0
 
 0xbf 0xba
 # CHECK: hlt #63
 
 # DCPS{1,2,3}

 0xbf 0xf3 0x51 0x8f
 0xbf 0xf3 0x55 0x8f
 0xbf 0xf3 0x5d 0x8f
 
 # CHECK: dmb ishld
 # CHECK: dmb oshld
 # CHECK: dmb nshld
 # CHECK: dmb ld
+
+[0x00 0xf0 0x00 0x0d]
+[0x63 0xeb 0x2d 0x46]
+# CHECK: and sp, r0, #0
+# CHECK: sbc.w r6, r3, sp, asr #16
+
+# STDERR-NOT: warning