[mips][microMIPS] Implement DPS.W.PH, DPSQ_S.W.PH, DPSQ_SA.L.W, DPSQX_S.W.PH, DPSQX_SA.W.PH, DPSU.H.QBL, DPSU.H.QBR and DPSX.W.PH instructions

[hvarga]

Summary

The patch implements microMIPSDSP instructions: DPS.W.PH, DPSQ_S.W.PH, DPSQ_SA.L.W, DPSQX_S.W.PH, DPSQX_SA.W.PH, DPSU.H.QBL, DPSU.H.QBR and DPSX.W.PH.

[hvarga]

Moved DPSU_H_QBL_MM and DPSU_H_QBR_MM to correct group.

[dsanders]

LGTM with a small tweak to the tests.

By the way, I recently discovered that we have no DSPr1 tests for the standard encodings. Given that you are adding tests for microMIPS DSPr1, would you be willing to add standard encoding tests too?

test/MC/Disassembler/Mips/micromips-dspr2/valid.txt

18–21 ↗

(On Diff #38381)

The DSPr2 test file should also contain DSPr1 tests. The intent is that you can diff the two files and the differences are just the instructions that were added in DSPr2. It also serves as a check that the predicates are correct.

Likewise for the assembler tests.

[hvarga]

In D14058#289511, @dsanders wrote:

LGTM with a small tweak to the tests.

By the way, I recently discovered that we have no DSPr1 tests for the standard encodings. Given that you are adding tests for microMIPS DSPr1, would you be willing to add standard encoding tests too?

I discussed this with Zoran and we agreed that can be a separated task.

[dsanders]

I discussed this with Zoran and we agreed that can be a separated task.

Thanks

llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td

 class EXTR_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr.w", 0b00111001>;
 class EXTR_R_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_r.w", 0b01111001>;
 class EXTR_RS_W_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_rs.w", 0b10111001>;
 class EXTR_S_H_MM_ENC : POOL32A_1RIMM5AC_FMT<"extr_s.h", 0b11111001>;
 class EXTRV_W_MM_ENC : POOL32A_2RAC_FMT<"extrv.w", 0b00111010>;
 class EXTRV_R_W_MM_ENC : POOL32A_2RAC_FMT<"extrv_r.w", 0b01111010>;
 class EXTRV_RS_W_MM_ENC : POOL32A_2RAC_FMT<"extrv_rs.w", 0b10111010>;
 class EXTRV_S_H_MM_ENC : POOL32A_2RAC_FMT<"extrv_s.h", 0b11111010>;
+class DPS_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dps.w.ph", 0b00010010>;
+class DPSQ_S_W_PH_MM_ENC : POOL32A_2RAC_FMT<"dpsq_s.w.ph", 0b00011010>;
+class DPSQ_SA_L_W_MM_ENC : POOL32A_2RAC_FMT<"dpsq_sa.l.w", 0b01011010>;
+class DPSQX_S_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsqx_s.w.ph", 0b10011010>;
+class DPSQX_SA_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsqx_sa.w.ph", 0b11011010>;
+class DPSU_H_QBL_MM_ENC : POOL32A_2RAC_FMT<"dpsu.h.qbl", 0b10010010>;
+class DPSU_H_QBR_MM_ENC : POOL32A_2RAC_FMT<"dpsu.h.qbr", 0b11010010>;
+class DPSX_W_PH_MMR2_ENC : POOL32A_2RAC_FMT<"dpsx.w.ph", 0b01010010>;
 
 // Instruction desc.
 class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
                                 InstrItinClass itin, RegisterOperand ROD,
                                 RegisterOperand ROS = ROD> {
   dag OutOperandList = (outs ROD:$rt);
   dag InOperandList = (ins ROS:$rs);
   string AsmString = !strconcat(opstr, "\t$rt, $rs");

 def EXTR_W_MM : DspMMRel, EXTR_W_MM_ENC, EXTR_W_MM_DESC;
 def EXTR_R_W_MM : DspMMRel, EXTR_R_W_MM_ENC, EXTR_R_W_MM_DESC;
 def EXTR_RS_W_MM : DspMMRel, EXTR_RS_W_MM_ENC, EXTR_RS_W_MM_DESC;
 def EXTR_S_H_MM : DspMMRel, EXTR_S_H_MM_ENC, EXTR_S_H_MM_DESC;
 def EXTRV_W_MM : DspMMRel, EXTRV_W_MM_ENC, EXTRV_W_MM_DESC;
 def EXTRV_R_W_MM : DspMMRel, EXTRV_R_W_MM_ENC, EXTRV_R_W_MM_DESC;
 def EXTRV_RS_W_MM : DspMMRel, EXTRV_RS_W_MM_ENC, EXTRV_RS_W_MM_DESC;
 def EXTRV_S_H_MM : DspMMRel, EXTRV_S_H_MM_ENC, EXTRV_S_H_MM_DESC;
+def DPSQ_S_W_PH_MM : DspMMRel, DPSQ_S_W_PH_MM_ENC, DPSQ_S_W_PH_DESC;
+def DPSQ_SA_L_W_MM : DspMMRel, DPSQ_SA_L_W_MM_ENC, DPSQ_SA_L_W_DESC;
+def DPSU_H_QBL_MM : DspMMRel, DPSU_H_QBL_MM_ENC, DPSU_H_QBL_DESC;
+def DPSU_H_QBR_MM : DspMMRel, DPSU_H_QBR_MM_ENC, DPSU_H_QBR_DESC;
 // microMIPS DSP Rev 2
 def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
                      ISA_DSPR2;
 def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2;
 def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
 def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2;
 def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
 def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2;

 def SUBQH_PH_MMR2 : DspMMRel, SUBQH_PH_MMR2_ENC, SUBQH_PH_DESC, ISA_DSPR2;
 def SUBQH_R_PH_MMR2 : DspMMRel, SUBQH_R_PH_MMR2_ENC, SUBQH_R_PH_DESC, ISA_DSPR2;
 def SUBQH_W_MMR2 : DspMMRel, SUBQH_W_MMR2_ENC, SUBQH_W_DESC, ISA_DSPR2;
 def SUBQH_R_W_MMR2 : DspMMRel, SUBQH_R_W_MMR2_ENC, SUBQH_R_W_DESC, ISA_DSPR2;
 def SUBU_PH_MMR2 : DspMMRel, SUBU_PH_MMR2_ENC, SUBU_PH_DESC, ISA_DSPR2;
 def SUBU_S_PH_MMR2 : DspMMRel, SUBU_S_PH_MMR2_ENC, SUBU_S_PH_DESC, ISA_DSPR2;
 def SUBUH_QB_MMR2 : DspMMRel, SUBUH_QB_MMR2_ENC, SUBUH_QB_DESC, ISA_DSPR2;
 def SUBUH_R_QB_MMR2 : DspMMRel, SUBUH_R_QB_MMR2_ENC, SUBUH_R_QB_DESC, ISA_DSPR2;
+def DPS_W_PH_MMR2 : DspMMRel, DPS_W_PH_MMR2_ENC, DPS_W_PH_DESC, ISA_DSPR2;
+def DPSQX_S_W_PH_MMR2 : DspMMRel, DPSQX_S_W_PH_MMR2_ENC, DPSQX_S_W_PH_DESC,
+                        ISA_DSPR2;
+def DPSQX_SA_W_PH_MMR2 : DspMMRel, DPSQX_SA_W_PH_MMR2_ENC, DPSQX_SA_W_PH_DESC,
+                         ISA_DSPR2;
+def DPSX_W_PH_MMR2 : DspMMRel, DPSX_W_PH_MMR2_ENC, DPSX_W_PH_DESC, ISA_DSPR2;

llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td

 def MAQ_SA_W_PHL : MAQ_SA_W_PHL_ENC, MAQ_SA_W_PHL_DESC;
 def MAQ_SA_W_PHR : MAQ_SA_W_PHR_ENC, MAQ_SA_W_PHR_DESC;
 def MFHI_DSP : MFHI_ENC, MFHI_DESC;
 def MFLO_DSP : MFLO_ENC, MFLO_DESC;
 def MTHI_DSP : MTHI_ENC, MTHI_DESC;
 def MTLO_DSP : MTLO_ENC, MTLO_DESC;
 def DPAU_H_QBL : DspMMRel, DPAU_H_QBL_ENC, DPAU_H_QBL_DESC;
 def DPAU_H_QBR : DspMMRel, DPAU_H_QBR_ENC, DPAU_H_QBR_DESC;
-def DPSU_H_QBL : DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
-def DPSU_H_QBR : DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
+def DPSU_H_QBL : DspMMRel, DPSU_H_QBL_ENC, DPSU_H_QBL_DESC;
+def DPSU_H_QBR : DspMMRel, DPSU_H_QBR_ENC, DPSU_H_QBR_DESC;
 def DPAQ_S_W_PH : DspMMRel, DPAQ_S_W_PH_ENC, DPAQ_S_W_PH_DESC;
-def DPSQ_S_W_PH : DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
+def DPSQ_S_W_PH : DspMMRel, DPSQ_S_W_PH_ENC, DPSQ_S_W_PH_DESC;
 def DPAQ_SA_L_W : DspMMRel, DPAQ_SA_L_W_ENC, DPAQ_SA_L_W_DESC;
-def DPSQ_SA_L_W : DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
+def DPSQ_SA_L_W : DspMMRel, DPSQ_SA_L_W_ENC, DPSQ_SA_L_W_DESC;
 def MULT_DSP : DspMMRel, MULT_DSP_ENC, MULT_DSP_DESC;
 def MULTU_DSP : DspMMRel, MULTU_DSP_ENC, MULTU_DSP_DESC;
 def MADD_DSP : DspMMRel, MADD_DSP_ENC, MADD_DSP_DESC;
 def MADDU_DSP : DspMMRel, MADDU_DSP_ENC, MADDU_DSP_DESC;
 def MSUB_DSP : DspMMRel, MSUB_DSP_ENC, MSUB_DSP_DESC;
 def MSUBU_DSP : DspMMRel, MSUBU_DSP_ENC, MSUBU_DSP_DESC;
 def CMPU_EQ_QB : CMPU_EQ_QB_ENC, CMPU_EQ_QB_DESC;
 def CMPU_LT_QB : CMPU_LT_QB_ENC, CMPU_LT_QB_DESC;

 def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC;
 def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC;
 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
 def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
 def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC;
-def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
+def DPS_W_PH : DspMMRel, DPS_W_PH_ENC, DPS_W_PH_DESC;
 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;
 def DPAQX_SA_W_PH : DspMMRel, DPAQX_SA_W_PH_ENC, DPAQX_SA_W_PH_DESC;
 def DPAX_W_PH : DspMMRel, DPAX_W_PH_ENC, DPAX_W_PH_DESC;
-def DPSX_W_PH : DPSX_W_PH_ENC, DPSX_W_PH_DESC;
-def DPSQX_S_W_PH : DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
-def DPSQX_SA_W_PH : DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
+def DPSX_W_PH : DspMMRel, DPSX_W_PH_ENC, DPSX_W_PH_DESC;
+def DPSQX_S_W_PH : DspMMRel, DPSQX_S_W_PH_ENC, DPSQX_S_W_PH_DESC;
+def DPSQX_SA_W_PH : DspMMRel, DPSQX_SA_W_PH_ENC, DPSQX_SA_W_PH_DESC;
 def MULSA_W_PH : MULSA_W_PH_ENC, MULSA_W_PH_DESC;
 def PRECR_QB_PH : PRECR_QB_PH_ENC, PRECR_QB_PH_DESC;
 def PRECR_SRA_PH_W : PRECR_SRA_PH_W_ENC, PRECR_SRA_PH_W_DESC;
 def PRECR_SRA_R_PH_W : PRECR_SRA_R_PH_W_ENC, PRECR_SRA_R_PH_W_DESC;
 def SHRA_QB : DspMMRel, SHRA_QB_ENC, SHRA_QB_DESC;
 def SHRAV_QB : DspMMRel, SHRAV_QB_ENC, SHRAV_QB_DESC;
 def SHRA_R_QB : DspMMRel, SHRA_R_QB_ENC, SHRA_R_QB_DESC;
 def SHRAV_R_QB : DspMMRel, SHRAV_R_QB_ENC, SHRAV_R_QB_DESC;

llvm/trunk/test/MC/Disassembler/Mips/micromips-dsp/valid.txt

 0x00 0x64 0x2a 0xf5 # CHECK: shra_r.w $3, $4, 5
 0x00 0x64 0xb8 0x7c # CHECK: shrl.qb $3, $4, 5
 0x00 0x85 0x1b 0x55 # CHECK: shrlv.qb $3, $4, $5
 0x00 0xa4 0x1a 0x0d # CHECK: subq.ph $3, $4, $5
 0x00 0xa4 0x1e 0x0d # CHECK: subq_s.ph $3, $4, $5
 0x00 0xa4 0x1b 0x45 # CHECK: subq_s.w $3, $4, $5
 0x00 0xa4 0x1a 0xcd # CHECK: subu.qb $3, $4, $5
 0x00 0xa4 0x1e 0xcd # CHECK: subu_s.qb $3, $4, $5
+0x00 0xc4 0x46 0xbc # CHECK: dpsq_s.w.ph $ac1, $4, $6
+0x00 0xc4 0x56 0xbc # CHECK: dpsq_sa.l.w $ac1, $4, $6
+0x00 0xc4 0x64 0xbc # CHECK: dpsu.h.qbl $ac1, $4, $6
+0x00 0xc4 0x74 0xbc # CHECK: dpsu.h.qbr $ac1, $4, $6

llvm/trunk/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt

 0x00 0xa4 0x1a 0x8d # CHECK: subqh.w $3, $4, $5
 0x00 0xa4 0x1e 0x8d # CHECK: subqh_r.w $3, $4, $5
 0x00 0xa4 0x1b 0x0d # CHECK: subu.ph $3, $4, $5
 0x00 0xa4 0x1f 0x0d # CHECK: subu_s.ph $3, $4, $5
 0x00 0xa4 0x1a 0xcd # CHECK: subu.qb $3, $4, $5
 0x00 0xa4 0x1e 0xcd # CHECK: subu_s.qb $3, $4, $5
 0x00 0xa4 0x1b 0x4d # CHECK: subuh.qb $3, $4, $5
 0x00 0xa4 0x1f 0x4d # CHECK: subuh_r.qb $3, $4, $5
+0x00 0xc4 0x46 0xbc # CHECK: dpsq_s.w.ph $ac1, $4, $6
+0x00 0xc4 0x56 0xbc # CHECK: dpsq_sa.l.w $ac1, $4, $6
+0x00 0xc4 0x64 0xbc # CHECK: dpsu.h.qbl $ac1, $4, $6
+0x00 0xc4 0x74 0xbc # CHECK: dpsu.h.qbr $ac1, $4, $6
+0x00 0xc4 0x44 0xbc # CHECK: dps.w.ph $ac1, $4, $6
+0x00 0xc4 0x66 0xbc # CHECK: dpsqx_s.w.ph $ac1, $4, $6
+0x00 0xc4 0x76 0xbc # CHECK: dpsqx_sa.w.ph $ac1, $4, $6
+0x00 0xc4 0x54 0xbc # CHECK: dpsx.w.ph $ac1, $4, $6

llvm/trunk/test/MC/Mips/micromips-dsp/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
   shra_r.w $3, $4, 5           # CHECK: shra_r.w $3, $4, 5      # encoding: [0x00,0x64,0x2a,0xf5]
   shrl.qb $3, $4, 5            # CHECK: shrl.qb $3, $4, 5       # encoding: [0x00,0x64,0xb8,0x7c]
   shrlv.qb $3, $4, $5          # CHECK: shrlv.qb $3, $4, $5     # encoding: [0x00,0x85,0x1b,0x55]
   subq.ph $3, $4, $5           # CHECK: subq.ph $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0x0d]
   subq_s.ph $3, $4, $5         # CHECK: subq_s.ph $3, $4, $5    # encoding: [0x00,0xa4,0x1e,0x0d]
   subq_s.w $3, $4, $5          # CHECK: subq_s.w $3, $4, $5     # encoding: [0x00,0xa4,0x1b,0x45]
   subu.qb $3, $4, $5           # CHECK: subu.qb $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0xcd]
   subu_s.qb $3, $4, $5         # CHECK: subu_s.qb $3, $4, $5    # encoding: [0x00,0xa4,0x1e,0xcd]
+  dpsq_s.w.ph $ac1, $4, $6     # CHECK: dpsq_s.w.ph $ac1, $4, $6   # encoding: [0x00,0xc4,0x46,0xbc]
+  dpsq_sa.l.w $ac1, $4, $6     # CHECK: dpsq_sa.l.w $ac1, $4, $6   # encoding: [0x00,0xc4,0x56,0xbc]
+  dpsu.h.qbl $ac1, $4, $6      # CHECK: dpsu.h.qbl $ac1, $4, $6    # encoding: [0x00,0xc4,0x64,0xbc]
+  dpsu.h.qbr $ac1, $4, $6      # CHECK: dpsu.h.qbr $ac1, $4, $6    # encoding: [0x00,0xc4,0x74,0xbc]

llvm/trunk/test/MC/Mips/micromips-dspr2/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
   subqh.w $3, $4, $5           # CHECK: subqh.w $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0x8d]
   subqh_r.w $3, $4, $5         # CHECK: subqh_r.w $3, $4, $5    # encoding: [0x00,0xa4,0x1e,0x8d]
   subu.ph $3, $4, $5           # CHECK: subu.ph $3, $4, $5      # encoding: [0x00,0xa4,0x1b,0x0d]
   subu_s.ph $3, $4, $5         # CHECK: subu_s.ph $3, $4, $5    # encoding: [0x00,0xa4,0x1f,0x0d]
   subu.qb $3, $4, $5           # CHECK: subu.qb $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0xcd]
   subu_s.qb $3, $4, $5         # CHECK: subu_s.qb $3, $4, $5    # encoding: [0x00,0xa4,0x1e,0xcd]
   subuh.qb $3, $4, $5          # CHECK: subuh.qb $3, $4, $5     # encoding: [0x00,0xa4,0x1b,0x4d]
   subuh_r.qb $3, $4, $5        # CHECK: subuh_r.qb $3, $4, $5   # encoding: [0x00,0xa4,0x1f,0x4d]
+  dpsq_s.w.ph $ac1, $4, $6     # CHECK: dpsq_s.w.ph $ac1, $4, $6   # encoding: [0x00,0xc4,0x46,0xbc]
+  dpsq_sa.l.w $ac1, $4, $6     # CHECK: dpsq_sa.l.w $ac1, $4, $6   # encoding: [0x00,0xc4,0x56,0xbc]
+  dpsu.h.qbl $ac1, $4, $6      # CHECK: dpsu.h.qbl $ac1, $4, $6    # encoding: [0x00,0xc4,0x64,0xbc]
+  dpsu.h.qbr $ac1, $4, $6      # CHECK: dpsu.h.qbr $ac1, $4, $6    # encoding: [0x00,0xc4,0x74,0xbc]
+  dps.w.ph $ac1, $4, $6        # CHECK: dps.w.ph $ac1, $4, $6      # encoding: [0x00,0xc4,0x44,0xbc]
+  dpsqx_s.w.ph $ac1, $4, $6    # CHECK: dpsqx_s.w.ph $ac1, $4, $6  # encoding: [0x00,0xc4,0x66,0xbc]
+  dpsqx_sa.w.ph $ac1, $4, $6   # CHECK: dpsqx_sa.w.ph $ac1, $4, $6 # encoding: [0x00,0xc4,0x76,0xbc]
+  dpsx.w.ph $ac1, $4, $6       # CHECK: dpsx.w.ph $ac1, $4, $6     # encoding: [0x00,0xc4,0x54,0xbc]