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Differential D14279

[mips][microMIPS] Implement PRECEQ.W.PHL, PRECEQ.W.PHR, PRECEQU.PH.QBL, PRECEQU.PH.QBLA, PRECEQU.PH.QBR, PRECEQU.PH.QBRA, PRECEU.PH.QBL, PRECEU.PH.QBLA, PRECEU.PH.QBR and PRECEU.PH.QBRA instructions
ClosedPublic

Authored by zbuljan on Nov 3 2015, 3:34 AM.

Details

Reviewers
dsanders
zoran.jovanovic
hvarga
Commits
rL253326: [mips][microMIPS] Implement PRECEQ.W.PHL, PRECEQ.W.PHR, PRECEQU.PH.QBL…
Summary

The patch implements microMIPSDSP instructions: PRECEQ.W.PHL, PRECEQ.W.PHR, PRECEQU.PH.QBL, PRECEQU.PH.QBLA, PRECEQU.PH.QBR, PRECEQU.PH.QBRA, PRECEU.PH.QBL, PRECEU.PH.QBLA, PRECEU.PH.QBR and PRECEU.PH.QBRA

Diff Detail

Repository
rL LLVM

Event Timeline

zbuljan updated this revision to Diff 39042.Nov 3 2015, 3:34 AM
zbuljan retitled this revision from to [mips][microMIPS] Implement PRECEQ.W.PHL, PRECEQ.W.PHR, PRECEQU.PH.QBL, PRECEQU.PH.QBLA, PRECEQU.PH.QBR, PRECEQU.PH.QBRA, PRECEU.PH.QBL, PRECEU.PH.QBLA, PRECEU.PH.QBR and PRECEU.PH.QBRA instructions.
zbuljan updated this object.
zbuljan added reviewers: dsanders, hvarga, zoran.jovanovic.
zbuljan added subscribers: petarj, llvm-commits.
Herald added a subscriber: dsanders. · View Herald TranscriptNov 3 2015, 3:34 AM
dsanders accepted this revision.Nov 14 2015, 6:07 AM
dsanders edited edge metadata.

LGTM

This revision is now accepted and ready to land.Nov 14 2015, 6:07 AM
dsanders added a comment.Nov 14 2015, 6:11 AM

Sorry, I missed a small detail.

test/MC/Disassembler/Mips/micromips-dsp/valid.txt
31–40 ↗(On Diff #39042)

These should be copied to the DSPr2 tests too. Likewise for the assembler tests.

See my comment on D14058 for more info.

Closed by commit rL253326: [mips][microMIPS] Implement PRECEQ.W.PHL, PRECEQ.W.PHR, PRECEQU.PH.QBL… (authored by zbuljan). · Explain WhyNov 17 2015, 1:46 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
Mips/
42 lines
20 lines
test/
MC/
Disassembler/
Mips/
micromips-dsp/
10 lines
micromips-dspr2/
10 lines
Mips/
micromips-dsp/
10 lines
micromips-dspr2/
10 lines

Diff 40376

llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td

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class SHRAV_QB_MMR2_ENC : POOL32A_3R_FMT<"shrav.qb", 0b00111001101>; class SHRAV_QB_MMR2_ENC : POOL32A_3R_FMT<"shrav.qb", 0b00111001101>;
class SHRAV_R_QB_MMR2_ENC : POOL32A_3R_FMT<"shrav_r.qb", 0b10111001101>; class SHRAV_R_QB_MMR2_ENC : POOL32A_3R_FMT<"shrav_r.qb", 0b10111001101>;
class SHRAV_R_W_MM_ENC : POOL32A_3RB0_FMT<"shrav_r.w", 0b1011010101>; class SHRAV_R_W_MM_ENC : POOL32A_3RB0_FMT<"shrav_r.w", 0b1011010101>;
class SHRA_R_W_MM_ENC : POOL32A_2RSA5B0_FMT<"shra_r.w", 0b1011110101>; class SHRA_R_W_MM_ENC : POOL32A_2RSA5B0_FMT<"shra_r.w", 0b1011110101>;
class SHRL_PH_MMR2_ENC : POOL32A_2RSA4OP6_FMT<"shrl.ph", 0b001111>; class SHRL_PH_MMR2_ENC : POOL32A_2RSA4OP6_FMT<"shrl.ph", 0b001111>;
class SHRL_QB_MM_ENC : POOL32A_2RSA3_FMT<"shrl.qb", 0b1100001>; class SHRL_QB_MM_ENC : POOL32A_2RSA3_FMT<"shrl.qb", 0b1100001>;
class SHRLV_PH_MMR2_ENC : POOL32A_3RB0_FMT<"shrlv.ph", 0b1100010101>; class SHRLV_PH_MMR2_ENC : POOL32A_3RB0_FMT<"shrlv.ph", 0b1100010101>;
class SHRLV_QB_MM_ENC : POOL32A_3RB0_FMT<"shrlv.qb", 0b1101010101>; class SHRLV_QB_MM_ENC : POOL32A_3RB0_FMT<"shrlv.qb", 0b1101010101>;
class PRECEQ_W_PHL_MM_ENC : POOL32A_2R_FMT<"preceq.w.phl", 0b0101000100>;
class PRECEQ_W_PHR_MM_ENC : POOL32A_2R_FMT<"preceq.w.phr", 0b0110000100>;
class PRECEQU_PH_QBL_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbl", 0b0111000100>;
class PRECEQU_PH_QBLA_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbla", 0b0111001100>;
class PRECEQU_PH_QBR_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbr", 0b1001000100>;
class PRECEQU_PH_QBRA_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbra", 0b1001001100>;
class PRECEU_PH_QBL_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbl", 0b1011000100>;
class PRECEU_PH_QBLA_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbla", 0b1011001100>;
class PRECEU_PH_QBR_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbr", 0b1101000100>;
class PRECEU_PH_QBRA_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbra", 0b1101001100>;
// Instruction desc. // Instruction desc.
class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode, class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
InstrItinClass itin, RegisterOperand ROD, InstrItinClass itin, RegisterOperand ROD,
RegisterOperand ROS = ROD> { RegisterOperand ROS = ROD> {
dag OutOperandList = (outs ROD:$rt); dag OutOperandList = (outs ROD:$rt);
dag InOperandList = (ins ROS:$rs); dag InOperandList = (ins ROS:$rs);
string AsmString = !strconcat(opstr, "\t$rt, $rs"); string AsmString = !strconcat(opstr, "\t$rt, $rs");
list<dag> Pattern = [(set ROD:$rt, (OpNode ROS:$rs))]; list<dag> Pattern = [(set ROD:$rt, (OpNode ROS:$rs))];
InstrItinClass Itinerary = itin; InstrItinClass Itinerary = itin;
} }
class ABSQ_S_PH_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< class ABSQ_S_PH_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"absq_s.ph", int_mips_absq_s_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>; "absq_s.ph", int_mips_absq_s_ph, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
class ABSQ_S_W_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< class ABSQ_S_W_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"absq_s.w", int_mips_absq_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag20]>; "absq_s.w", int_mips_absq_s_w, NoItinerary, GPR32Opnd>, Defs<[DSPOutFlag20]>;
class ABSQ_S_QB_MMR2_DESC : ABSQ_S_PH_MM_R2_DESC_BASE< class ABSQ_S_QB_MMR2_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>; "absq_s.qb", int_mips_absq_s_qb, NoItinerary, DSPROpnd>, Defs<[DSPOutFlag20]>;
class PRECEQ_W_PHL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"preceq.w.phl", int_mips_preceq_w_phl, NoItinerary, GPR32Opnd, DSPROpnd>;
class PRECEQ_W_PHR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"preceq.w.phr", int_mips_preceq_w_phr, NoItinerary, GPR32Opnd, DSPROpnd>;
class PRECEQU_PH_QBL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"precequ.ph.qbl", int_mips_precequ_ph_qbl, NoItinerary, DSPROpnd>;
class PRECEQU_PH_QBLA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"precequ.ph.qbla", int_mips_precequ_ph_qbla, NoItinerary, DSPROpnd>;
class PRECEQU_PH_QBR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"precequ.ph.qbr", int_mips_precequ_ph_qbr, NoItinerary, DSPROpnd>;
class PRECEQU_PH_QBRA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"precequ.ph.qbra", int_mips_precequ_ph_qbra, NoItinerary, DSPROpnd>;
class PRECEU_PH_QBL_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"preceu.ph.qbl", int_mips_preceu_ph_qbl, NoItinerary, DSPROpnd>;
class PRECEU_PH_QBLA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"preceu.ph.qbla", int_mips_preceu_ph_qbla, NoItinerary, DSPROpnd>;
class PRECEU_PH_QBR_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"preceu.ph.qbr", int_mips_preceu_ph_qbr, NoItinerary, DSPROpnd>;
class PRECEU_PH_QBRA_MM_DESC : ABSQ_S_PH_MM_R2_DESC_BASE<
"preceu.ph.qbra", int_mips_preceu_ph_qbra, NoItinerary, DSPROpnd>;
class SHLL_R2_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode, class SHLL_R2_MM_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
SDPatternOperator ImmPat, InstrItinClass itin, SDPatternOperator ImmPat, InstrItinClass itin,
RegisterOperand RO, Operand ImmOpnd> { RegisterOperand RO, Operand ImmOpnd> {
dag OutOperandList = (outs RO:$rt); dag OutOperandList = (outs RO:$rt);
dag InOperandList = (ins RO:$rs, ImmOpnd:$sa); dag InOperandList = (ins RO:$rs, ImmOpnd:$sa);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa"); string AsmString = !strconcat(instr_asm, "\t$rt, $rs, $sa");
list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))]; list<dag> Pattern = [(set RO:$rt, (OpNode RO:$rs, ImmPat:$sa))];
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def SHRA_PH_MM : DspMMRel, SHRA_PH_MM_ENC, SHRA_PH_MM_DESC; def SHRA_PH_MM : DspMMRel, SHRA_PH_MM_ENC, SHRA_PH_MM_DESC;
def SHRA_R_PH_MM : DspMMRel, SHRA_R_PH_MM_ENC, SHRA_R_PH_MM_DESC; def SHRA_R_PH_MM : DspMMRel, SHRA_R_PH_MM_ENC, SHRA_R_PH_MM_DESC;
def SHRAV_PH_MM : DspMMRel, SHRAV_PH_MM_ENC, SHRAV_PH_MM_DESC; def SHRAV_PH_MM : DspMMRel, SHRAV_PH_MM_ENC, SHRAV_PH_MM_DESC;
def SHRAV_R_PH_MM : DspMMRel, SHRAV_R_PH_MM_ENC, SHRAV_R_PH_MM_DESC; def SHRAV_R_PH_MM : DspMMRel, SHRAV_R_PH_MM_ENC, SHRAV_R_PH_MM_DESC;
def SHRAV_R_W_MM : DspMMRel, SHRAV_R_W_MM_ENC, SHRAV_R_W_MM_DESC; def SHRAV_R_W_MM : DspMMRel, SHRAV_R_W_MM_ENC, SHRAV_R_W_MM_DESC;
def SHRA_R_W_MM : DspMMRel, SHRA_R_W_MM_ENC, SHRA_R_W_MM_DESC; def SHRA_R_W_MM : DspMMRel, SHRA_R_W_MM_ENC, SHRA_R_W_MM_DESC;
def SHRL_QB_MM : DspMMRel, SHRL_QB_MM_ENC, SHRL_QB_MM_DESC; def SHRL_QB_MM : DspMMRel, SHRL_QB_MM_ENC, SHRL_QB_MM_DESC;
def SHRLV_QB_MM : DspMMRel, SHRLV_QB_MM_ENC, SHRLV_QB_MM_DESC; def SHRLV_QB_MM : DspMMRel, SHRLV_QB_MM_ENC, SHRLV_QB_MM_DESC;
def PRECEQ_W_PHL_MM : DspMMRel, PRECEQ_W_PHL_MM_ENC, PRECEQ_W_PHL_MM_DESC;
def PRECEQ_W_PHR_MM : DspMMRel, PRECEQ_W_PHR_MM_ENC, PRECEQ_W_PHR_MM_DESC;
def PRECEQU_PH_QBL_MM : DspMMRel, PRECEQU_PH_QBL_MM_ENC, PRECEQU_PH_QBL_MM_DESC;
def PRECEQU_PH_QBLA_MM : DspMMRel, PRECEQU_PH_QBLA_MM_ENC,
PRECEQU_PH_QBLA_MM_DESC;
def PRECEQU_PH_QBR_MM : DspMMRel, PRECEQU_PH_QBR_MM_ENC, PRECEQU_PH_QBR_MM_DESC;
def PRECEQU_PH_QBRA_MM : DspMMRel, PRECEQU_PH_QBRA_MM_ENC,
PRECEQU_PH_QBRA_MM_DESC;
def PRECEU_PH_QBL_MM : DspMMRel, PRECEU_PH_QBL_MM_ENC, PRECEU_PH_QBL_MM_DESC;
def PRECEU_PH_QBLA_MM : DspMMRel, PRECEU_PH_QBLA_MM_ENC, PRECEU_PH_QBLA_MM_DESC;
def PRECEU_PH_QBR_MM : DspMMRel, PRECEU_PH_QBR_MM_ENC, PRECEU_PH_QBR_MM_DESC;
def PRECEU_PH_QBRA_MM : DspMMRel, PRECEU_PH_QBRA_MM_ENC, PRECEU_PH_QBRA_MM_DESC;
// microMIPS DSP Rev 2 // microMIPS DSP Rev 2
def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC, def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
ISA_DSPR2; ISA_DSPR2;
def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2; def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2;
def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2; def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2; def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2;
def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2; def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2; def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2;
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llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td

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def MODSUB : MODSUB_ENC, MODSUB_DESC; def MODSUB : MODSUB_ENC, MODSUB_DESC;
def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC; def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC; def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC; def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC; def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC; def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;
def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC; def PRECRQ_RS_PH_W : PRECRQ_RS_PH_W_ENC, PRECRQ_RS_PH_W_DESC;
def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC; def PRECRQU_S_QB_PH : PRECRQU_S_QB_PH_ENC, PRECRQU_S_QB_PH_DESC;
def PRECEQ_W_PHL : PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC; def PRECEQ_W_PHL : DspMMRel, PRECEQ_W_PHL_ENC, PRECEQ_W_PHL_DESC;
def PRECEQ_W_PHR : PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC; def PRECEQ_W_PHR : DspMMRel, PRECEQ_W_PHR_ENC, PRECEQ_W_PHR_DESC;
def PRECEQU_PH_QBL : PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC; def PRECEQU_PH_QBL : DspMMRel, PRECEQU_PH_QBL_ENC, PRECEQU_PH_QBL_DESC;
def PRECEQU_PH_QBR : PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC; def PRECEQU_PH_QBR : DspMMRel, PRECEQU_PH_QBR_ENC, PRECEQU_PH_QBR_DESC;
def PRECEQU_PH_QBLA : PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC; def PRECEQU_PH_QBLA : DspMMRel, PRECEQU_PH_QBLA_ENC, PRECEQU_PH_QBLA_DESC;
def PRECEQU_PH_QBRA : PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC; def PRECEQU_PH_QBRA : DspMMRel, PRECEQU_PH_QBRA_ENC, PRECEQU_PH_QBRA_DESC;
def PRECEU_PH_QBL : PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC; def PRECEU_PH_QBL : DspMMRel, PRECEU_PH_QBL_ENC, PRECEU_PH_QBL_DESC;
def PRECEU_PH_QBR : PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC; def PRECEU_PH_QBR : DspMMRel, PRECEU_PH_QBR_ENC, PRECEU_PH_QBR_DESC;
def PRECEU_PH_QBLA : PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC; def PRECEU_PH_QBLA : DspMMRel, PRECEU_PH_QBLA_ENC, PRECEU_PH_QBLA_DESC;
def PRECEU_PH_QBRA : PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC; def PRECEU_PH_QBRA : DspMMRel, PRECEU_PH_QBRA_ENC, PRECEU_PH_QBRA_DESC;
def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC; def SHLL_QB : DspMMRel, SHLL_QB_ENC, SHLL_QB_DESC;
def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC; def SHLLV_QB : DspMMRel, SHLLV_QB_ENC, SHLLV_QB_DESC;
def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC; def SHRL_QB : DspMMRel, SHRL_QB_ENC, SHRL_QB_DESC;
def SHRLV_QB : DspMMRel, SHRLV_QB_ENC, SHRLV_QB_DESC; def SHRLV_QB : DspMMRel, SHRLV_QB_ENC, SHRLV_QB_DESC;
def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC; def SHLL_PH : DspMMRel, SHLL_PH_ENC, SHLL_PH_DESC;
def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC; def SHLLV_PH : DspMMRel, SHLLV_PH_ENC, SHLLV_PH_DESC;
def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC; def SHLL_S_PH : DspMMRel, SHLL_S_PH_ENC, SHLL_S_PH_DESC;
def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC; def SHLLV_S_PH : DspMMRel, SHLLV_S_PH_ENC, SHLLV_S_PH_DESC;
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llvm/trunk/test/MC/Disassembler/Mips/micromips-dsp/valid.txt

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0x02 0xb4 0xb0 0xbc # CHECK: dpau.h.qbr $ac2, $20, $21 0x02 0xb4 0xb0 0xbc # CHECK: dpau.h.qbr $ac2, $20, $21
0x00 0x64 0x41 0x3c # CHECK: insv $3, $4 0x00 0x64 0x41 0x3c # CHECK: insv $3, $4
0x00 0xe6 0x4a 0xbc # CHECK: madd $ac1, $6, $7 0x00 0xe6 0x4a 0xbc # CHECK: madd $ac1, $6, $7
0x01 0x28 0x1a 0xbc # CHECK: maddu $ac0, $8, $9 0x01 0x28 0x1a 0xbc # CHECK: maddu $ac0, $8, $9
0x01 0x6a 0xea 0xbc # CHECK: msub $ac3, $10, $11 0x01 0x6a 0xea 0xbc # CHECK: msub $ac3, $10, $11
0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13 0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13
0x00 0x62 0xcc 0xbc # CHECK: mult $ac3, $2, $3 0x00 0x62 0xcc 0xbc # CHECK: mult $ac3, $2, $3
0x00 0xa4 0x9c 0xbc # CHECK: multu $ac2, $4, $5 0x00 0xa4 0x9c 0xbc # CHECK: multu $ac2, $4, $5
0x00 0x22 0x51 0x3c # CHECK: preceq.w.phl $1, $2
0x00 0x64 0x61 0x3c # CHECK: preceq.w.phr $3, $4
0x00 0xa6 0x71 0x3c # CHECK: precequ.ph.qbl $5, $6
0x00 0xe8 0x73 0x3c # CHECK: precequ.ph.qbla $7, $8
0x01 0x2a 0x91 0x3c # CHECK: precequ.ph.qbr $9, $10
0x01 0x6c 0x93 0x3c # CHECK: precequ.ph.qbra $11, $12
0x01 0xae 0xb1 0x3c # CHECK: preceu.ph.qbl $13, $14
0x01 0xf0 0xb3 0x3c # CHECK: preceu.ph.qbla $15, $16
0x02 0x32 0xd1 0x3c # CHECK: preceu.ph.qbr $17, $18
0x02 0x74 0xd3 0x3c # CHECK: preceu.ph.qbra $19, $20
0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5 0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5
0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5 0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5
0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5 0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5
0x00 0x85 0x18 0x0e # CHECK: shllv.ph $3, $4, $5 0x00 0x85 0x18 0x0e # CHECK: shllv.ph $3, $4, $5
0x00 0x85 0x1c 0x0e # CHECK: shllv_s.ph $3, $4, $5 0x00 0x85 0x1c 0x0e # CHECK: shllv_s.ph $3, $4, $5
0x00 0x85 0x1b 0x95 # CHECK: shllv.qb $3, $4, $5 0x00 0x85 0x1b 0x95 # CHECK: shllv.qb $3, $4, $5
0x00 0x85 0x1b 0xd5 # CHECK: shllv_s.w $3, $4, $5 0x00 0x85 0x1b 0xd5 # CHECK: shllv_s.w $3, $4, $5
0x00 0x64 0x2b 0xf5 # CHECK: shll_s.w $3, $4, 5 0x00 0x64 0x2b 0xf5 # CHECK: shll_s.w $3, $4, 5
0x00 0x64 0x53 0x35 # CHECK: shra.ph $3, $4, 5 0x00 0x64 0x53 0x35 # CHECK: shra.ph $3, $4, 5
0x00 0x64 0x57 0x35 # CHECK: shra_r.ph $3, $4, 5 0x00 0x64 0x57 0x35 # CHECK: shra_r.ph $3, $4, 5
0x00 0x85 0x19 0x8d # CHECK: shrav.ph $3, $4, $5 0x00 0x85 0x19 0x8d # CHECK: shrav.ph $3, $4, $5
0x00 0x85 0x1d 0x8d # CHECK: shrav_r.ph $3, $4, $5 0x00 0x85 0x1d 0x8d # CHECK: shrav_r.ph $3, $4, $5
0x00 0x85 0x1a 0xd5 # CHECK: shrav_r.w $3, $4, $5 0x00 0x85 0x1a 0xd5 # CHECK: shrav_r.w $3, $4, $5
0x00 0x64 0x2a 0xf5 # CHECK: shra_r.w $3, $4, 5 0x00 0x64 0x2a 0xf5 # CHECK: shra_r.w $3, $4, 5
0x00 0x64 0xb8 0x7c # CHECK: shrl.qb $3, $4, 5 0x00 0x64 0xb8 0x7c # CHECK: shrl.qb $3, $4, 5
0x00 0x85 0x1b 0x55 # CHECK: shrlv.qb $3, $4, $5 0x00 0x85 0x1b 0x55 # CHECK: shrlv.qb $3, $4, $5

llvm/trunk/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt

Show All 27 Lines
0x00 0x22 0xd0 0xbc # CHECK: dpax.w.ph $ac3, $2, $1 0x00 0x22 0xd0 0xbc # CHECK: dpax.w.ph $ac3, $2, $1
0x00 0x64 0x41 0x3c # CHECK: insv $3, $4 0x00 0x64 0x41 0x3c # CHECK: insv $3, $4
0x00 0xe6 0x4a 0xbc # CHECK: madd $ac1, $6, $7 0x00 0xe6 0x4a 0xbc # CHECK: madd $ac1, $6, $7
0x01 0x28 0x1a 0xbc # CHECK: maddu $ac0, $8, $9 0x01 0x28 0x1a 0xbc # CHECK: maddu $ac0, $8, $9
0x01 0x6a 0xea 0xbc # CHECK: msub $ac3, $10, $11 0x01 0x6a 0xea 0xbc # CHECK: msub $ac3, $10, $11
0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13 0x01 0xac 0xba 0xbc # CHECK: msubu $ac2, $12, $13
0x00 0x62 0xcc 0xbc # CHECK: mult $ac3, $2, $3 0x00 0x62 0xcc 0xbc # CHECK: mult $ac3, $2, $3
0x00 0xa4 0x9c 0xbc # CHECK: multu $ac2, $4, $5 0x00 0xa4 0x9c 0xbc # CHECK: multu $ac2, $4, $5
0x00 0x22 0x51 0x3c # CHECK: preceq.w.phl $1, $2
0x00 0x64 0x61 0x3c # CHECK: preceq.w.phr $3, $4
0x00 0xa6 0x71 0x3c # CHECK: precequ.ph.qbl $5, $6
0x00 0xe8 0x73 0x3c # CHECK: precequ.ph.qbla $7, $8
0x01 0x2a 0x91 0x3c # CHECK: precequ.ph.qbr $9, $10
0x01 0x6c 0x93 0x3c # CHECK: precequ.ph.qbra $11, $12
0x01 0xae 0xb1 0x3c # CHECK: preceu.ph.qbl $13, $14
0x01 0xf0 0xb3 0x3c # CHECK: preceu.ph.qbla $15, $16
0x02 0x32 0xd1 0x3c # CHECK: preceu.ph.qbr $17, $18
0x02 0x74 0xd3 0x3c # CHECK: preceu.ph.qbra $19, $20
0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5 0x00 0x64 0x53 0xb5 # CHECK: shll.ph $3, $4, 5
0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5 0x00 0x64 0x5b 0xb5 # CHECK: shll_s.ph $3, $4, 5
0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5 0x00 0x64 0xa8 0x7c # CHECK: shll.qb $3, $4, 5
0x00 0x85 0x18 0x0e # CHECK: shllv.ph $3, $4, $5 0x00 0x85 0x18 0x0e # CHECK: shllv.ph $3, $4, $5
0x00 0x85 0x1c 0x0e # CHECK: shllv_s.ph $3, $4, $5 0x00 0x85 0x1c 0x0e # CHECK: shllv_s.ph $3, $4, $5
0x00 0x85 0x1b 0x95 # CHECK: shllv.qb $3, $4, $5 0x00 0x85 0x1b 0x95 # CHECK: shllv.qb $3, $4, $5
0x00 0x85 0x1b 0xd5 # CHECK: shllv_s.w $3, $4, $5 0x00 0x85 0x1b 0xd5 # CHECK: shllv_s.w $3, $4, $5
0x00 0x64 0x2b 0xf5 # CHECK: shll_s.w $3, $4, 5 0x00 0x64 0x2b 0xf5 # CHECK: shll_s.w $3, $4, 5
Show All 14 Lines

llvm/trunk/test/MC/Mips/micromips-dsp/valid.s

Show All 15 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
dpau.h.qbr $ac2, $20, $21 # CHECK: dpau.h.qbr $ac2, $20, $21 # encoding: [0x02,0xb4,0xb0,0xbc] dpau.h.qbr $ac2, $20, $21 # CHECK: dpau.h.qbr $ac2, $20, $21 # encoding: [0x02,0xb4,0xb0,0xbc]
insv $3, $4 # CHECK: insv $3, $4 # encoding: [0x00,0x64,0x41,0x3c] insv $3, $4 # CHECK: insv $3, $4 # encoding: [0x00,0x64,0x41,0x3c]
madd $ac1, $6, $7 # CHECK: madd $ac1, $6, $7 # encoding: [0x00,0xe6,0x4a,0xbc] madd $ac1, $6, $7 # CHECK: madd $ac1, $6, $7 # encoding: [0x00,0xe6,0x4a,0xbc]
maddu $ac0, $8, $9 # CHECK: maddu $ac0, $8, $9 # encoding: [0x01,0x28,0x1a,0xbc] maddu $ac0, $8, $9 # CHECK: maddu $ac0, $8, $9 # encoding: [0x01,0x28,0x1a,0xbc]
msub $ac3, $10, $11 # CHECK: msub $ac3, $10, $11 # encoding: [0x01,0x6a,0xea,0xbc] msub $ac3, $10, $11 # CHECK: msub $ac3, $10, $11 # encoding: [0x01,0x6a,0xea,0xbc]
msubu $ac2, $12, $13 # CHECK: msubu $ac2, $12, $13 # encoding: [0x01,0xac,0xba,0xbc] msubu $ac2, $12, $13 # CHECK: msubu $ac2, $12, $13 # encoding: [0x01,0xac,0xba,0xbc]
mult $ac3, $2, $3 # CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x62,0xcc,0xbc] mult $ac3, $2, $3 # CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x62,0xcc,0xbc]
multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc] multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc]
preceq.w.phl $1, $2 # CHECK: preceq.w.phl $1, $2 # encoding: [0x00,0x22,0x51,0x3c]
preceq.w.phr $3, $4 # CHECK: preceq.w.phr $3, $4 # encoding: [0x00,0x64,0x61,0x3c]
precequ.ph.qbl $5, $6 # CHECK: precequ.ph.qbl $5, $6 # encoding: [0x00,0xa6,0x71,0x3c]
precequ.ph.qbla $7, $8 # CHECK: precequ.ph.qbla $7, $8 # encoding: [0x00,0xe8,0x73,0x3c]
precequ.ph.qbr $9, $10 # CHECK: precequ.ph.qbr $9, $10 # encoding: [0x01,0x2a,0x91,0x3c]
precequ.ph.qbra $11, $12 # CHECK: precequ.ph.qbra $11, $12 # encoding: [0x01,0x6c,0x93,0x3c]
preceu.ph.qbl $13, $14 # CHECK: preceu.ph.qbl $13, $14 # encoding: [0x01,0xae,0xb1,0x3c]
preceu.ph.qbla $15, $16 # CHECK: preceu.ph.qbla $15, $16 # encoding: [0x01,0xf0,0xb3,0x3c]
preceu.ph.qbr $17, $18 # CHECK: preceu.ph.qbr $17, $18 # encoding: [0x02,0x32,0xd1,0x3c]
preceu.ph.qbra $19, $20 # CHECK: preceu.ph.qbra $19, $20 # encoding: [0x02,0x74,0xd3,0x3c]
shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5] shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5]
shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5] shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5]
shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c] shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c]
shllv.ph $3, $4, $5 # CHECK: shllv.ph $3, $4, $5 # encoding: [0x00,0x85,0x18,0x0e] shllv.ph $3, $4, $5 # CHECK: shllv.ph $3, $4, $5 # encoding: [0x00,0x85,0x18,0x0e]
shllv_s.ph $3, $4, $5 # CHECK: shllv_s.ph $3, $4, $5 # encoding: [0x00,0x85,0x1c,0x0e] shllv_s.ph $3, $4, $5 # CHECK: shllv_s.ph $3, $4, $5 # encoding: [0x00,0x85,0x1c,0x0e]
shllv.qb $3, $4, $5 # CHECK: shllv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x95] shllv.qb $3, $4, $5 # CHECK: shllv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x95]
shllv_s.w $3, $4, $5 # CHECK: shllv_s.w $3, $4, $5 # encoding: [0x00,0x85,0x1b,0xd5] shllv_s.w $3, $4, $5 # CHECK: shllv_s.w $3, $4, $5 # encoding: [0x00,0x85,0x1b,0xd5]
shll_s.w $3, $4, 5 # CHECK: shll_s.w $3, $4, 5 # encoding: [0x00,0x64,0x2b,0xf5] shll_s.w $3, $4, 5 # CHECK: shll_s.w $3, $4, 5 # encoding: [0x00,0x64,0x2b,0xf5]
shra.ph $3, $4, 5 # CHECK: shra.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0x35] shra.ph $3, $4, 5 # CHECK: shra.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0x35]
shra_r.ph $3, $4, 5 # CHECK: shra_r.ph $3, $4, 5 # encoding: [0x00,0x64,0x57,0x35] shra_r.ph $3, $4, 5 # CHECK: shra_r.ph $3, $4, 5 # encoding: [0x00,0x64,0x57,0x35]
shrav.ph $3, $4, $5 # CHECK: shrav.ph $3, $4, $5 # encoding: [0x00,0x85,0x19,0x8d] shrav.ph $3, $4, $5 # CHECK: shrav.ph $3, $4, $5 # encoding: [0x00,0x85,0x19,0x8d]
shrav_r.ph $3, $4, $5 # CHECK: shrav_r.ph $3, $4, $5 # encoding: [0x00,0x85,0x1d,0x8d] shrav_r.ph $3, $4, $5 # CHECK: shrav_r.ph $3, $4, $5 # encoding: [0x00,0x85,0x1d,0x8d]
shrav_r.w $3, $4, $5 # CHECK: shrav_r.w $3, $4, $5 # encoding: [0x00,0x85,0x1a,0xd5] shrav_r.w $3, $4, $5 # CHECK: shrav_r.w $3, $4, $5 # encoding: [0x00,0x85,0x1a,0xd5]
shra_r.w $3, $4, 5 # CHECK: shra_r.w $3, $4, 5 # encoding: [0x00,0x64,0x2a,0xf5] shra_r.w $3, $4, 5 # CHECK: shra_r.w $3, $4, 5 # encoding: [0x00,0x64,0x2a,0xf5]
shrl.qb $3, $4, 5 # CHECK: shrl.qb $3, $4, 5 # encoding: [0x00,0x64,0xb8,0x7c] shrl.qb $3, $4, 5 # CHECK: shrl.qb $3, $4, 5 # encoding: [0x00,0x64,0xb8,0x7c]
shrlv.qb $3, $4, $5 # CHECK: shrlv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x55] shrlv.qb $3, $4, $5 # CHECK: shrlv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x55]

llvm/trunk/test/MC/Mips/micromips-dspr2/valid.s

Show All 28 Lines# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
dpax.w.ph $ac3, $2, $1 # CHECK: dpax.w.ph $ac3, $2, $1 # encoding: [0x00,0x22,0xd0,0xbc] dpax.w.ph $ac3, $2, $1 # CHECK: dpax.w.ph $ac3, $2, $1 # encoding: [0x00,0x22,0xd0,0xbc]
insv $3, $4 # CHECK: insv $3, $4 # encoding: [0x00,0x64,0x41,0x3c] insv $3, $4 # CHECK: insv $3, $4 # encoding: [0x00,0x64,0x41,0x3c]
madd $ac1, $6, $7 # CHECK: madd $ac1, $6, $7 # encoding: [0x00,0xe6,0x4a,0xbc] madd $ac1, $6, $7 # CHECK: madd $ac1, $6, $7 # encoding: [0x00,0xe6,0x4a,0xbc]
maddu $ac0, $8, $9 # CHECK: maddu $ac0, $8, $9 # encoding: [0x01,0x28,0x1a,0xbc] maddu $ac0, $8, $9 # CHECK: maddu $ac0, $8, $9 # encoding: [0x01,0x28,0x1a,0xbc]
msub $ac3, $10, $11 # CHECK: msub $ac3, $10, $11 # encoding: [0x01,0x6a,0xea,0xbc] msub $ac3, $10, $11 # CHECK: msub $ac3, $10, $11 # encoding: [0x01,0x6a,0xea,0xbc]
msubu $ac2, $12, $13 # CHECK: msubu $ac2, $12, $13 # encoding: [0x01,0xac,0xba,0xbc] msubu $ac2, $12, $13 # CHECK: msubu $ac2, $12, $13 # encoding: [0x01,0xac,0xba,0xbc]
mult $ac3, $2, $3 # CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x62,0xcc,0xbc] mult $ac3, $2, $3 # CHECK: mult $ac3, $2, $3 # encoding: [0x00,0x62,0xcc,0xbc]
multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc] multu $ac2, $4, $5 # CHECK: multu $ac2, $4, $5 # encoding: [0x00,0xa4,0x9c,0xbc]
preceq.w.phl $1, $2 # CHECK: preceq.w.phl $1, $2 # encoding: [0x00,0x22,0x51,0x3c]
preceq.w.phr $3, $4 # CHECK: preceq.w.phr $3, $4 # encoding: [0x00,0x64,0x61,0x3c]
precequ.ph.qbl $5, $6 # CHECK: precequ.ph.qbl $5, $6 # encoding: [0x00,0xa6,0x71,0x3c]
precequ.ph.qbla $7, $8 # CHECK: precequ.ph.qbla $7, $8 # encoding: [0x00,0xe8,0x73,0x3c]
precequ.ph.qbr $9, $10 # CHECK: precequ.ph.qbr $9, $10 # encoding: [0x01,0x2a,0x91,0x3c]
precequ.ph.qbra $11, $12 # CHECK: precequ.ph.qbra $11, $12 # encoding: [0x01,0x6c,0x93,0x3c]
preceu.ph.qbl $13, $14 # CHECK: preceu.ph.qbl $13, $14 # encoding: [0x01,0xae,0xb1,0x3c]
preceu.ph.qbla $15, $16 # CHECK: preceu.ph.qbla $15, $16 # encoding: [0x01,0xf0,0xb3,0x3c]
preceu.ph.qbr $17, $18 # CHECK: preceu.ph.qbr $17, $18 # encoding: [0x02,0x32,0xd1,0x3c]
preceu.ph.qbra $19, $20 # CHECK: preceu.ph.qbra $19, $20 # encoding: [0x02,0x74,0xd3,0x3c]
shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5] shll.ph $3, $4, 5 # CHECK: shll.ph $3, $4, 5 # encoding: [0x00,0x64,0x53,0xb5]
shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5] shll_s.ph $3, $4, 5 # CHECK: shll_s.ph $3, $4, 5 # encoding: [0x00,0x64,0x5b,0xb5]
shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c] shll.qb $3, $4, 5 # CHECK: shll.qb $3, $4, 5 # encoding: [0x00,0x64,0xa8,0x7c]
shllv.ph $3, $4, $5 # CHECK: shllv.ph $3, $4, $5 # encoding: [0x00,0x85,0x18,0x0e] shllv.ph $3, $4, $5 # CHECK: shllv.ph $3, $4, $5 # encoding: [0x00,0x85,0x18,0x0e]
shllv_s.ph $3, $4, $5 # CHECK: shllv_s.ph $3, $4, $5 # encoding: [0x00,0x85,0x1c,0x0e] shllv_s.ph $3, $4, $5 # CHECK: shllv_s.ph $3, $4, $5 # encoding: [0x00,0x85,0x1c,0x0e]
shllv.qb $3, $4, $5 # CHECK: shllv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x95] shllv.qb $3, $4, $5 # CHECK: shllv.qb $3, $4, $5 # encoding: [0x00,0x85,0x1b,0x95]
shllv_s.w $3, $4, $5 # CHECK: shllv_s.w $3, $4, $5 # encoding: [0x00,0x85,0x1b,0xd5] shllv_s.w $3, $4, $5 # CHECK: shllv_s.w $3, $4, $5 # encoding: [0x00,0x85,0x1b,0xd5]
shll_s.w $3, $4, 5 # CHECK: shll_s.w $3, $4, 5 # encoding: [0x00,0x64,0x2b,0xf5] shll_s.w $3, $4, 5 # CHECK: shll_s.w $3, $4, 5 # encoding: [0x00,0x64,0x2b,0xf5]
Show All 14 Lines