[mips][microMIPS] Implement SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, SUBQH[_R].W, SUBU[_S].PH, SUBU[_S].QB and SUBUH[_R].QB instructions

[zbuljan]

Summary

The patch implements microMIPSDSP instructions: SUBQ[_S].PH, SUBQ_S.W, SUBQH[_R].PH, SUBQH[_R].W, SUBU[_S].PH, SUBU[_S].QB and SUBUH[_R].QB

[dsanders]

LGTM with a small test change.

test/MC/Disassembler/Mips/micromips-dspr2/valid.txt

18–25 ↗

(On Diff #38535)

The DSPr1 tests should also be present. Likewise for the assembler tests.

See my comment on D14058 for more info.

llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrInfo.td

 class PRECEQU_PH_QBL_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbl", 0b0111000100>;
 class PRECEQU_PH_QBLA_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbla", 0b0111001100>;
 class PRECEQU_PH_QBR_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbr", 0b1001000100>;
 class PRECEQU_PH_QBRA_MM_ENC : POOL32A_2R_FMT<"precequ.ph.qbra", 0b1001001100>;
 class PRECEU_PH_QBL_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbl", 0b1011000100>;
 class PRECEU_PH_QBLA_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbla", 0b1011001100>;
 class PRECEU_PH_QBR_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbr", 0b1101000100>;
 class PRECEU_PH_QBRA_MM_ENC : POOL32A_2R_FMT<"preceu.ph.qbra", 0b1101001100>;
+class SUBQ_PH_MM_ENC : POOL32A_3R_FMT<"subq.ph", 0b01000001101>;
+class SUBQ_S_PH_MM_ENC : POOL32A_3R_FMT<"subq_s.ph", 0b11000001101>;
+class SUBQ_S_W_MM_ENC : POOL32A_3RB0_FMT<"subq_s.w", 0b1101000101>;
+class SUBQH_PH_MMR2_ENC : POOL32A_3R_FMT<"subqh.ph", 0b01001001101>;
+class SUBQH_R_PH_MMR2_ENC : POOL32A_3R_FMT<"subqh_r.ph", 0b11001001101>;
+class SUBQH_W_MMR2_ENC : POOL32A_3R_FMT<"subqh.w", 0b01010001101>;
+class SUBQH_R_W_MMR2_ENC : POOL32A_3R_FMT<"subqh_r.w", 0b11010001101>;
+class SUBU_PH_MMR2_ENC : POOL32A_3R_FMT<"subu.ph", 0b01100001101>;
+class SUBU_S_PH_MMR2_ENC : POOL32A_3R_FMT<"subu_s.ph", 0b11100001101>;
+class SUBU_QB_MM_ENC : POOL32A_3R_FMT<"subu.qb", 0b01011001101>;
+class SUBU_S_QB_MM_ENC : POOL32A_3R_FMT<"subu_s.qb", 0b11011001101>;
+class SUBUH_QB_MMR2_ENC : POOL32A_3R_FMT<"subuh.qb", 0b01101001101>;
+class SUBUH_R_QB_MMR2_ENC : POOL32A_3R_FMT<"subuh_r.qb", 0b11101001101>;
 
 // Instruction desc.
 class ABSQ_S_PH_MM_R2_DESC_BASE<string opstr, SDPatternOperator OpNode,
                                 InstrItinClass itin, RegisterOperand ROD,
                                 RegisterOperand ROS = ROD> {
   dag OutOperandList = (outs ROD:$rt);
   dag InOperandList = (ins ROS:$rs);
   string AsmString = !strconcat(opstr, "\t$rt, $rs");
def PRECEQU_PH_QBLA_MM : DspMMRel, PRECEQU_PH_QBLA_MM_ENC,
                          PRECEQU_PH_QBLA_MM_DESC;
 def PRECEQU_PH_QBR_MM : DspMMRel, PRECEQU_PH_QBR_MM_ENC, PRECEQU_PH_QBR_MM_DESC;
 def PRECEQU_PH_QBRA_MM : DspMMRel, PRECEQU_PH_QBRA_MM_ENC,
                          PRECEQU_PH_QBRA_MM_DESC;
 def PRECEU_PH_QBL_MM : DspMMRel, PRECEU_PH_QBL_MM_ENC, PRECEU_PH_QBL_MM_DESC;
 def PRECEU_PH_QBLA_MM : DspMMRel, PRECEU_PH_QBLA_MM_ENC, PRECEU_PH_QBLA_MM_DESC;
 def PRECEU_PH_QBR_MM : DspMMRel, PRECEU_PH_QBR_MM_ENC, PRECEU_PH_QBR_MM_DESC;
 def PRECEU_PH_QBRA_MM : DspMMRel, PRECEU_PH_QBRA_MM_ENC, PRECEU_PH_QBRA_MM_DESC;
+def SUBQ_PH_MM : DspMMRel, SUBQ_PH_MM_ENC, SUBQ_PH_DESC;
+def SUBQ_S_PH_MM : DspMMRel, SUBQ_S_PH_MM_ENC, SUBQ_S_PH_DESC;
+def SUBQ_S_W_MM : DspMMRel, SUBQ_S_W_MM_ENC, SUBQ_S_W_DESC;
+def SUBU_QB_MM : DspMMRel, SUBU_QB_MM_ENC, SUBU_QB_DESC;
+def SUBU_S_QB_MM : DspMMRel, SUBU_S_QB_MM_ENC, SUBU_S_QB_DESC;
 // microMIPS DSP Rev 2
 def ABSQ_S_QB_MMR2 : DspMMRel, ABSQ_S_QB_MMR2_ENC, ABSQ_S_QB_MMR2_DESC,
                      ISA_DSPR2;
 def ADDQH_PH_MMR2 : DspMMRel, ADDQH_PH_MMR2_ENC, ADDQH_PH_DESC, ISA_DSPR2;
 def ADDQH_R_PH_MMR2 : DspMMRel, ADDQH_R_PH_MMR2_ENC, ADDQH_R_PH_DESC, ISA_DSPR2;
 def ADDQH_W_MMR2 : DspMMRel, ADDQH_W_MMR2_ENC, ADDQH_W_DESC, ISA_DSPR2;
 def ADDQH_R_W_MMR2 : DspMMRel, ADDQH_R_W_MMR2_ENC, ADDQH_R_W_DESC, ISA_DSPR2;
 def ADDU_PH_MMR2 : DspMMRel, ADDU_PH_MMR2_ENC, ADDU_PH_DESC, ISA_DSPR2;

 def SHRA_QB_MMR2 : DspMMRel, SHRA_QB_MMR2_ENC, SHRA_QB_MMR2_DESC, ISA_DSPR2;
 def SHRA_R_QB_MMR2 : DspMMRel, SHRA_R_QB_MMR2_ENC, SHRA_R_QB_MMR2_DESC,
                      ISA_DSPR2;
 def SHRAV_QB_MMR2 : DspMMRel, SHRAV_QB_MMR2_ENC, SHRAV_QB_MMR2_DESC, ISA_DSPR2;
 def SHRAV_R_QB_MMR2 : DspMMRel, SHRAV_R_QB_MMR2_ENC, SHRAV_R_QB_MMR2_DESC,
                       ISA_DSPR2;
 def SHRL_PH_MMR2 : DspMMRel, SHRL_PH_MMR2_ENC, SHRL_PH_MMR2_DESC, ISA_DSPR2;
 def SHRLV_PH_MMR2 : DspMMRel, SHRLV_PH_MMR2_ENC, SHRLV_PH_MMR2_DESC, ISA_DSPR2;
+def SUBQH_PH_MMR2 : DspMMRel, SUBQH_PH_MMR2_ENC, SUBQH_PH_DESC, ISA_DSPR2;
+def SUBQH_R_PH_MMR2 : DspMMRel, SUBQH_R_PH_MMR2_ENC, SUBQH_R_PH_DESC, ISA_DSPR2;
+def SUBQH_W_MMR2 : DspMMRel, SUBQH_W_MMR2_ENC, SUBQH_W_DESC, ISA_DSPR2;
+def SUBQH_R_W_MMR2 : DspMMRel, SUBQH_R_W_MMR2_ENC, SUBQH_R_W_DESC, ISA_DSPR2;
+def SUBU_PH_MMR2 : DspMMRel, SUBU_PH_MMR2_ENC, SUBU_PH_DESC, ISA_DSPR2;
+def SUBU_S_PH_MMR2 : DspMMRel, SUBU_S_PH_MMR2_ENC, SUBU_S_PH_DESC, ISA_DSPR2;
+def SUBUH_QB_MMR2 : DspMMRel, SUBUH_QB_MMR2_ENC, SUBUH_QB_DESC, ISA_DSPR2;
+def SUBUH_R_QB_MMR2 : DspMMRel, SUBUH_R_QB_MMR2_ENC, SUBUH_R_QB_DESC, ISA_DSPR2;

llvm/trunk/lib/Target/Mips/MipsDSPInstrInfo.td

 // Pseudos.
 def BPOSGE32_PSEUDO : BPOSGE32_PSEUDO_DESC_BASE<int_mips_bposge32,
                                                 NoItinerary>, Uses<[DSPPos]>;
 
 // Instruction defs.
 // MIPS DSP Rev 1
 def ADDU_QB : DspMMRel, ADDU_QB_ENC, ADDU_QB_DESC;
 def ADDU_S_QB : DspMMRel, ADDU_S_QB_ENC, ADDU_S_QB_DESC;
-def SUBU_QB : SUBU_QB_ENC, SUBU_QB_DESC;
-def SUBU_S_QB : SUBU_S_QB_ENC, SUBU_S_QB_DESC;
+def SUBU_QB : DspMMRel, SUBU_QB_ENC, SUBU_QB_DESC;
+def SUBU_S_QB : DspMMRel, SUBU_S_QB_ENC, SUBU_S_QB_DESC;
 def ADDQ_PH : DspMMRel, ADDQ_PH_ENC, ADDQ_PH_DESC;
 def ADDQ_S_PH : DspMMRel, ADDQ_S_PH_ENC, ADDQ_S_PH_DESC;
-def SUBQ_PH : SUBQ_PH_ENC, SUBQ_PH_DESC;
-def SUBQ_S_PH : SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
+def SUBQ_PH : DspMMRel, SUBQ_PH_ENC, SUBQ_PH_DESC;
+def SUBQ_S_PH : DspMMRel, SUBQ_S_PH_ENC, SUBQ_S_PH_DESC;
 def ADDQ_S_W : DspMMRel, ADDQ_S_W_ENC, ADDQ_S_W_DESC;
-def SUBQ_S_W : SUBQ_S_W_ENC, SUBQ_S_W_DESC;
+def SUBQ_S_W : DspMMRel, SUBQ_S_W_ENC, SUBQ_S_W_DESC;
 def ADDSC : DspMMRel, ADDSC_ENC, ADDSC_DESC;
 def ADDWC : DspMMRel, ADDWC_ENC, ADDWC_DESC;
 def MODSUB : MODSUB_ENC, MODSUB_DESC;
 def RADDU_W_QB : RADDU_W_QB_ENC, RADDU_W_QB_DESC;
 def ABSQ_S_PH : DspMMRel, ABSQ_S_PH_ENC, ABSQ_S_PH_DESC;
 def ABSQ_S_W : DspMMRel, ABSQ_S_W_ENC, ABSQ_S_W_DESC;
 def PRECRQ_QB_PH : PRECRQ_QB_PH_ENC, PRECRQ_QB_PH_DESC;
 def PRECRQ_PH_W : PRECRQ_PH_W_ENC, PRECRQ_PH_W_DESC;

 def RDDSP : RDDSP_ENC, RDDSP_DESC;
 def WRDSP : WRDSP_ENC, WRDSP_DESC;
 
 // MIPS DSP Rev 2
 let Predicates = [HasDSPR2] in {
 
 def ADDU_PH : DspMMRel, ADDU_PH_ENC, ADDU_PH_DESC;
 def ADDU_S_PH : DspMMRel, ADDU_S_PH_ENC, ADDU_S_PH_DESC;
-def SUBU_PH : SUBU_PH_ENC, SUBU_PH_DESC;
-def SUBU_S_PH : SUBU_S_PH_ENC, SUBU_S_PH_DESC;
+def SUBU_PH : DspMMRel, SUBU_PH_ENC, SUBU_PH_DESC;
+def SUBU_S_PH : DspMMRel, SUBU_S_PH_ENC, SUBU_S_PH_DESC;
 def CMPGDU_EQ_QB : CMPGDU_EQ_QB_ENC, CMPGDU_EQ_QB_DESC;
 def CMPGDU_LT_QB : CMPGDU_LT_QB_ENC, CMPGDU_LT_QB_DESC;
 def CMPGDU_LE_QB : CMPGDU_LE_QB_ENC, CMPGDU_LE_QB_DESC;
 def ABSQ_S_QB : DspMMRel, ABSQ_S_QB_ENC, ABSQ_S_QB_DESC;
 def ADDUH_QB : DspMMRel, ADDUH_QB_ENC, ADDUH_QB_DESC;
 def ADDUH_R_QB : DspMMRel, ADDUH_R_QB_ENC, ADDUH_R_QB_DESC;
-def SUBUH_QB : SUBUH_QB_ENC, SUBUH_QB_DESC;
-def SUBUH_R_QB : SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
+def SUBUH_QB : DspMMRel, SUBUH_QB_ENC, SUBUH_QB_DESC;
+def SUBUH_R_QB : DspMMRel, SUBUH_R_QB_ENC, SUBUH_R_QB_DESC;
 def ADDQH_PH : DspMMRel, ADDQH_PH_ENC, ADDQH_PH_DESC;
 def ADDQH_R_PH : DspMMRel, ADDQH_R_PH_ENC, ADDQH_R_PH_DESC;
-def SUBQH_PH : SUBQH_PH_ENC, SUBQH_PH_DESC;
-def SUBQH_R_PH : SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
+def SUBQH_PH : DspMMRel, SUBQH_PH_ENC, SUBQH_PH_DESC;
+def SUBQH_R_PH : DspMMRel, SUBQH_R_PH_ENC, SUBQH_R_PH_DESC;
 def ADDQH_W : DspMMRel, ADDQH_W_ENC, ADDQH_W_DESC;
 def ADDQH_R_W : DspMMRel, ADDQH_R_W_ENC, ADDQH_R_W_DESC;
-def SUBQH_W : SUBQH_W_ENC, SUBQH_W_DESC;
-def SUBQH_R_W : SUBQH_R_W_ENC, SUBQH_R_W_DESC;
+def SUBQH_W : DspMMRel, SUBQH_W_ENC, SUBQH_W_DESC;
+def SUBQH_R_W : DspMMRel, SUBQH_R_W_ENC, SUBQH_R_W_DESC;
 def MUL_PH : MUL_PH_ENC, MUL_PH_DESC;
 def MUL_S_PH : MUL_S_PH_ENC, MUL_S_PH_DESC;
 def MULQ_S_W : MULQ_S_W_ENC, MULQ_S_W_DESC;
 def MULQ_RS_W : MULQ_RS_W_ENC, MULQ_RS_W_DESC;
 def MULQ_S_PH : MULQ_S_PH_ENC, MULQ_S_PH_DESC;
 def DPA_W_PH : DspMMRel, DPA_W_PH_ENC, DPA_W_PH_DESC;
 def DPS_W_PH : DPS_W_PH_ENC, DPS_W_PH_DESC;
 def DPAQX_S_W_PH : DspMMRel, DPAQX_S_W_PH_ENC, DPAQX_S_W_PH_DESC;

llvm/trunk/test/MC/Disassembler/Mips/micromips-dsp/valid.txt

 0x00 0x64 0x53 0x35 # CHECK: shra.ph $3, $4, 5
 0x00 0x64 0x57 0x35 # CHECK: shra_r.ph $3, $4, 5
 0x00 0x85 0x19 0x8d # CHECK: shrav.ph $3, $4, $5
 0x00 0x85 0x1d 0x8d # CHECK: shrav_r.ph $3, $4, $5
 0x00 0x85 0x1a 0xd5 # CHECK: shrav_r.w $3, $4, $5
 0x00 0x64 0x2a 0xf5 # CHECK: shra_r.w $3, $4, 5
 0x00 0x64 0xb8 0x7c # CHECK: shrl.qb $3, $4, 5
 0x00 0x85 0x1b 0x55 # CHECK: shrlv.qb $3, $4, $5
+0x00 0xa4 0x1a 0x0d # CHECK: subq.ph $3, $4, $5
+0x00 0xa4 0x1e 0x0d # CHECK: subq_s.ph $3, $4, $5
+0x00 0xa4 0x1b 0x45 # CHECK: subq_s.w $3, $4, $5
+0x00 0xa4 0x1a 0xcd # CHECK: subu.qb $3, $4, $5
+0x00 0xa4 0x1e 0xcd # CHECK: subu_s.qb $3, $4, $5

llvm/trunk/test/MC/Disassembler/Mips/micromips-dspr2/valid.txt

 0x00 0x85 0x1d 0x8d # CHECK: shrav_r.ph $3, $4, $5
 0x00 0x85 0x1d 0xcd # CHECK: shrav_r.qb $3, $4, $5
 0x00 0x85 0x1a 0xd5 # CHECK: shrav_r.w $3, $4, $5
 0x00 0x64 0x2a 0xf5 # CHECK: shra_r.w $3, $4, 5
 0x00 0x64 0x53 0xfc # CHECK: shrl.ph $3, $4, 5
 0x00 0x64 0xb8 0x7c # CHECK: shrl.qb $3, $4, 5
 0x00 0x85 0x1b 0x15 # CHECK: shrlv.ph $3, $4, $5
 0x00 0x85 0x1b 0x55 # CHECK: shrlv.qb $3, $4, $5
+0x00 0xa4 0x1a 0x0d # CHECK: subq.ph $3, $4, $5
+0x00 0xa4 0x1e 0x0d # CHECK: subq_s.ph $3, $4, $5
+0x00 0xa4 0x1b 0x45 # CHECK: subq_s.w $3, $4, $5
+0x00 0xa4 0x1a 0x4d # CHECK: subqh.ph $3, $4, $5
+0x00 0xa4 0x1e 0x4d # CHECK: subqh_r.ph $3, $4, $5
+0x00 0xa4 0x1a 0x8d # CHECK: subqh.w $3, $4, $5
+0x00 0xa4 0x1e 0x8d # CHECK: subqh_r.w $3, $4, $5
+0x00 0xa4 0x1b 0x0d # CHECK: subu.ph $3, $4, $5
+0x00 0xa4 0x1f 0x0d # CHECK: subu_s.ph $3, $4, $5
+0x00 0xa4 0x1a 0xcd # CHECK: subu.qb $3, $4, $5
+0x00 0xa4 0x1e 0xcd # CHECK: subu_s.qb $3, $4, $5
+0x00 0xa4 0x1b 0x4d # CHECK: subuh.qb $3, $4, $5
+0x00 0xa4 0x1f 0x4d # CHECK: subuh_r.qb $3, $4, $5

llvm/trunk/test/MC/Mips/micromips-dsp/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dsp | FileCheck %s
   shra.ph $3, $4, 5            # CHECK: shra.ph $3, $4, 5       # encoding: [0x00,0x64,0x53,0x35]
   shra_r.ph $3, $4, 5          # CHECK: shra_r.ph $3, $4, 5     # encoding: [0x00,0x64,0x57,0x35]
   shrav.ph $3, $4, $5          # CHECK: shrav.ph $3, $4, $5     # encoding: [0x00,0x85,0x19,0x8d]
   shrav_r.ph $3, $4, $5        # CHECK: shrav_r.ph $3, $4, $5   # encoding: [0x00,0x85,0x1d,0x8d]
   shrav_r.w $3, $4, $5         # CHECK: shrav_r.w $3, $4, $5    # encoding: [0x00,0x85,0x1a,0xd5]
   shra_r.w $3, $4, 5           # CHECK: shra_r.w $3, $4, 5      # encoding: [0x00,0x64,0x2a,0xf5]
   shrl.qb $3, $4, 5            # CHECK: shrl.qb $3, $4, 5       # encoding: [0x00,0x64,0xb8,0x7c]
   shrlv.qb $3, $4, $5          # CHECK: shrlv.qb $3, $4, $5     # encoding: [0x00,0x85,0x1b,0x55]
+  subq.ph $3, $4, $5           # CHECK: subq.ph $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0x0d]
+  subq_s.ph $3, $4, $5         # CHECK: subq_s.ph $3, $4, $5    # encoding: [0x00,0xa4,0x1e,0x0d]
+  subq_s.w $3, $4, $5          # CHECK: subq_s.w $3, $4, $5     # encoding: [0x00,0xa4,0x1b,0x45]
+  subu.qb $3, $4, $5           # CHECK: subu.qb $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0xcd]
+  subu_s.qb $3, $4, $5         # CHECK: subu_s.qb $3, $4, $5    # encoding: [0x00,0xa4,0x1e,0xcd]

llvm/trunk/test/MC/Mips/micromips-dspr2/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -mcpu=mips32r6 -mattr=micromips -mattr=+dspr2 | FileCheck %s
   shrav_r.ph $3, $4, $5        # CHECK: shrav_r.ph $3, $4, $5   # encoding: [0x00,0x85,0x1d,0x8d]
   shrav_r.qb $3, $4, $5        # CHECK: shrav_r.qb $3, $4, $5   # encoding: [0x00,0x85,0x1d,0xcd]
   shrav_r.w $3, $4, $5         # CHECK: shrav_r.w $3, $4, $5    # encoding: [0x00,0x85,0x1a,0xd5]
   shra_r.w $3, $4, 5           # CHECK: shra_r.w $3, $4, 5      # encoding: [0x00,0x64,0x2a,0xf5]
   shrl.ph $3, $4, 5            # CHECK: shrl.ph $3, $4, 5       # encoding: [0x00,0x64,0x53,0xfc]
   shrl.qb $3, $4, 5            # CHECK: shrl.qb $3, $4, 5       # encoding: [0x00,0x64,0xb8,0x7c]
   shrlv.ph $3, $4, $5          # CHECK: shrlv.ph $3, $4, $5     # encoding: [0x00,0x85,0x1b,0x15]
   shrlv.qb $3, $4, $5          # CHECK: shrlv.qb $3, $4, $5     # encoding: [0x00,0x85,0x1b,0x55]
+  subq.ph $3, $4, $5           # CHECK: subq.ph $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0x0d]
+  subq_s.ph $3, $4, $5         # CHECK: subq_s.ph $3, $4, $5    # encoding: [0x00,0xa4,0x1e,0x0d]
+  subq_s.w $3, $4, $5          # CHECK: subq_s.w $3, $4, $5     # encoding: [0x00,0xa4,0x1b,0x45]
+  subqh.ph $3, $4, $5          # CHECK: subqh.ph $3, $4, $5     # encoding: [0x00,0xa4,0x1a,0x4d]
+  subqh_r.ph $3, $4, $5        # CHECK: subqh_r.ph $3, $4, $5   # encoding: [0x00,0xa4,0x1e,0x4d]
+  subqh.w $3, $4, $5           # CHECK: subqh.w $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0x8d]
+  subqh_r.w $3, $4, $5         # CHECK: subqh_r.w $3, $4, $5    # encoding: [0x00,0xa4,0x1e,0x8d]
+  subu.ph $3, $4, $5           # CHECK: subu.ph $3, $4, $5      # encoding: [0x00,0xa4,0x1b,0x0d]
+  subu_s.ph $3, $4, $5         # CHECK: subu_s.ph $3, $4, $5    # encoding: [0x00,0xa4,0x1f,0x0d]
+  subu.qb $3, $4, $5           # CHECK: subu.qb $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0xcd]
+  subu_s.qb $3, $4, $5         # CHECK: subu_s.qb $3, $4, $5    # encoding: [0x00,0xa4,0x1e,0xcd]
+  subuh.qb $3, $4, $5          # CHECK: subuh.qb $3, $4, $5     # encoding: [0x00,0xa4,0x1b,0x4d]
+  subuh_r.qb $3, $4, $5        # CHECK: subuh_r.qb $3, $4, $5   # encoding: [0x00,0xa4,0x1f,0x4d]