Fix for Arm watchpoint cache corruption in case of ptrace failure

[omjavaid]

Summary

Arm watchpoint handlers incorrectly updates watchpoint cache incase we have a ptrace failures.

This patch fixes this issue by reverting the cache to its previous state in case of a ptrace failure.

[tberghammer]

LGTM

lldb/trunk/source/Plugins/Process/Linux/NativeRegisterContextLinux_arm.cpp

if ((m_hbr_regs[bp_index].control & 1) == 0)
         m_hbr_regs[bp_index].address = addr;
         m_hbr_regs[bp_index].control = control_value;
         m_hbr_regs[bp_index].refcount = 1;
 
         // PTRACE call to set corresponding hardware breakpoint register.
         error = WriteHardwareDebugRegs(eDREGTypeBREAK, bp_index);
 
         if (error.Fail())
+        {
+            m_hbr_regs[bp_index].address = 0;
+            m_hbr_regs[bp_index].control &= ~1;
+            m_hbr_regs[bp_index].refcount = 0;
+
             return LLDB_INVALID_INDEX32;
         }
+    }
     else
         m_hbr_regs[bp_index].refcount++;
 
     return bp_index;
 }
 
 bool
 NativeRegisterContextLinux_arm::ClearHardwareBreakpoint (uint32_t hw_idx)
NativeRegisterContextLinux_arm::ClearHardwareBreakpoint (uint32_t hw_idx)
     // Update reference count if multiple references.
     if (m_hbr_regs[hw_idx].refcount > 1)
     {
         m_hbr_regs[hw_idx].refcount--;
         return true;
     }
     else if (m_hbr_regs[hw_idx].refcount == 1)
     {
+        // Create a backup we can revert to in case of failure.
+        lldb::addr_t tempAddr = m_hbr_regs[hw_idx].address;
+        uint32_t tempControl = m_hbr_regs[hw_idx].control;
+        uint32_t tempRefCount = m_hbr_regs[hw_idx].refcount;
+
         m_hbr_regs[hw_idx].control &= ~1;
         m_hbr_regs[hw_idx].address = 0;
         m_hbr_regs[hw_idx].refcount = 0;
 
         // PTRACE call to clear corresponding hardware breakpoint register.
         WriteHardwareDebugRegs(eDREGTypeBREAK, hw_idx);
 
         if (error.Fail())
+        {
+            m_hbr_regs[hw_idx].control = tempControl;
+            m_hbr_regs[hw_idx].address = tempAddr;
+            m_hbr_regs[hw_idx].refcount = tempRefCount;
+
             return false;
+        }
 
         return true;
     }
 
     return false;
 }
 
 uint32_t
if ((m_hwp_regs[wp_index].control & 1) == 0)
         m_hwp_regs[wp_index].address = addr;
         m_hwp_regs[wp_index].control = control_value;
         m_hwp_regs[wp_index].refcount = 1;
 
         // PTRACE call to set corresponding watchpoint register.
         error = WriteHardwareDebugRegs(eDREGTypeWATCH, wp_index);
 
         if (error.Fail())
+        {
+            m_hwp_regs[wp_index].address = 0;
+            m_hwp_regs[wp_index].control &= ~1;
+            m_hwp_regs[wp_index].refcount = 0;
+
             return LLDB_INVALID_INDEX32;
         }
+    }
     else
         m_hwp_regs[wp_index].refcount++;
 
     return wp_index;
 }
 
 bool
 NativeRegisterContextLinux_arm::ClearHardwareWatchpoint (uint32_t wp_index)
NativeRegisterContextLinux_arm::ClearHardwareWatchpoint (uint32_t wp_index)
     // Update reference count if multiple references.
     if (m_hwp_regs[wp_index].refcount > 1)
     {
         m_hwp_regs[wp_index].refcount--;
         return true;
     }
     else if (m_hwp_regs[wp_index].refcount == 1)
     {
+        // Create a backup we can revert to in case of failure.
+        lldb::addr_t tempAddr = m_hwp_regs[wp_index].address;
+        uint32_t tempControl = m_hwp_regs[wp_index].control;
+        uint32_t tempRefCount = m_hwp_regs[wp_index].refcount;
+
         // Update watchpoint in local cache
         m_hwp_regs[wp_index].control &= ~1;
         m_hwp_regs[wp_index].address = 0;
         m_hwp_regs[wp_index].refcount = 0;
 
         // Ptrace call to update hardware debug registers
         error = WriteHardwareDebugRegs(eDREGTypeWATCH, wp_index);
 
         if (error.Fail())
+        {
+            m_hwp_regs[wp_index].control = tempControl;
+            m_hwp_regs[wp_index].address = tempAddr;
+            m_hwp_regs[wp_index].refcount = tempRefCount;
+
             return false;
+        }
 
         return true;
     }
 
     return false;
 }
 
 Error
 NativeRegisterContextLinux_arm::ClearAllHardwareWatchpoints ()
 {
     Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_WATCHPOINTS));
 
     if (log)
         log->Printf ("NativeRegisterContextLinux_arm::%s()", __FUNCTION__);
 
     Error error;
 
     // Read hardware breakpoint and watchpoint information.
     error = ReadHardwareDebugInfo ();
 
     if (error.Fail())
         return error;
 
+    lldb::addr_t tempAddr = 0;
+    uint32_t tempControl = 0, tempRefCount = 0;
+
     for (uint32_t i = 0; i < m_max_hwp_supported; i++)
     {
         if (m_hwp_regs[i].control & 0x01)
         {
+            // Create a backup we can revert to in case of failure.
+            tempAddr = m_hwp_regs[i].address;
+            tempControl = m_hwp_regs[i].control;
+            tempRefCount = m_hwp_regs[i].refcount;
+
             // Clear watchpoints in local cache
             m_hwp_regs[i].control &= ~1;
             m_hwp_regs[i].address = 0;
             m_hwp_regs[i].refcount = 0;
 
             // Ptrace call to update hardware debug registers
             error = WriteHardwareDebugRegs(eDREGTypeWATCH, i);
 
             if (error.Fail())
+            {
+                m_hwp_regs[i].control = tempControl;
+                m_hwp_regs[i].address = tempAddr;
+                m_hwp_regs[i].refcount = tempRefCount;
+
                 return error;
             }
         }
+    }
 
     return Error();
 }
 
 uint32_t
 NativeRegisterContextLinux_arm::GetWatchpointSize(uint32_t wp_index)
 {
     Log *log(lldb_private::GetLogIfAllCategoriesSet (LIBLLDB_LOG_WATCHPOINTS));