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Differential D126852

[RISCV] Add more patterns for FNMADD
ClosedPublic

Authored by liaolucy on Jun 1 2022, 8:52 PM.

Details

Reviewers
craig.topper
luismarques
asb
Commits
rGf14d18c7a954: [RISCV] Add more patterns for FNMADD
Summary

D54205 handles fnmadd: -rs1 * rs2 - rs3
This patch add fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)

Diff Detail

Event Timeline

liaolucy created this revision.Jun 1 2022, 8:52 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 1 2022, 8:52 PM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 28 others. · View Herald Transcript
liaolucy requested review of this revision.Jun 1 2022, 8:52 PM
Herald added a project: Restricted Project. · View Herald TranscriptJun 1 2022, 8:52 PM
Herald added subscribers: llvm-commits, • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
craig.topper requested changes to this revision.EditedJun 1 2022, 8:57 PM

This patch is only valid with the nsz flag on the FMA.

See also https://reviews.llvm.org/D109525 and https://reviews.llvm.org/D90901

This revision now requires changes to proceed.Jun 1 2022, 8:57 PM
Harbormaster completed remote builds in B167440: Diff 433643.Jun 1 2022, 9:51 PM
liaolucy updated this revision to Diff 433707.Jun 2 2022, 3:01 AM

Address @craig.topper's comment.

Add a PatFrag to check presence of nsz on the fma.

liaolucy edited the summary of this revision. (Show Details)Jun 2 2022, 3:02 AM
Harbormaster completed remote builds in B167484: Diff 433707.Jun 2 2022, 3:40 AM
craig.topper accepted this revision.Jun 2 2022, 9:26 PM

LGTM

This revision is now accepted and ready to land.Jun 2 2022, 9:26 PM
This revision was landed with ongoing or failed builds.Jun 3 2022, 9:31 PM
Closed by commit rGf14d18c7a954: [RISCV] Add more patterns for FNMADD (authored by liaolucy). · Explain Why
This revision was automatically updated to reflect the committed changes.
liaolucy added a commit: rGf14d18c7a954: [RISCV] Add more patterns for FNMADD.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
4 lines
8 lines
4 lines
test/
CodeGen/
RISCV/
79 lines
76 lines
173 lines

Diff 434240

llvm/lib/Target/RISCV/RISCVInstrInfoD.td

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// fnmsub: -rs1 * rs2 + rs3 // fnmsub: -rs1 * rs2 + rs3
def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3), def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, FPR64:$rs3),
(FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; (FNMSUB_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
// fnmadd: -rs1 * rs2 - rs3 // fnmadd: -rs1 * rs2 - rs3
def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)), def : Pat<(any_fma (fneg FPR64:$rs1), FPR64:$rs2, (fneg FPR64:$rs3)),
(FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>; (FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)
def : Pat<(fneg (any_fma_nsz FPR64:$rs1, FPR64:$rs2, FPR64:$rs3)),
(FNMADD_D FPR64:$rs1, FPR64:$rs2, FPR64:$rs3, 0b111)>;
// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches // The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
// LLVM's fminnum and fmaxnum. // LLVM's fminnum and fmaxnum.
// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
def : PatFprFpr<fminnum, FMIN_D, FPR64>; def : PatFprFpr<fminnum, FMIN_D, FPR64>;
def : PatFprFpr<fmaxnum, FMAX_D, FPR64>; def : PatFprFpr<fmaxnum, FMAX_D, FPR64>;
/// Setcc /// Setcc
// FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
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llvm/lib/Target/RISCV/RISCVInstrInfoF.td

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def riscv_any_fcvt_w_rv64 : PatFrags<(ops node:$src, node:$frm), def riscv_any_fcvt_w_rv64 : PatFrags<(ops node:$src, node:$frm),
[(riscv_strict_fcvt_w_rv64 node:$src, node:$frm), [(riscv_strict_fcvt_w_rv64 node:$src, node:$frm),
(riscv_fcvt_w_rv64 node:$src, node:$frm)]>; (riscv_fcvt_w_rv64 node:$src, node:$frm)]>;
def riscv_any_fcvt_wu_rv64 : PatFrags<(ops node:$src, node:$frm), def riscv_any_fcvt_wu_rv64 : PatFrags<(ops node:$src, node:$frm),
[(riscv_strict_fcvt_wu_rv64 node:$src, node:$frm), [(riscv_strict_fcvt_wu_rv64 node:$src, node:$frm),
(riscv_fcvt_wu_rv64 node:$src, node:$frm)]>; (riscv_fcvt_wu_rv64 node:$src, node:$frm)]>;
def any_fma_nsz : PatFrag<(ops node:$rs1, node:$rs2, node:$rs3),
(any_fma node:$rs1, node:$rs2, node:$rs3), [{
return N->getFlags().hasNoSignedZeros();
}]>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Operand and SDNode transformation definitions. // Operand and SDNode transformation definitions.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Zfinx // Zfinx
def GPRAsFPR : AsmOperandClass { def GPRAsFPR : AsmOperandClass {
let Name = "GPRAsFPR"; let Name = "GPRAsFPR";
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// fnmsub: -rs1 * rs2 + rs3 // fnmsub: -rs1 * rs2 + rs3
def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3), def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, FPR32:$rs3),
(FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; (FNMSUB_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
// fnmadd: -rs1 * rs2 - rs3 // fnmadd: -rs1 * rs2 - rs3
def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)), def : Pat<(any_fma (fneg FPR32:$rs1), FPR32:$rs2, (fneg FPR32:$rs3)),
(FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>; (FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)
def : Pat<(fneg (any_fma_nsz FPR32:$rs1, FPR32:$rs2, FPR32:$rs3)),
(FNMADD_S FPR32:$rs1, FPR32:$rs2, FPR32:$rs3, 0b111)>;
// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches // The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
// LLVM's fminnum and fmaxnum // LLVM's fminnum and fmaxnum
// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
def : PatFprFpr<fminnum, FMIN_S, FPR32>; def : PatFprFpr<fminnum, FMIN_S, FPR32>;
def : PatFprFpr<fmaxnum, FMAX_S, FPR32>; def : PatFprFpr<fmaxnum, FMAX_S, FPR32>;
/// Setcc /// Setcc
// FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
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llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

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// fnmsub: -rs1 * rs2 + rs3 // fnmsub: -rs1 * rs2 + rs3
def : Pat<(any_fma (fneg FPR16:$rs1), FPR16:$rs2, FPR16:$rs3), def : Pat<(any_fma (fneg FPR16:$rs1), FPR16:$rs2, FPR16:$rs3),
(FNMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>; (FNMSUB_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
// fnmadd: -rs1 * rs2 - rs3 // fnmadd: -rs1 * rs2 - rs3
def : Pat<(any_fma (fneg FPR16:$rs1), FPR16:$rs2, (fneg FPR16:$rs3)), def : Pat<(any_fma (fneg FPR16:$rs1), FPR16:$rs2, (fneg FPR16:$rs3)),
(FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>; (FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)
def : Pat<(fneg (any_fma_nsz FPR16:$rs1, FPR16:$rs2, FPR16:$rs3)),
(FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, 0b111)>;
// The ratified 20191213 ISA spec defines fmin and fmax in a way that matches // The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
// LLVM's fminnum and fmaxnum // LLVM's fminnum and fmaxnum
// <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>. // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
def : PatFprFpr<fminnum, FMIN_H, FPR16>; def : PatFprFpr<fminnum, FMIN_H, FPR16>;
def : PatFprFpr<fmaxnum, FMAX_H, FPR16>; def : PatFprFpr<fmaxnum, FMAX_H, FPR16>;
/// Setcc /// Setcc
// FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
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llvm/test/CodeGen/RISCV/double-arith.ll

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%b_ = fadd double 0.0, %b %b_ = fadd double 0.0, %b
%c_ = fadd double 0.0, %c %c_ = fadd double 0.0, %c
%negb = fsub double -0.0, %b_ %negb = fsub double -0.0, %b_
%negc = fsub double -0.0, %c_ %negc = fsub double -0.0, %c_
%1 = call double @llvm.fma.f64(double %a, double %negb, double %negc) %1 = call double @llvm.fma.f64(double %a, double %negb, double %negc)
ret double %1 ret double %1
} }
define double @fnmadd_d_3(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmadd_d_3:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fmadd.d ft0, fa0, fa1, fa2
; RV32IFD-NEXT: fneg.d fa0, ft0
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fnmadd_d_3:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmadd.d ft0, fa0, fa1, fa2
; RV64IFD-NEXT: fneg.d fa0, ft0
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fnmadd_d_3:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: fnmadd_d_3:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call fma@plt
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call double @llvm.fma.f64(double %a, double %b, double %c)
%neg = fneg double %1
ret double %neg
}
define double @fnmadd_nsz(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmadd_nsz:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: fnmadd_nsz:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fnmadd.d fa0, fa0, fa1, fa2
; RV64IFD-NEXT: ret
;
; RV32I-LABEL: fnmadd_nsz:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call fma@plt
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: xor a1, a1, a2
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: fnmadd_nsz:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call fma@plt
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call nsz double @llvm.fma.f64(double %a, double %b, double %c)
%neg = fneg nsz double %1
ret double %neg
}
define double @fnmsub_d(double %a, double %b, double %c) nounwind { define double @fnmsub_d(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fnmsub_d: ; RV32IFD-LABEL: fnmsub_d:
; RV32IFD: # %bb.0: ; RV32IFD: # %bb.0:
; RV32IFD-NEXT: fcvt.d.w ft0, zero ; RV32IFD-NEXT: fcvt.d.w ft0, zero
; RV32IFD-NEXT: fadd.d ft0, fa0, ft0 ; RV32IFD-NEXT: fadd.d ft0, fa0, ft0
; RV32IFD-NEXT: fnmsub.d fa0, ft0, fa1, fa2 ; RV32IFD-NEXT: fnmsub.d fa0, ft0, fa1, fa2
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; ;
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llvm/test/CodeGen/RISCV/float-arith.ll

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%b_ = fadd float 0.0, %b %b_ = fadd float 0.0, %b
%c_ = fadd float 0.0, %c %c_ = fadd float 0.0, %c
%negb = fsub float -0.0, %b_ %negb = fsub float -0.0, %b_
%negc = fsub float -0.0, %c_ %negc = fsub float -0.0, %c_
%1 = call float @llvm.fma.f32(float %a, float %negb, float %negc) %1 = call float @llvm.fma.f32(float %a, float %negb, float %negc)
ret float %1 ret float %1
} }
define float @fnmadd_s_3(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmadd_s_3:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmadd.s ft0, fa0, fa1, fa2
; RV32IF-NEXT: fneg.s fa0, ft0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fnmadd_s_3:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmadd.s ft0, fa0, fa1, fa2
; RV64IF-NEXT: fneg.s fa0, ft0
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_3:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: fnmadd_s_3:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call float @llvm.fma.f32(float %a, float %b, float %c)
%neg = fneg float %1
ret float %neg
}
define float @fnmadd_nsz(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmadd_nsz:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fnmadd_nsz:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fnmadd.s fa0, fa0, fa1, fa2
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fnmadd_nsz:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV64I-LABEL: fnmadd_nsz:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: lui a1, 524288
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call nsz float @llvm.fma.f32(float %a, float %b, float %c)
%neg = fneg nsz float %1
ret float %neg
}
define float @fnmsub_s(float %a, float %b, float %c) nounwind { define float @fnmsub_s(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmsub_s: ; RV32IF-LABEL: fnmsub_s:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, zero ; RV32IF-NEXT: fmv.w.x ft0, zero
; RV32IF-NEXT: fadd.s ft0, fa0, ft0 ; RV32IF-NEXT: fadd.s ft0, fa0, ft0
; RV32IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2 ; RV32IF-NEXT: fnmsub.s fa0, ft0, fa1, fa2
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; ;
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llvm/test/CodeGen/RISCV/half-arith.ll

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%b_ = fadd half 0.0, %b %b_ = fadd half 0.0, %b
%c_ = fadd half 0.0, %c %c_ = fadd half 0.0, %c
%negb = fsub half -0.0, %b_ %negb = fsub half -0.0, %b_
%negc = fsub half -0.0, %c_ %negc = fsub half -0.0, %c_
%1 = call half @llvm.fma.f16(half %a, half %negb, half %negc) %1 = call half @llvm.fma.f16(half %a, half %negb, half %negc)
ret half %1 ret half %1
} }
define half @fnmadd_s_3(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fnmadd_s_3:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmadd.h ft0, fa0, fa1, fa2
; RV32IZFH-NEXT: fneg.h fa0, ft0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fnmadd_s_3:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fmadd.h ft0, fa0, fa1, fa2
; RV64IZFH-NEXT: fneg.h fa0, ft0
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fnmadd_s_3:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s3, a1, -1
; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __extendhfsf2@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __extendhfsf2@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __extendhfsf2@plt
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: call __truncsfhf2@plt
; RV32I-NEXT: lui a1, 1048568
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
; RV64I-LABEL: fnmadd_s_3:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __extendhfsf2@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __extendhfsf2@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __extendhfsf2@plt
; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: call __truncsfhf2@plt
; RV64I-NEXT: lui a1, 1048568
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
%1 = call half @llvm.fma.f16(half %a, half %b, half %c)
%neg = fneg half %1
ret half %neg
}
define half @fnmadd_nsz(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fnmadd_nsz:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fnmadd_nsz:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: fnmadd.h fa0, fa0, fa1, fa2
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fnmadd_nsz:
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a2
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi s3, a1, -1
; RV32I-NEXT: and a0, a0, s3
; RV32I-NEXT: call __extendhfsf2@plt
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: and a0, s1, s3
; RV32I-NEXT: call __extendhfsf2@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: and a0, s0, s3
; RV32I-NEXT: call __extendhfsf2@plt
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: call __truncsfhf2@plt
; RV32I-NEXT: lui a1, 1048568
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
; RV64I-LABEL: fnmadd_nsz:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s1, 24(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 16(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s3, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a2
; RV64I-NEXT: mv s1, a1
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw s3, a1, -1
; RV64I-NEXT: and a0, a0, s3
; RV64I-NEXT: call __extendhfsf2@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: and a0, s1, s3
; RV64I-NEXT: call __extendhfsf2@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: and a0, s0, s3
; RV64I-NEXT: call __extendhfsf2@plt
; RV64I-NEXT: mv a2, a0
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: call __truncsfhf2@plt
; RV64I-NEXT: lui a1, 1048568
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
%1 = call nsz half @llvm.fma.f16(half %a, half %b, half %c)
%neg = fneg nsz half %1
ret half %neg
}
define half @fnmsub_s(half %a, half %b, half %c) nounwind { define half @fnmsub_s(half %a, half %b, half %c) nounwind {
; RV32IZFH-LABEL: fnmsub_s: ; RV32IZFH-LABEL: fnmsub_s:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: fmv.h.x ft0, zero ; RV32IZFH-NEXT: fmv.h.x ft0, zero
; RV32IZFH-NEXT: fadd.h ft0, fa0, ft0 ; RV32IZFH-NEXT: fadd.h ft0, fa0, ft0
; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2 ; RV32IZFH-NEXT: fnmsub.h fa0, ft0, fa1, fa2
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; ;
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