use "unpredictable" metadata in fast-isel when splitting compares

[spatel]

Summary

This patch uses the metadata created by the llvm.unpredictable intrinsic in D12341 to avoid creating an unpredictable branch.

[kparzysz]

LGTM

[spatel]

Patch updated:
Added 'TODO' comment assuming that 'unpredictable' now carries a value rather being a boolean.

[spatel]

Patch updated:
Removed comment about threshold value; we can add that feature when we have profile data to feed into this metadata.

llvm/trunk/lib/CodeGen/CodeGenPrepare.cpp

for (auto &BB : F) {
     //   %cond2 = icmp|fcmp|binary instruction ...
     //   %cond.or = or|and i1 %cond1, cond2
     //   br i1 %cond.or label %dest1, label %dest2"
     BinaryOperator *LogicOp;
     BasicBlock *TBB, *FBB;
     if (!match(BB.getTerminator(), m_Br(m_OneUse(m_BinOp(LogicOp)), TBB, FBB)))
       continue;
 
+    auto *Br1 = cast<BranchInst>(BB.getTerminator());
+    if (Br1->getMetadata(LLVMContext::MD_unpredictable))
+      continue;
+
     unsigned Opc;
     Value *Cond1, *Cond2;
     if (match(LogicOp, m_And(m_OneUse(m_Value(Cond1)),
                              m_OneUse(m_Value(Cond2)))))
       Opc = Instruction::And;
     else if (match(LogicOp, m_Or(m_OneUse(m_Value(Cond1)),
                                  m_OneUse(m_Value(Cond2)))))
       Opc = Instruction::Or;
for (auto &BB : F) {
     auto *InsertBefore = std::next(Function::iterator(BB))
         .getNodePtrUnchecked();
     auto TmpBB = BasicBlock::Create(BB.getContext(),
                                     BB.getName() + ".cond.split",
                                     BB.getParent(), InsertBefore);
 
     // Update original basic block by using the first condition directly by the
     // branch instruction and removing the no longer needed and/or instruction.
-    auto *Br1 = cast<BranchInst>(BB.getTerminator());
     Br1->setCondition(Cond1);
     LogicOp->eraseFromParent();
 
     // Depending on the conditon we have to either replace the true or the false
     // successor of the original branch instruction.
     if (Opc == Instruction::And)
       Br1->setSuccessor(0, TmpBB);
     else

llvm/trunk/test/CodeGen/AArch64/fast-isel-branch-cond-split.ll

 bb3:
   ret i64 0
 
 bb4:
   %2 = call i64 @bar()
   ret i64 %2
 }
 
+; If the branch is unpredictable, don't add another branch.
+
+; CHECK-LABEL: test_or_unpredictable
+; CHECK:       cmp   w0, #0
+; CHECK-NEXT:  cset  w8, eq
+; CHECK-NEXT:  cmp   w1, #0
+; CHECK-NEXT:  cset  w9, eq
+; CHECK-NEXT:  orr   w8, w8, w9
+; CHECK-NEXT:  and   w8, w8, #0x1
+; CHECK-NEXT:  cmp   w8, #0
+; CHECK-NEXT:  b.ne 
+define i64 @test_or_unpredictable(i32 %a, i32 %b) {
+bb1:
+  %0 = icmp eq i32 %a, 0
+  %1 = icmp eq i32 %b, 0
+  %or.cond = or i1 %0, %1
+  br i1 %or.cond, label %bb3, label %bb4, !unpredictable !2
+
+bb3:
+  ret i64 0
+
+bb4:
+  %2 = call i64 @bar()
+  ret i64 %2
+}
+
+; CHECK-LABEL: test_and_unpredictable
+; CHECK:       cmp   w0, #0
+; CHECK-NEXT:  cset  w8, ne
+; CHECK-NEXT:  cmp   w1, #0
+; CHECK-NEXT:  cset  w9, ne
+; CHECK-NEXT:  and   w8, w8, w9
+; CHECK-NEXT:  and   w8, w8, #0x1
+; CHECK-NEXT:  cmp   w8, #0
+; CHECK-NEXT:  b.eq 
+define i64 @test_and_unpredictable(i32 %a, i32 %b) {
+bb1:
+  %0 = icmp ne i32 %a, 0
+  %1 = icmp ne i32 %b, 0
+  %or.cond = and i1 %0, %1
+  br i1 %or.cond, label %bb4, label %bb3, !unpredictable !2
+
+bb3:
+  ret i64 0
+
+bb4:
+  %2 = call i64 @bar()
+  ret i64 %2
+}
+
 declare i64 @bar()
 
 !0 = !{!"branch_weights", i32 5128, i32 32}
 !1 = !{!"branch_weights", i32 1024, i32 4136}
+!2 = !{}
+