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- Apr 21 2014, 4:27 PM (352 w, 2 d)
Tue, Jan 19
Thu, Jan 14
Mehdi has fixed this.
Wed, Jan 13
Committed in https://reviews.llvm.org/rGa2e6506c47b1.
Committed in https://reviews.llvm.org/rGa2e6506c47b1.
Could you try this patch? https://reviews.llvm.org/D94607
Thanks for the report, looking into it.
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Dec 16 2020
This commit broke compilation of debuginfo-tests/llvm-prettyprinters/gdb/mlir-support.cpp. The compile command for this file doesn't get the path to the tblgen-generated includes, and it fails with
In file included from /w/src/llvm.org/debuginfo-tests/llvm-prettyprinters/gdb/mlir-support.cpp:2: /w/src/llvm.org/llvm/../mlir/include/mlir/IR/BuiltinTypes.h:638:10: fatal error: 'mlir/IR/BuiltinTypes.h.inc' file not found #include "mlir/IR/BuiltinTypes.h.inc" ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1 error generated.
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Nov 27 2020
LGTM, Thanks!
Nov 25 2020
Looks great! Thank you for doing this.
Nov 23 2020
Nov 20 2020
LGTM. Thanks!
Nov 19 2020
Sorry, I just noticed this now. Yes, this does make perfect sense. As a matter of fact, I've been thinking of reorganizing the "default mode" to be something that does not need an explicit entry.
Nov 2 2020
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Sep 30 2020
Committed in db04bec5f1eeb581ee1470e5f444cc7b918c6d93. Somehow phabricator missed it and didn't close automatically.
Sep 25 2020
Sep 24 2020
You're right, it goes in the other direction. Looks ok to me.
Sep 23 2020
I don't think it's safe to add dead defs to the extra lanes. You could split the superset into the matching part and the remaining part, then only operate on the matching one.
We should probably change bugpoint to stop using undef everywhere.
Fixed in https://reviews.llvm.org/rGe976fb1e54f3.
Sep 21 2020
Removed unnecessary checks in isSubmask.
Fixed submask detection.
Sep 18 2020
Pre-committed new test file.
Add testcases with unequal masks.
Removed the bool argument to getMatchingValue. Added comments explaining how the return value is used.
Sep 16 2020
Sep 15 2020
Should be fixed in https://reviews.llvm.org/rG5f4abb7fab1c.
The machine instructions in both dumps are identical... There are differences in addresses that are printed in the dump, and in the names of some values in the LLVM IR, but the machine instructions are the same.
The LLVM ERROR: Do not know how to split the result of this operator! happens when a function with an HVX intrinsic is compiled without +hvx,+hvx-length... attributes.
I added it to attributes #0, #1, #3 and #4.
If you have the ability to pass LLVM options, could you get the good and bad outputs with -debug-only=isel,legalize-types,legalizedag -print-after-all?
Just llc -march=hexagon < bad_hvx64_code.ll, but I added "target-cpu"="hexagonv65" "target-features"="+hvx,+hvx-length64b" to attributes inside the file.
Rebased on top of D87691.
Created D87691 with the refactoring. Will rebase this patch soon.
Sep 14 2020
Great, thanks! Will take a look tomorrow.
Do you know what vector types are involved (e.g. <32 x i8>)? Anything with i1 or i64?
This should be NFC for everything that doesn't involve masked loads/stores.
Sep 12 2020
Sep 11 2020
Sure. Keep me posted.