[ARM][AArch64] Turn on by default interleaved access lowering

[sbaranga]

Summary

Interleaved access lowering removes a memory operation and a
sequence of vector shuffles and replaces it with a series of
memory operations. This should be always beneficial.

This pass in only enabled on ARM/AArch64.

[rengolin]

W00t!!

I'm assuming no regressions on test-suite and usual benchmarks.

If that's true, LGTM!

[sbaranga]

Hi Renato,

This should be part of a series of patches to enable interleaved access vectorization. I haven't tried benchmarking this specific change.

I'll post two more patches to enable interleaved access vectorization on ARM/AArch64 that rely on this change going in, and I'll have benchmarking numbers for those.

Cheers,
Silviu

[rengolin]

I'm more concerned with correctness at this level. But if you have tested all your changes together, as long as this one doesn't fail basic check-all on its own, should be ok.

[sbaranga]

Thanks, committed in r246540

-Silviu

lib/CodeGen/InterleavedAccessPass.cpp

 
 using namespace llvm;
 
 #define DEBUG_TYPE "interleaved-access"
 
 static cl::opt<bool> LowerInterleavedAccesses(
     "lower-interleaved-accesses",
     cl::desc("Enable lowering interleaved accesses to intrinsics"),
-    cl::init(false), cl::Hidden);
+    cl::init(true), cl::Hidden);
 
 static unsigned MaxFactor; // The maximum supported interleave factor.
 
 namespace llvm {
 static void initializeInterleavedAccessPass(PassRegistry &);
 }
 
 namespace {

test/CodeGen/ARM/vext.ll

-; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - -lower-interleaved-accesses=false | FileCheck %s
 
 define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: test_vextd:
 ;CHECK: vext
   %tmp1 = load <8 x i8>, <8 x i8>* %A
   %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10>
   ret <8 x i8> %tmp3

test/CodeGen/ARM/vpadd.ll

-; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
+; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - -lower-interleaved-accesses=false | FileCheck %s
 
 define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 ;CHECK-LABEL: vpaddi8:
 ;CHECK: vpadd.i8
   %tmp1 = load <8 x i8>, <8 x i8>* %A
   %tmp2 = load <8 x i8>, <8 x i8>* %B
   %tmp3 = call <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
   ret <8 x i8> %tmp3