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Differential D117710

AMDGPU/GlobalISel: Mostly fix BFI patterns
ClosedPublic

Authored by arsenm on Jan 19 2022, 11:56 AM.

Details

Reviewers
foad
Group Reviewers
Restricted Project
Summary

Most importantly, fixes constant bus errors in the 64-bit cases. It's
surprising to me these were even passing the selection test using
SReg_* sources. Also fixes pattern matching in the 32-bit cases, with
simple operands.




These patterns aren't working in a few cases, like with mixed SGPR

inputs. The patterns aren't looking through the SGPR->VGPR copies like

they need to. The vector cases also have some unmerges of build_vector

which are obscuring the inputs.
Diff Detail
Event Timeline
arsenm created this revision.Jan 19 2022, 11:56 AM
Herald added subscribers: foad, kerbowa, hiraditya and 8 others.  ·  View Herald TranscriptJan 19 2022, 11:56 AM
arsenm requested review of this revision.Jan 19 2022, 11:56 AM
Herald added a project: Restricted Project.  ·  View Herald TranscriptJan 19 2022, 11:56 AM
Herald added a subscriber: wdng.  ·  View Herald Transcript
arsenm added a parent revision: D117708: AMDGPU: Add some additional test coverage for BFI matching.Jan 19 2022, 11:56 AM
Harbormaster completed remote builds in B144383: Diff 401360.Jan 19 2022, 11:57 AM
foad accepted this revision.Jan 20 2022, 2:51 AM
LGTM, thanks!
llvm/test/CodeGen/AMDGPU/bfi_int.ll


5
Could use a common prefix GFX8 for GFX8-SDAG and GFX8-GISEL, since the simple cases work out identical, and the same for GFX10?
This revision is now accepted and ready to land.Jan 20 2022, 2:51 AM
arsenm closed this revision.Jan 26 2022, 12:07 PM
09fc311af702e06fbb7a89cdee13a61face102ed
Revision Contents
PathSize
llvm/
lib/
Target/
AMDGPU/
54 lines
test/
CodeGen/
AMDGPU/
763 lines
Diff 401360
llvm/lib/Target/AMDGPU/SIInstructions.td
Show First 20 Lines • Show All 1,764 Lines • ▼ Show 20 Lines    return X && NotX &&

      ~(unsigned)X->getZExtValue() == (unsigned)NotX->getZExtValue();
      ~(unsigned)X->getZExtValue() == (unsigned)NotX->getZExtValue();

  }]
  }]

>;
>;




// Definition from ISA doc:
// Definition from ISA doc:

// (y & x) | (z & ~x)
// (y & x) | (z & ~x)

def : AMDGPUPat <
def : AMDGPUPat <

  (DivergentBinFrag<or> (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
  (DivergentBinFrag<or> (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),

  (V_BFI_B32_e64 $x, $y, $z)
  (V_BFI_B32_e64 VSrc_b32:$x, VSrc_b32:$y, VSrc_b32:$z)

>;
>;




// (y & C) | (z & ~C)
// (y & C) | (z & ~C)

def : AMDGPUPat <
def : AMDGPUPat <

  (BFIImm32 i32:$x, i32:$y, i32:$z),
  (BFIImm32 i32:$x, i32:$y, i32:$z),

  (V_BFI_B32_e64 $x, $y, $z)
  (V_BFI_B32_e64 VSrc_b32:$x, VSrc_b32:$y, VSrc_b32:$z)

>;
>;




// 64-bit version
// 64-bit version

def : AMDGPUPat <
def : AMDGPUPat <

  (DivergentBinFrag<or> (and i64:$y, i64:$x), (and i64:$z, (not i64:$x))),
  (DivergentBinFrag<or> (and i64:$y, i64:$x), (and i64:$z, (not i64:$x))),

  (REG_SEQUENCE SReg_64,
  (REG_SEQUENCE VReg_64,

    (V_BFI_B32_e64 (i32 (EXTRACT_SUBREG SReg_64:$x, sub0)),
    (V_BFI_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$x, sub0)),

               (i32 (EXTRACT_SUBREG SReg_64:$y, sub0)),
               (i32 (EXTRACT_SUBREG VReg_64:$y, sub0)),

               (i32 (EXTRACT_SUBREG SReg_64:$z, sub0))), sub0,
               (i32 (EXTRACT_SUBREG VReg_64:$z, sub0))), sub0,

    (V_BFI_B32_e64 (i32 (EXTRACT_SUBREG SReg_64:$x, sub1)),
    (V_BFI_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$x, sub1)),

               (i32 (EXTRACT_SUBREG SReg_64:$y, sub1)),
               (i32 (EXTRACT_SUBREG VReg_64:$y, sub1)),

               (i32 (EXTRACT_SUBREG SReg_64:$z, sub1))), sub1)
               (i32 (EXTRACT_SUBREG VReg_64:$z, sub1))), sub1)

>;
>;




// SHA-256 Ch function
// SHA-256 Ch function

// z ^ (x & (y ^ z))
// z ^ (x & (y ^ z))

def : AMDGPUPat <
def : AMDGPUPat <

  (DivergentBinFrag<xor> i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
  (DivergentBinFrag<xor> i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),

  (V_BFI_B32_e64 $x, $y, $z)
  (V_BFI_B32_e64 VSrc_b32:$x, VSrc_b32:$y, VSrc_b32:$z)

>;
>;




// 64-bit version
// 64-bit version

def : AMDGPUPat <
def : AMDGPUPat <

  (DivergentBinFrag<xor> i64:$z, (and i64:$x, (xor i64:$y, i64:$z))),
  (DivergentBinFrag<xor> i64:$z, (and i64:$x, (xor i64:$y, i64:$z))),

  (REG_SEQUENCE SReg_64,
  (REG_SEQUENCE VReg_64,

    (V_BFI_B32_e64 (i32 (EXTRACT_SUBREG SReg_64:$x, sub0)),
    (V_BFI_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$x, sub0)),

               (i32 (EXTRACT_SUBREG SReg_64:$y, sub0)),
               (i32 (EXTRACT_SUBREG VReg_64:$y, sub0)),

               (i32 (EXTRACT_SUBREG SReg_64:$z, sub0))), sub0,
               (i32 (EXTRACT_SUBREG VReg_64:$z, sub0))), sub0,

    (V_BFI_B32_e64 (i32 (EXTRACT_SUBREG SReg_64:$x, sub1)),
    (V_BFI_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$x, sub1)),

               (i32 (EXTRACT_SUBREG SReg_64:$y, sub1)),
               (i32 (EXTRACT_SUBREG VReg_64:$y, sub1)),

               (i32 (EXTRACT_SUBREG SReg_64:$z, sub1))), sub1)
               (i32 (EXTRACT_SUBREG VReg_64:$z, sub1))), sub1)

>;
>;




def : AMDGPUPat <
def : AMDGPUPat <

  (fcopysign f32:$src0, f32:$src1),
  (fcopysign f32:$src0, f32:$src1),

  (V_BFI_B32_e64 (S_MOV_B32 (i32 0x7fffffff)), $src0, $src1)
  (V_BFI_B32_e64 (S_MOV_B32 (i32 0x7fffffff)), $src0, $src1)

>;
>;




def : AMDGPUPat <
def : AMDGPUPat <

▲ Show 20 Lines • Show All 909 Lines • ▼ Show 20 Lines
>;
>;




// SHA-256 Ma patterns
// SHA-256 Ma patterns




// ((x & z) | (y & (x | z))) -> BFI (XOR x, y), z, y
// ((x & z) | (y & (x | z))) -> BFI (XOR x, y), z, y

def : AMDGPUPat <
def : AMDGPUPat <

  (DivergentBinFrag<or> (and i32:$x, i32:$z),
  (DivergentBinFrag<or> (and i32:$x, i32:$z),

                        (and i32:$y, (or i32:$x, i32:$z))),
                        (and i32:$y, (or i32:$x, i32:$z))),

  (V_BFI_B32_e64 (V_XOR_B32_e64 i32:$x, i32:$y), i32:$z, i32:$y)
  (V_BFI_B32_e64 (V_XOR_B32_e64 VSrc_b32:$x, VSrc_b32:$y), VSrc_b32:$z, VSrc_b32:$y)

>;
>;




def : AMDGPUPat <
def : AMDGPUPat <

  (DivergentBinFrag<or> (and i64:$x, i64:$z),
  (DivergentBinFrag<or> (and i64:$x, i64:$z),

                        (and i64:$y, (or i64:$x, i64:$z))),
                        (and i64:$y, (or i64:$x, i64:$z))),

  (REG_SEQUENCE SReg_64,
  (REG_SEQUENCE VReg_64,

    (V_BFI_B32_e64 (V_XOR_B32_e64 (i32 (EXTRACT_SUBREG SReg_64:$x, sub0)),
    (V_BFI_B32_e64 (V_XOR_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$x, sub0)),

                    (i32 (EXTRACT_SUBREG SReg_64:$y, sub0))),
                    (i32 (EXTRACT_SUBREG VReg_64:$y, sub0))),

               (i32 (EXTRACT_SUBREG SReg_64:$z, sub0)),
               (i32 (EXTRACT_SUBREG VReg_64:$z, sub0)),

               (i32 (EXTRACT_SUBREG SReg_64:$y, sub0))), sub0,
               (i32 (EXTRACT_SUBREG VReg_64:$y, sub0))), sub0,

    (V_BFI_B32_e64 (V_XOR_B32_e64 (i32 (EXTRACT_SUBREG SReg_64:$x, sub1)),
    (V_BFI_B32_e64 (V_XOR_B32_e64 (i32 (EXTRACT_SUBREG VReg_64:$x, sub1)),

                    (i32 (EXTRACT_SUBREG SReg_64:$y, sub1))),
                    (i32 (EXTRACT_SUBREG VReg_64:$y, sub1))),

               (i32 (EXTRACT_SUBREG SReg_64:$z, sub1)),
               (i32 (EXTRACT_SUBREG VReg_64:$z, sub1)),

               (i32 (EXTRACT_SUBREG SReg_64:$y, sub1))), sub1)
               (i32 (EXTRACT_SUBREG VReg_64:$y, sub1))), sub1)

>;
>;




multiclass IntMed3Pat<Instruction med3Inst,
multiclass IntMed3Pat<Instruction med3Inst,

                 SDPatternOperator min,
                 SDPatternOperator min,

                 SDPatternOperator max,
                 SDPatternOperator max,

                 SDPatternOperator min_oneuse,
                 SDPatternOperator min_oneuse,

                 SDPatternOperator max_oneuse> {
                 SDPatternOperator max_oneuse> {




▲ Show 20 Lines • Show All 334 Lines • Show Last 20 Lines
llvm/test/CodeGen/AMDGPU/bfi_int.ll
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX7 %s
; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX7 %s

; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX8 %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX8 %s

; RUN: llc -march=amdgcn -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX10 %s
; RUN: llc -march=amdgcn -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX10 %s

; RUN: llc -global-isel -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX8-GISEL %s

foadUnsubmitted
Not Done
ReplyInline Actions
Could use a common prefix GFX8 for GFX8-SDAG and GFX8-GISEL, since the simple cases work out identical, and the same for GFX10?
foad: Could use a common prefix GFX8 for GFX8-SDAG and GFX8-GISEL, since the simple cases work out…
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1031 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX10-GISEL %s




; BFI_INT Definition pattern from ISA docs
; BFI_INT Definition pattern from ISA docs

; (y & x) | (z & ~x)
; (y & x) | (z & ~x)

;
;

define amdgpu_kernel void @s_bfi_def_i32(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {
define amdgpu_kernel void @s_bfi_def_i32(i32 addrspace(1)* %out, i32 %x, i32 %y, i32 %z) {

; GFX7-LABEL: s_bfi_def_i32:
; GFX7-LABEL: s_bfi_def_i32:

; GFX7:       ; %bb.0: ; %entry
; GFX7:       ; %bb.0: ; %entry

; GFX7-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb
; GFX7-NEXT:    s_load_dwordx2 s[4:5], s[0:1], 0xb

Show All 33 Lines
; GFX10-NEXT:    v_mov_b32_e32 v0, 0
; GFX10-NEXT:    v_mov_b32_e32 v0, 0

; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt lgkmcnt(0)

; GFX10-NEXT:    s_andn2_b32 s4, s4, s2
; GFX10-NEXT:    s_andn2_b32 s4, s4, s2

; GFX10-NEXT:    s_and_b32 s2, s3, s2
; GFX10-NEXT:    s_and_b32 s2, s3, s2

; GFX10-NEXT:    s_or_b32 s2, s4, s2
; GFX10-NEXT:    s_or_b32 s2, s4, s2

; GFX10-NEXT:    v_mov_b32_e32 v1, s2
; GFX10-NEXT:    v_mov_b32_e32 v1, s2

; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]

; GFX10-NEXT:    s_endpgm
; GFX10-NEXT:    s_endpgm

;

; GFX8-GISEL-LABEL: s_bfi_def_i32:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c

; GFX8-GISEL-NEXT:    s_load_dword s4, s[0:1], 0x34

; GFX8-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24

; GFX8-GISEL-NEXT:    s_waitcnt lgkmcnt(0)

; GFX8-GISEL-NEXT:    s_andn2_b32 s4, s4, s2

; GFX8-GISEL-NEXT:    s_and_b32 s2, s3, s2

; GFX8-GISEL-NEXT:    s_or_b32 s2, s4, s2

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v0, s0

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v2, s2

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v1, s1

; GFX8-GISEL-NEXT:    flat_store_dword v[0:1], v2

; GFX8-GISEL-NEXT:    s_endpgm

;

; GFX10-GISEL-LABEL: s_bfi_def_i32:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    s_clause 0x2

; GFX10-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c

; GFX10-GISEL-NEXT:    s_load_dword s4, s[0:1], 0x34

; GFX10-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24

; GFX10-GISEL-NEXT:    v_mov_b32_e32 v1, 0

; GFX10-GISEL-NEXT:    s_waitcnt lgkmcnt(0)

; GFX10-GISEL-NEXT:    s_andn2_b32 s4, s4, s2

; GFX10-GISEL-NEXT:    s_and_b32 s2, s3, s2

; GFX10-GISEL-NEXT:    s_or_b32 s2, s4, s2

; GFX10-GISEL-NEXT:    v_mov_b32_e32 v0, s2

; GFX10-GISEL-NEXT:    global_store_dword v1, v0, s[0:1]

; GFX10-GISEL-NEXT:    s_endpgm

entry:
entry:

  %0 = xor i32 %x, -1
  %0 = xor i32 %x, -1

  %1 = and i32 %z, %0
  %1 = and i32 %z, %0

  %2 = and i32 %y, %x
  %2 = and i32 %y, %x

  %3 = or i32 %1, %2
  %3 = or i32 %1, %2

  store i32 %3, i32 addrspace(1)* %out
  store i32 %3, i32 addrspace(1)* %out

  ret void
  ret void

}
}

Show All 12 Lines
; GFX8-NEXT:    s_setpc_b64 s[30:31]
; GFX8-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX10-LABEL: v_bfi_def_i32:
; GFX10-LABEL: v_bfi_def_i32:

; GFX10:       ; %bb.0: ; %entry
; GFX10:       ; %bb.0: ; %entry

; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-NEXT:    v_bfi_b32 v0, v0, v1, v2
; GFX10-NEXT:    v_bfi_b32 v0, v0, v1, v2

; GFX10-NEXT:    s_setpc_b64 s[30:31]
; GFX10-NEXT:    s_setpc_b64 s[30:31]

;

; GFX8-GISEL-LABEL: v_bfi_def_i32:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-GISEL-NEXT:    v_bfi_b32 v0, v0, v1, v2

; GFX8-GISEL-NEXT:    s_setpc_b64 s[30:31]

;

; GFX10-GISEL-LABEL: v_bfi_def_i32:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX10-GISEL-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-GISEL-NEXT:    v_bfi_b32 v0, v0, v1, v2

; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]

entry:
entry:

  %0 = xor i32 %x, -1
  %0 = xor i32 %x, -1

  %1 = and i32 %z, %0
  %1 = and i32 %z, %0

  %2 = and i32 %y, %x
  %2 = and i32 %y, %x

  %3 = or i32 %1, %2
  %3 = or i32 %1, %2

  ret i32 %3
  ret i32 %3

}
}




Show All 39 Lines
; GFX10-NEXT:    v_mov_b32_e32 v0, 0
; GFX10-NEXT:    v_mov_b32_e32 v0, 0

; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt lgkmcnt(0)

; GFX10-NEXT:    s_xor_b32 s3, s3, s4
; GFX10-NEXT:    s_xor_b32 s3, s3, s4

; GFX10-NEXT:    s_and_b32 s2, s2, s3
; GFX10-NEXT:    s_and_b32 s2, s2, s3

; GFX10-NEXT:    s_xor_b32 s2, s4, s2
; GFX10-NEXT:    s_xor_b32 s2, s4, s2

; GFX10-NEXT:    v_mov_b32_e32 v1, s2
; GFX10-NEXT:    v_mov_b32_e32 v1, s2

; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]

; GFX10-NEXT:    s_endpgm
; GFX10-NEXT:    s_endpgm

;

; GFX8-GISEL-LABEL: s_bfi_sha256_ch:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c

; GFX8-GISEL-NEXT:    s_load_dword s4, s[0:1], 0x34

; GFX8-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24

; GFX8-GISEL-NEXT:    s_waitcnt lgkmcnt(0)

; GFX8-GISEL-NEXT:    s_xor_b32 s3, s3, s4

; GFX8-GISEL-NEXT:    s_and_b32 s2, s2, s3

; GFX8-GISEL-NEXT:    s_xor_b32 s2, s4, s2

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v0, s0

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v2, s2

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v1, s1

; GFX8-GISEL-NEXT:    flat_store_dword v[0:1], v2

; GFX8-GISEL-NEXT:    s_endpgm

;

; GFX10-GISEL-LABEL: s_bfi_sha256_ch:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    s_clause 0x2

; GFX10-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c

; GFX10-GISEL-NEXT:    s_load_dword s4, s[0:1], 0x34

; GFX10-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24

; GFX10-GISEL-NEXT:    v_mov_b32_e32 v1, 0

; GFX10-GISEL-NEXT:    s_waitcnt lgkmcnt(0)

; GFX10-GISEL-NEXT:    s_xor_b32 s3, s3, s4

; GFX10-GISEL-NEXT:    s_and_b32 s2, s2, s3

; GFX10-GISEL-NEXT:    s_xor_b32 s2, s4, s2

; GFX10-GISEL-NEXT:    v_mov_b32_e32 v0, s2

; GFX10-GISEL-NEXT:    global_store_dword v1, v0, s[0:1]

; GFX10-GISEL-NEXT:    s_endpgm

entry:
entry:

  %0 = xor i32 %y, %z
  %0 = xor i32 %y, %z

  %1 = and i32 %x, %0
  %1 = and i32 %x, %0

  %2 = xor i32 %z, %1
  %2 = xor i32 %z, %1

  store i32 %2, i32 addrspace(1)* %out
  store i32 %2, i32 addrspace(1)* %out

  ret void
  ret void

}
}




Show All 11 Lines
; GFX8-NEXT:    s_setpc_b64 s[30:31]
; GFX8-NEXT:    s_setpc_b64 s[30:31]

;
;

; GFX10-LABEL: v_bfi_sha256_ch:
; GFX10-LABEL: v_bfi_sha256_ch:

; GFX10:       ; %bb.0: ; %entry
; GFX10:       ; %bb.0: ; %entry

; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-NEXT:    v_bfi_b32 v0, v0, v1, v2
; GFX10-NEXT:    v_bfi_b32 v0, v0, v1, v2

; GFX10-NEXT:    s_setpc_b64 s[30:31]
; GFX10-NEXT:    s_setpc_b64 s[30:31]

;

; GFX8-GISEL-LABEL: v_bfi_sha256_ch:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-GISEL-NEXT:    v_bfi_b32 v0, v0, v1, v2

; GFX8-GISEL-NEXT:    s_setpc_b64 s[30:31]

;

; GFX10-GISEL-LABEL: v_bfi_sha256_ch:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX10-GISEL-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-GISEL-NEXT:    v_bfi_b32 v0, v0, v1, v2

; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]

entry:
entry:

  %0 = xor i32 %y, %z
  %0 = xor i32 %y, %z

  %1 = and i32 %x, %0
  %1 = and i32 %x, %0

  %2 = xor i32 %z, %1
  %2 = xor i32 %z, %1

  ret i32 %2
  ret i32 %2

}
}




define amdgpu_ps float @v_s_s_bfi_sha256_ch(i32 %x, i32 inreg %y, i32 inreg %z) {
define amdgpu_ps float @v_s_s_bfi_sha256_ch(i32 %x, i32 inreg %y, i32 inreg %z) {

; GFX7-LABEL: v_s_s_bfi_sha256_ch:
; GFX7-LABEL: v_s_s_bfi_sha256_ch:

; GFX7:       ; %bb.0: ; %entry
; GFX7:       ; %bb.0: ; %entry

; GFX7-NEXT:    v_mov_b32_e32 v1, s1
; GFX7-NEXT:    v_mov_b32_e32 v1, s1

; GFX7-NEXT:    v_bfi_b32 v0, v0, s0, v1
; GFX7-NEXT:    v_bfi_b32 v0, v0, s0, v1

; GFX7-NEXT:    ; return to shader part epilog
; GFX7-NEXT:    ; return to shader part epilog

;
;

; GFX8-LABEL: v_s_s_bfi_sha256_ch:
; GFX8-LABEL: v_s_s_bfi_sha256_ch:

; GFX8:       ; %bb.0: ; %entry
; GFX8:       ; %bb.0: ; %entry

; GFX8-NEXT:    v_mov_b32_e32 v1, s1
; GFX8-NEXT:    v_mov_b32_e32 v1, s1

; GFX8-NEXT:    v_bfi_b32 v0, v0, s0, v1
; GFX8-NEXT:    v_bfi_b32 v0, v0, s0, v1

; GFX8-NEXT:    ; return to shader part epilog
; GFX8-NEXT:    ; return to shader part epilog

;
;

; GFX10-LABEL: v_s_s_bfi_sha256_ch:
; GFX10-LABEL: v_s_s_bfi_sha256_ch:

; GFX10:       ; %bb.0: ; %entry
; GFX10:       ; %bb.0: ; %entry

; GFX10-NEXT:    v_bfi_b32 v0, v0, s0, s1
; GFX10-NEXT:    v_bfi_b32 v0, v0, s0, s1

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: v_s_s_bfi_sha256_ch:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    s_xor_b32 s0, s0, s1

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, s1, v0

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: v_s_s_bfi_sha256_ch:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    s_xor_b32 s0, s0, s1

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, s1, v0

; GFX10-GISEL-NEXT:    ; return to shader part epilog

entry:
entry:

  %xor0 = xor i32 %y, %z
  %xor0 = xor i32 %y, %z

  %and = and i32 %x, %xor0
  %and = and i32 %x, %xor0

  %xor1 = xor i32 %z, %and
  %xor1 = xor i32 %z, %and

  %cast = bitcast i32 %xor1 to float
  %cast = bitcast i32 %xor1 to float

  ret float %cast
  ret float %cast

}
}




Show All 9 Lines
; GFX8-NEXT:    v_mov_b32_e32 v1, s1
; GFX8-NEXT:    v_mov_b32_e32 v1, s1

; GFX8-NEXT:    v_bfi_b32 v0, s0, v0, v1
; GFX8-NEXT:    v_bfi_b32 v0, s0, v0, v1

; GFX8-NEXT:    ; return to shader part epilog
; GFX8-NEXT:    ; return to shader part epilog

;
;

; GFX10-LABEL: s_v_s_bfi_sha256_ch:
; GFX10-LABEL: s_v_s_bfi_sha256_ch:

; GFX10:       ; %bb.0: ; %entry
; GFX10:       ; %bb.0: ; %entry

; GFX10-NEXT:    v_bfi_b32 v0, s0, v0, s1
; GFX10-NEXT:    v_bfi_b32 v0, s0, v0, s1

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: s_v_s_bfi_sha256_ch:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, s1, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, s1, v0

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: s_v_s_bfi_sha256_ch:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, s1, v0

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, s1, v0

; GFX10-GISEL-NEXT:    ; return to shader part epilog

entry:
entry:

  %xor0 = xor i32 %y, %z
  %xor0 = xor i32 %y, %z

  %and = and i32 %x, %xor0
  %and = and i32 %x, %xor0

  %xor1 = xor i32 %z, %and
  %xor1 = xor i32 %z, %and

  %cast = bitcast i32 %xor1 to float
  %cast = bitcast i32 %xor1 to float

  ret float %cast
  ret float %cast

}
}




Show All 9 Lines
; GFX8-NEXT:    v_mov_b32_e32 v1, s1
; GFX8-NEXT:    v_mov_b32_e32 v1, s1

; GFX8-NEXT:    v_bfi_b32 v0, s0, v1, v0
; GFX8-NEXT:    v_bfi_b32 v0, s0, v1, v0

; GFX8-NEXT:    ; return to shader part epilog
; GFX8-NEXT:    ; return to shader part epilog

;
;

; GFX10-LABEL: s_s_v_bfi_sha256_ch:
; GFX10-LABEL: s_s_v_bfi_sha256_ch:

; GFX10:       ; %bb.0: ; %entry
; GFX10:       ; %bb.0: ; %entry

; GFX10-NEXT:    v_bfi_b32 v0, s0, s1, v0
; GFX10-NEXT:    v_bfi_b32 v0, s0, s1, v0

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: s_s_v_bfi_sha256_ch:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v1, s0

; GFX8-GISEL-NEXT:    v_bfi_b32 v0, v1, s1, v0

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: s_s_v_bfi_sha256_ch:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    v_bfi_b32 v0, s0, s1, v0

; GFX10-GISEL-NEXT:    ; return to shader part epilog

entry:
entry:

  %xor0 = xor i32 %y, %z
  %xor0 = xor i32 %y, %z

  %and = and i32 %x, %xor0
  %and = and i32 %x, %xor0

  %xor1 = xor i32 %z, %and
  %xor1 = xor i32 %z, %and

  %cast = bitcast i32 %xor1 to float
  %cast = bitcast i32 %xor1 to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps float @s_v_v_bfi_sha256_ch(i32 inreg %x, i32 %y, i32 %z) {
define amdgpu_ps float @s_v_v_bfi_sha256_ch(i32 inreg %x, i32 %y, i32 %z) {

; GFX7-LABEL: s_v_v_bfi_sha256_ch:
; GFX7-LABEL: s_v_v_bfi_sha256_ch:

; GFX7:       ; %bb.0: ; %entry
; GFX7:       ; %bb.0: ; %entry

; GFX7-NEXT:    v_bfi_b32 v0, s0, v0, v1
; GFX7-NEXT:    v_bfi_b32 v0, s0, v0, v1

; GFX7-NEXT:    ; return to shader part epilog
; GFX7-NEXT:    ; return to shader part epilog

;
;

; GFX8-LABEL: s_v_v_bfi_sha256_ch:
; GFX8-LABEL: s_v_v_bfi_sha256_ch:

; GFX8:       ; %bb.0: ; %entry
; GFX8:       ; %bb.0: ; %entry

; GFX8-NEXT:    v_bfi_b32 v0, s0, v0, v1
; GFX8-NEXT:    v_bfi_b32 v0, s0, v0, v1

; GFX8-NEXT:    ; return to shader part epilog
; GFX8-NEXT:    ; return to shader part epilog

;
;

; GFX10-LABEL: s_v_v_bfi_sha256_ch:
; GFX10-LABEL: s_v_v_bfi_sha256_ch:

; GFX10:       ; %bb.0: ; %entry
; GFX10:       ; %bb.0: ; %entry

; GFX10-NEXT:    v_bfi_b32 v0, s0, v0, v1
; GFX10-NEXT:    v_bfi_b32 v0, s0, v0, v1

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: s_v_v_bfi_sha256_ch:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    v_bfi_b32 v0, s0, v0, v1

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: s_v_v_bfi_sha256_ch:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    v_bfi_b32 v0, s0, v0, v1

; GFX10-GISEL-NEXT:    ; return to shader part epilog

entry:
entry:

  %xor0 = xor i32 %y, %z
  %xor0 = xor i32 %y, %z

  %and = and i32 %x, %xor0
  %and = and i32 %x, %xor0

  %xor1 = xor i32 %z, %and
  %xor1 = xor i32 %z, %and

  %cast = bitcast i32 %xor1 to float
  %cast = bitcast i32 %xor1 to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps float @v_s_v_bfi_sha256_ch(i32 %x, i32 inreg %y, i32 %z) {
define amdgpu_ps float @v_s_v_bfi_sha256_ch(i32 %x, i32 inreg %y, i32 %z) {

; GFX7-LABEL: v_s_v_bfi_sha256_ch:
; GFX7-LABEL: v_s_v_bfi_sha256_ch:

; GFX7:       ; %bb.0: ; %entry
; GFX7:       ; %bb.0: ; %entry

; GFX7-NEXT:    v_bfi_b32 v0, v0, s0, v1
; GFX7-NEXT:    v_bfi_b32 v0, v0, s0, v1

; GFX7-NEXT:    ; return to shader part epilog
; GFX7-NEXT:    ; return to shader part epilog

;
;

; GFX8-LABEL: v_s_v_bfi_sha256_ch:
; GFX8-LABEL: v_s_v_bfi_sha256_ch:

; GFX8:       ; %bb.0: ; %entry
; GFX8:       ; %bb.0: ; %entry

; GFX8-NEXT:    v_bfi_b32 v0, v0, s0, v1
; GFX8-NEXT:    v_bfi_b32 v0, v0, s0, v1

; GFX8-NEXT:    ; return to shader part epilog
; GFX8-NEXT:    ; return to shader part epilog

;
;

; GFX10-LABEL: v_s_v_bfi_sha256_ch:
; GFX10-LABEL: v_s_v_bfi_sha256_ch:

; GFX10:       ; %bb.0: ; %entry
; GFX10:       ; %bb.0: ; %entry

; GFX10-NEXT:    v_bfi_b32 v0, v0, s0, v1
; GFX10-NEXT:    v_bfi_b32 v0, v0, s0, v1

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: v_s_v_bfi_sha256_ch:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    v_bfi_b32 v0, v0, s0, v1

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: v_s_v_bfi_sha256_ch:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    v_bfi_b32 v0, v0, s0, v1

; GFX10-GISEL-NEXT:    ; return to shader part epilog

entry:
entry:

  %xor0 = xor i32 %y, %z
  %xor0 = xor i32 %y, %z

  %and = and i32 %x, %xor0
  %and = and i32 %x, %xor0

  %xor1 = xor i32 %z, %and
  %xor1 = xor i32 %z, %and

  %cast = bitcast i32 %xor1 to float
  %cast = bitcast i32 %xor1 to float

  ret float %cast
  ret float %cast

}
}




define amdgpu_ps float @v_v_s_bfi_sha256_ch(i32 %x, i32 %y, i32 inreg %z) {
define amdgpu_ps float @v_v_s_bfi_sha256_ch(i32 %x, i32 %y, i32 inreg %z) {

; GFX7-LABEL: v_v_s_bfi_sha256_ch:
; GFX7-LABEL: v_v_s_bfi_sha256_ch:

; GFX7:       ; %bb.0: ; %entry
; GFX7:       ; %bb.0: ; %entry

; GFX7-NEXT:    v_bfi_b32 v0, v0, v1, s0
; GFX7-NEXT:    v_bfi_b32 v0, v0, v1, s0

; GFX7-NEXT:    ; return to shader part epilog
; GFX7-NEXT:    ; return to shader part epilog

;
;

; GFX8-LABEL: v_v_s_bfi_sha256_ch:
; GFX8-LABEL: v_v_s_bfi_sha256_ch:

; GFX8:       ; %bb.0: ; %entry
; GFX8:       ; %bb.0: ; %entry

; GFX8-NEXT:    v_bfi_b32 v0, v0, v1, s0
; GFX8-NEXT:    v_bfi_b32 v0, v0, v1, s0

; GFX8-NEXT:    ; return to shader part epilog
; GFX8-NEXT:    ; return to shader part epilog

;
;

; GFX10-LABEL: v_v_s_bfi_sha256_ch:
; GFX10-LABEL: v_v_s_bfi_sha256_ch:

; GFX10:       ; %bb.0: ; %entry
; GFX10:       ; %bb.0: ; %entry

; GFX10-NEXT:    v_bfi_b32 v0, v0, v1, s0
; GFX10-NEXT:    v_bfi_b32 v0, v0, v1, s0

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: v_v_s_bfi_sha256_ch:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v1, s0, v1

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, v0, v1

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, s0, v0

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: v_v_s_bfi_sha256_ch:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v1, s0, v1

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, v0, v1

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, s0, v0

; GFX10-GISEL-NEXT:    ; return to shader part epilog

entry:
entry:

  %xor0 = xor i32 %y, %z
  %xor0 = xor i32 %y, %z

  %and = and i32 %x, %xor0
  %and = and i32 %x, %xor0

  %xor1 = xor i32 %z, %and
  %xor1 = xor i32 %z, %and

  %cast = bitcast i32 %xor1 to float
  %cast = bitcast i32 %xor1 to float

  ret float %cast
  ret float %cast

}
}




▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; GFX10-NEXT:    s_waitcnt lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt lgkmcnt(0)

; GFX10-NEXT:    s_or_b32 s5, s2, s4
; GFX10-NEXT:    s_or_b32 s5, s2, s4

; GFX10-NEXT:    s_and_b32 s2, s2, s4
; GFX10-NEXT:    s_and_b32 s2, s2, s4

; GFX10-NEXT:    s_and_b32 s3, s3, s5
; GFX10-NEXT:    s_and_b32 s3, s3, s5

; GFX10-NEXT:    s_or_b32 s2, s2, s3
; GFX10-NEXT:    s_or_b32 s2, s2, s3

; GFX10-NEXT:    v_mov_b32_e32 v1, s2
; GFX10-NEXT:    v_mov_b32_e32 v1, s2

; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]
; GFX10-NEXT:    global_store_dword v0, v1, s[0:1]

; GFX10-NEXT:    s_endpgm
; GFX10-NEXT:    s_endpgm

;

; GFX8-GISEL-LABEL: s_bfi_sha256_ma:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c

; GFX8-GISEL-NEXT:    s_load_dword s4, s[0:1], 0x34

; GFX8-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24

; GFX8-GISEL-NEXT:    s_waitcnt lgkmcnt(0)

; GFX8-GISEL-NEXT:    s_and_b32 s5, s2, s4

; GFX8-GISEL-NEXT:    s_or_b32 s2, s2, s4

; GFX8-GISEL-NEXT:    s_and_b32 s2, s3, s2

; GFX8-GISEL-NEXT:    s_or_b32 s2, s5, s2

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v0, s0

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v2, s2

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v1, s1

; GFX8-GISEL-NEXT:    flat_store_dword v[0:1], v2

; GFX8-GISEL-NEXT:    s_endpgm

;

; GFX10-GISEL-LABEL: s_bfi_sha256_ma:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    s_clause 0x2

; GFX10-GISEL-NEXT:    s_load_dwordx2 s[2:3], s[0:1], 0x2c

; GFX10-GISEL-NEXT:    s_load_dword s4, s[0:1], 0x34

; GFX10-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x24

; GFX10-GISEL-NEXT:    v_mov_b32_e32 v1, 0

; GFX10-GISEL-NEXT:    s_waitcnt lgkmcnt(0)

; GFX10-GISEL-NEXT:    s_or_b32 s5, s2, s4

; GFX10-GISEL-NEXT:    s_and_b32 s2, s2, s4

; GFX10-GISEL-NEXT:    s_and_b32 s3, s3, s5

; GFX10-GISEL-NEXT:    s_or_b32 s2, s2, s3

; GFX10-GISEL-NEXT:    v_mov_b32_e32 v0, s2

; GFX10-GISEL-NEXT:    global_store_dword v1, v0, s[0:1]

; GFX10-GISEL-NEXT:    s_endpgm

entry:
entry:

  %0 = and i32 %x, %z
  %0 = and i32 %x, %z

  %1 = or i32 %x, %z
  %1 = or i32 %x, %z

  %2 = and i32 %y, %1
  %2 = and i32 %y, %1

  %3 = or i32 %0, %2
  %3 = or i32 %0, %2

  store i32 %3, i32 addrspace(1)* %out
  store i32 %3, i32 addrspace(1)* %out

  ret void
  ret void

}
}

Show All 15 Lines
;
;

; GFX10-LABEL: v_bfi_sha256_ma:
; GFX10-LABEL: v_bfi_sha256_ma:

; GFX10:       ; %bb.0: ; %entry
; GFX10:       ; %bb.0: ; %entry

; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v1
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v1

; GFX10-NEXT:    v_bfi_b32 v0, v0, v2, v1
; GFX10-NEXT:    v_bfi_b32 v0, v0, v2, v1

; GFX10-NEXT:    s_setpc_b64 s[30:31]
; GFX10-NEXT:    s_setpc_b64 s[30:31]

;

; GFX8-GISEL-LABEL: v_bfi_sha256_ma:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v1

; GFX8-GISEL-NEXT:    v_bfi_b32 v0, v0, v2, v1

; GFX8-GISEL-NEXT:    s_setpc_b64 s[30:31]

;

; GFX10-GISEL-LABEL: v_bfi_sha256_ma:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX10-GISEL-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v1

; GFX10-GISEL-NEXT:    v_bfi_b32 v0, v0, v2, v1

; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]

entry:
entry:

  %0 = and i32 %x, %z
  %0 = and i32 %x, %z

  %1 = or i32 %x, %z
  %1 = or i32 %x, %z

  %2 = and i32 %y, %1
  %2 = and i32 %y, %1

  %3 = or i32 %0, %2
  %3 = or i32 %0, %2

  ret i32 %3
  ret i32 %3

}
}




Show All 14 Lines
;
;

; GFX10-LABEL: v_bitselect_v2i32_pat1:
; GFX10-LABEL: v_bitselect_v2i32_pat1:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-NEXT:    v_bfi_b32 v0, v2, v0, v4
; GFX10-NEXT:    v_bfi_b32 v0, v2, v0, v4

; GFX10-NEXT:    v_bfi_b32 v1, v3, v1, v5
; GFX10-NEXT:    v_bfi_b32 v1, v3, v1, v5

; GFX10-NEXT:    s_setpc_b64 s[30:31]
; GFX10-NEXT:    s_setpc_b64 s[30:31]

;

; GFX8-GISEL-LABEL: v_bitselect_v2i32_pat1:

; GFX8-GISEL:       ; %bb.0:

; GFX8-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v4

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v1, v1, v5

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, v0, v2

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, v1, v3

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v4

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v1, v1, v5

; GFX8-GISEL-NEXT:    s_setpc_b64 s[30:31]

;

; GFX10-GISEL-LABEL: v_bitselect_v2i32_pat1:

; GFX10-GISEL:       ; %bb.0:

; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX10-GISEL-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v4

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v1, v1, v5

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, v0, v2

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, v1, v3

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v4

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v1, v1, v5

; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]

  %xor.0 = xor <2 x i32> %a, %mask
  %xor.0 = xor <2 x i32> %a, %mask

  %and = and <2 x i32> %xor.0, %b
  %and = and <2 x i32> %xor.0, %b

  %bitselect = xor <2 x i32> %and, %mask
  %bitselect = xor <2 x i32> %and, %mask

  ret <2 x i32> %bitselect
  ret <2 x i32> %bitselect

}
}




define i64 @v_bitselect_i64_pat_0(i64 %a, i64 %b, i64 %mask) {
define i64 @v_bitselect_i64_pat_0(i64 %a, i64 %b, i64 %mask) {

; GFX7-LABEL: v_bitselect_i64_pat_0:
; GFX7-LABEL: v_bitselect_i64_pat_0:

Show All 12 Lines
;
;

; GFX10-LABEL: v_bitselect_i64_pat_0:
; GFX10-LABEL: v_bitselect_i64_pat_0:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-NEXT:    v_bfi_b32 v0, v0, v2, v4
; GFX10-NEXT:    v_bfi_b32 v0, v0, v2, v4

; GFX10-NEXT:    v_bfi_b32 v1, v1, v3, v5
; GFX10-NEXT:    v_bfi_b32 v1, v1, v3, v5

; GFX10-NEXT:    s_setpc_b64 s[30:31]
; GFX10-NEXT:    s_setpc_b64 s[30:31]

;

; GFX8-GISEL-LABEL: v_bitselect_i64_pat_0:

; GFX8-GISEL:       ; %bb.0:

; GFX8-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-GISEL-NEXT:    v_and_b32_e32 v2, v0, v2

; GFX8-GISEL-NEXT:    v_and_b32_e32 v3, v1, v3

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, -1, v0

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v1, -1, v1

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, v0, v4

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, v1, v5

; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, v2, v0

; GFX8-GISEL-NEXT:    v_or_b32_e32 v1, v3, v1

; GFX8-GISEL-NEXT:    s_setpc_b64 s[30:31]

;

; GFX10-GISEL-LABEL: v_bitselect_i64_pat_0:

; GFX10-GISEL:       ; %bb.0:

; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX10-GISEL-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v6, -1, v0

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v7, -1, v1

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, v0, v2

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, v1, v3

; GFX10-GISEL-NEXT:    v_and_b32_e32 v2, v6, v4

; GFX10-GISEL-NEXT:    v_and_b32_e32 v3, v7, v5

; GFX10-GISEL-NEXT:    v_or_b32_e32 v0, v0, v2

; GFX10-GISEL-NEXT:    v_or_b32_e32 v1, v1, v3

; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]

  %and0 = and i64 %a, %b
  %and0 = and i64 %a, %b

  %not.a = xor i64 %a, -1
  %not.a = xor i64 %a, -1

  %and1 = and i64 %not.a, %mask
  %and1 = and i64 %not.a, %mask

  %bitselect = or i64 %and0, %and1
  %bitselect = or i64 %and0, %and1

  ret i64 %bitselect
  ret i64 %bitselect

}
}




define amdgpu_ps <2 x float> @v_s_s_bitselect_i64_pat_0(i64 %a, i64 inreg %b, i64 inreg %mask) {
define amdgpu_ps <2 x float> @v_s_s_bitselect_i64_pat_0(i64 %a, i64 inreg %b, i64 inreg %mask) {

Show All 13 Lines
; GFX8-NEXT:    v_bfi_b32 v0, v0, s0, v2
; GFX8-NEXT:    v_bfi_b32 v0, v0, s0, v2

; GFX8-NEXT:    ; return to shader part epilog
; GFX8-NEXT:    ; return to shader part epilog

;
;

; GFX10-LABEL: v_s_s_bitselect_i64_pat_0:
; GFX10-LABEL: v_s_s_bitselect_i64_pat_0:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    v_bfi_b32 v0, v0, s0, s2
; GFX10-NEXT:    v_bfi_b32 v0, v0, s0, s2

; GFX10-NEXT:    v_bfi_b32 v1, v1, s1, s3
; GFX10-NEXT:    v_bfi_b32 v1, v1, s1, s3

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: v_s_s_bitselect_i64_pat_0:

; GFX8-GISEL:       ; %bb.0:

; GFX8-GISEL-NEXT:    v_and_b32_e32 v2, s0, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v3, s1, v1

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, -1, v0

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v1, -1, v1

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, s2, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, s3, v1

; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, v2, v0

; GFX8-GISEL-NEXT:    v_or_b32_e32 v1, v3, v1

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: v_s_s_bitselect_i64_pat_0:

; GFX10-GISEL:       ; %bb.0:

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v2, -1, v0

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v3, -1, v1

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, s1, v1

; GFX10-GISEL-NEXT:    v_and_b32_e32 v2, s2, v2

; GFX10-GISEL-NEXT:    v_and_b32_e32 v3, s3, v3

; GFX10-GISEL-NEXT:    v_or_b32_e32 v0, v0, v2

; GFX10-GISEL-NEXT:    v_or_b32_e32 v1, v1, v3

; GFX10-GISEL-NEXT:    ; return to shader part epilog

  %and0 = and i64 %a, %b
  %and0 = and i64 %a, %b

  %not.a = xor i64 %a, -1
  %not.a = xor i64 %a, -1

  %and1 = and i64 %not.a, %mask
  %and1 = and i64 %not.a, %mask

  %bitselect = or i64 %and0, %and1
  %bitselect = or i64 %and0, %and1

  %cast = bitcast i64 %bitselect to <2 x float>
  %cast = bitcast i64 %bitselect to <2 x float>

  ret <2 x float> %cast
  ret <2 x float> %cast

}
}




Show All 14 Lines
; GFX8-NEXT:    v_bfi_b32 v0, s0, v0, v2
; GFX8-NEXT:    v_bfi_b32 v0, s0, v0, v2

; GFX8-NEXT:    ; return to shader part epilog
; GFX8-NEXT:    ; return to shader part epilog

;
;

; GFX10-LABEL: s_v_s_bitselect_i64_pat_0:
; GFX10-LABEL: s_v_s_bitselect_i64_pat_0:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    v_bfi_b32 v0, s0, v0, s2
; GFX10-NEXT:    v_bfi_b32 v0, s0, v0, s2

; GFX10-NEXT:    v_bfi_b32 v1, s1, v1, s3
; GFX10-NEXT:    v_bfi_b32 v1, s1, v1, s3

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: s_v_s_bitselect_i64_pat_0:

; GFX8-GISEL:       ; %bb.0:

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, s1, v1

; GFX8-GISEL-NEXT:    s_andn2_b64 s[0:1], s[2:3], s[0:1]

; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, s0, v0

; GFX8-GISEL-NEXT:    v_or_b32_e32 v1, s1, v1

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: s_v_s_bitselect_i64_pat_0:

; GFX10-GISEL:       ; %bb.0:

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, s1, v1

; GFX10-GISEL-NEXT:    s_andn2_b64 s[0:1], s[2:3], s[0:1]

; GFX10-GISEL-NEXT:    v_or_b32_e32 v0, s0, v0

; GFX10-GISEL-NEXT:    v_or_b32_e32 v1, s1, v1

; GFX10-GISEL-NEXT:    ; return to shader part epilog

  %and0 = and i64 %a, %b
  %and0 = and i64 %a, %b

  %not.a = xor i64 %a, -1
  %not.a = xor i64 %a, -1

  %and1 = and i64 %not.a, %mask
  %and1 = and i64 %not.a, %mask

  %bitselect = or i64 %and0, %and1
  %bitselect = or i64 %and0, %and1

  %cast = bitcast i64 %bitselect to <2 x float>
  %cast = bitcast i64 %bitselect to <2 x float>

  ret <2 x float> %cast
  ret <2 x float> %cast

}
}




Show All 14 Lines
; GFX8-NEXT:    v_bfi_b32 v0, s0, v2, v0
; GFX8-NEXT:    v_bfi_b32 v0, s0, v2, v0

; GFX8-NEXT:    ; return to shader part epilog
; GFX8-NEXT:    ; return to shader part epilog

;
;

; GFX10-LABEL: s_s_v_bitselect_i64_pat_0:
; GFX10-LABEL: s_s_v_bitselect_i64_pat_0:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    v_bfi_b32 v0, s0, s2, v0
; GFX10-NEXT:    v_bfi_b32 v0, s0, s2, v0

; GFX10-NEXT:    v_bfi_b32 v1, s1, s3, v1
; GFX10-NEXT:    v_bfi_b32 v1, s1, s3, v1

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: s_s_v_bitselect_i64_pat_0:

; GFX8-GISEL:       ; %bb.0:

; GFX8-GISEL-NEXT:    s_and_b64 s[2:3], s[0:1], s[2:3]

; GFX8-GISEL-NEXT:    s_not_b64 s[0:1], s[0:1]

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, s1, v1

; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, s2, v0

; GFX8-GISEL-NEXT:    v_or_b32_e32 v1, s3, v1

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: s_s_v_bitselect_i64_pat_0:

; GFX10-GISEL:       ; %bb.0:

; GFX10-GISEL-NEXT:    s_not_b64 s[4:5], s[0:1]

; GFX10-GISEL-NEXT:    s_and_b64 s[0:1], s[0:1], s[2:3]

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, s4, v0

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, s5, v1

; GFX10-GISEL-NEXT:    v_or_b32_e32 v0, s0, v0

; GFX10-GISEL-NEXT:    v_or_b32_e32 v1, s1, v1

; GFX10-GISEL-NEXT:    ; return to shader part epilog

  %and0 = and i64 %a, %b
  %and0 = and i64 %a, %b

  %not.a = xor i64 %a, -1
  %not.a = xor i64 %a, -1

  %and1 = and i64 %not.a, %mask
  %and1 = and i64 %not.a, %mask

  %bitselect = or i64 %and0, %and1
  %bitselect = or i64 %and0, %and1

  %cast = bitcast i64 %bitselect to <2 x float>
  %cast = bitcast i64 %bitselect to <2 x float>

  ret <2 x float> %cast
  ret <2 x float> %cast

}
}




Show All 10 Lines
; GFX8-NEXT:    v_bfi_b32 v0, v0, v2, s0
; GFX8-NEXT:    v_bfi_b32 v0, v0, v2, s0

; GFX8-NEXT:    ; return to shader part epilog
; GFX8-NEXT:    ; return to shader part epilog

;
;

; GFX10-LABEL: v_v_s_bitselect_i64_pat_0:
; GFX10-LABEL: v_v_s_bitselect_i64_pat_0:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    v_bfi_b32 v0, v0, v2, s0
; GFX10-NEXT:    v_bfi_b32 v0, v0, v2, s0

; GFX10-NEXT:    v_bfi_b32 v1, v1, v3, s1
; GFX10-NEXT:    v_bfi_b32 v1, v1, v3, s1

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: v_v_s_bitselect_i64_pat_0:

; GFX8-GISEL:       ; %bb.0:

; GFX8-GISEL-NEXT:    v_and_b32_e32 v2, v0, v2

; GFX8-GISEL-NEXT:    v_and_b32_e32 v3, v1, v3

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, -1, v0

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v1, -1, v1

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, s1, v1

; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, v2, v0

; GFX8-GISEL-NEXT:    v_or_b32_e32 v1, v3, v1

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: v_v_s_bitselect_i64_pat_0:

; GFX10-GISEL:       ; %bb.0:

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v4, -1, v0

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v5, -1, v1

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, v0, v2

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, v1, v3

; GFX10-GISEL-NEXT:    v_and_b32_e32 v2, s0, v4

; GFX10-GISEL-NEXT:    v_and_b32_e32 v3, s1, v5

; GFX10-GISEL-NEXT:    v_or_b32_e32 v0, v0, v2

; GFX10-GISEL-NEXT:    v_or_b32_e32 v1, v1, v3

; GFX10-GISEL-NEXT:    ; return to shader part epilog

  %and0 = and i64 %a, %b
  %and0 = and i64 %a, %b

  %not.a = xor i64 %a, -1
  %not.a = xor i64 %a, -1

  %and1 = and i64 %not.a, %mask
  %and1 = and i64 %not.a, %mask

  %bitselect = or i64 %and0, %and1
  %bitselect = or i64 %and0, %and1

  %cast = bitcast i64 %bitselect to <2 x float>
  %cast = bitcast i64 %bitselect to <2 x float>

  ret <2 x float> %cast
  ret <2 x float> %cast

}
}




Show All 10 Lines
; GFX8-NEXT:    v_bfi_b32 v0, v0, s0, v2
; GFX8-NEXT:    v_bfi_b32 v0, v0, s0, v2

; GFX8-NEXT:    ; return to shader part epilog
; GFX8-NEXT:    ; return to shader part epilog

;
;

; GFX10-LABEL: v_s_v_bitselect_i64_pat_0:
; GFX10-LABEL: v_s_v_bitselect_i64_pat_0:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    v_bfi_b32 v0, v0, s0, v2
; GFX10-NEXT:    v_bfi_b32 v0, v0, s0, v2

; GFX10-NEXT:    v_bfi_b32 v1, v1, s1, v3
; GFX10-NEXT:    v_bfi_b32 v1, v1, s1, v3

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: v_s_v_bitselect_i64_pat_0:

; GFX8-GISEL:       ; %bb.0:

; GFX8-GISEL-NEXT:    v_and_b32_e32 v4, s0, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v5, s1, v1

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, -1, v0

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v1, -1, v1

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, v0, v2

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, v1, v3

; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, v4, v0

; GFX8-GISEL-NEXT:    v_or_b32_e32 v1, v5, v1

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: v_s_v_bitselect_i64_pat_0:

; GFX10-GISEL:       ; %bb.0:

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v4, -1, v0

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v5, -1, v1

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, s1, v1

; GFX10-GISEL-NEXT:    v_and_b32_e32 v2, v4, v2

; GFX10-GISEL-NEXT:    v_and_b32_e32 v3, v5, v3

; GFX10-GISEL-NEXT:    v_or_b32_e32 v0, v0, v2

; GFX10-GISEL-NEXT:    v_or_b32_e32 v1, v1, v3

; GFX10-GISEL-NEXT:    ; return to shader part epilog

  %and0 = and i64 %a, %b
  %and0 = and i64 %a, %b

  %not.a = xor i64 %a, -1
  %not.a = xor i64 %a, -1

  %and1 = and i64 %not.a, %mask
  %and1 = and i64 %not.a, %mask

  %bitselect = or i64 %and0, %and1
  %bitselect = or i64 %and0, %and1

  %cast = bitcast i64 %bitselect to <2 x float>
  %cast = bitcast i64 %bitselect to <2 x float>

  ret <2 x float> %cast
  ret <2 x float> %cast

}
}




Show All 10 Lines
; GFX8-NEXT:    v_bfi_b32 v0, s0, v0, v2
; GFX8-NEXT:    v_bfi_b32 v0, s0, v0, v2

; GFX8-NEXT:    ; return to shader part epilog
; GFX8-NEXT:    ; return to shader part epilog

;
;

; GFX10-LABEL: s_v_v_bitselect_i64_pat_0:
; GFX10-LABEL: s_v_v_bitselect_i64_pat_0:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    v_bfi_b32 v0, s0, v0, v2
; GFX10-NEXT:    v_bfi_b32 v0, s0, v0, v2

; GFX10-NEXT:    v_bfi_b32 v1, s1, v1, v3
; GFX10-NEXT:    v_bfi_b32 v1, s1, v1, v3

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: s_v_v_bitselect_i64_pat_0:

; GFX8-GISEL:       ; %bb.0:

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, s1, v1

; GFX8-GISEL-NEXT:    s_not_b64 s[0:1], s[0:1]

; GFX8-GISEL-NEXT:    v_and_b32_e32 v2, s0, v2

; GFX8-GISEL-NEXT:    v_and_b32_e32 v3, s1, v3

; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, v0, v2

; GFX8-GISEL-NEXT:    v_or_b32_e32 v1, v1, v3

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: s_v_v_bitselect_i64_pat_0:

; GFX10-GISEL:       ; %bb.0:

; GFX10-GISEL-NEXT:    s_not_b64 s[2:3], s[0:1]

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, s1, v1

; GFX10-GISEL-NEXT:    v_and_b32_e32 v2, s2, v2

; GFX10-GISEL-NEXT:    v_and_b32_e32 v3, s3, v3

; GFX10-GISEL-NEXT:    v_or_b32_e32 v0, v0, v2

; GFX10-GISEL-NEXT:    v_or_b32_e32 v1, v1, v3

; GFX10-GISEL-NEXT:    ; return to shader part epilog

  %and0 = and i64 %a, %b
  %and0 = and i64 %a, %b

  %not.a = xor i64 %a, -1
  %not.a = xor i64 %a, -1

  %and1 = and i64 %not.a, %mask
  %and1 = and i64 %not.a, %mask

  %bitselect = or i64 %and0, %and1
  %bitselect = or i64 %and0, %and1

  %cast = bitcast i64 %bitselect to <2 x float>
  %cast = bitcast i64 %bitselect to <2 x float>

  ret <2 x float> %cast
  ret <2 x float> %cast

}
}




Show All 14 Lines
;
;

; GFX10-LABEL: v_bitselect_i64_pat_1:
; GFX10-LABEL: v_bitselect_i64_pat_1:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-NEXT:    v_bfi_b32 v0, v2, v0, v4
; GFX10-NEXT:    v_bfi_b32 v0, v2, v0, v4

; GFX10-NEXT:    v_bfi_b32 v1, v3, v1, v5
; GFX10-NEXT:    v_bfi_b32 v1, v3, v1, v5

; GFX10-NEXT:    s_setpc_b64 s[30:31]
; GFX10-NEXT:    s_setpc_b64 s[30:31]

;

; GFX8-GISEL-LABEL: v_bitselect_i64_pat_1:

; GFX8-GISEL:       ; %bb.0:

; GFX8-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v4

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v1, v1, v5

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, v0, v2

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, v1, v3

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v4

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v1, v1, v5

; GFX8-GISEL-NEXT:    s_setpc_b64 s[30:31]

;

; GFX10-GISEL-LABEL: v_bitselect_i64_pat_1:

; GFX10-GISEL:       ; %bb.0:

; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX10-GISEL-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v4

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v1, v1, v5

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, v0, v2

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, v1, v3

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v4

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v1, v1, v5

; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]

  %xor.0 = xor i64 %a, %mask
  %xor.0 = xor i64 %a, %mask

  %and = and i64 %xor.0, %b
  %and = and i64 %xor.0, %b

  %bitselect = xor i64 %and, %mask
  %bitselect = xor i64 %and, %mask

  ret i64 %bitselect
  ret i64 %bitselect

}
}




define amdgpu_ps <2 x float> @v_s_s_bitselect_i64_pat_1(i64 %a, i64 inreg %b, i64 inreg %mask) {
define amdgpu_ps <2 x float> @v_s_s_bitselect_i64_pat_1(i64 %a, i64 inreg %b, i64 inreg %mask) {

; GFX7-LABEL: v_s_s_bitselect_i64_pat_1:
; GFX7-LABEL: v_s_s_bitselect_i64_pat_1:

Show All 12 Lines
; GFX8-NEXT:    v_bfi_b32 v0, s0, v0, v2
; GFX8-NEXT:    v_bfi_b32 v0, s0, v0, v2

; GFX8-NEXT:    ; return to shader part epilog
; GFX8-NEXT:    ; return to shader part epilog

;
;

; GFX10-LABEL: v_s_s_bitselect_i64_pat_1:
; GFX10-LABEL: v_s_s_bitselect_i64_pat_1:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    v_bfi_b32 v0, s0, v0, s2
; GFX10-NEXT:    v_bfi_b32 v0, s0, v0, s2

; GFX10-NEXT:    v_bfi_b32 v1, s1, v1, s3
; GFX10-NEXT:    v_bfi_b32 v1, s1, v1, s3

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: v_s_s_bitselect_i64_pat_1:

; GFX8-GISEL:       ; %bb.0:

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, s2, v0

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v1, s3, v1

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, s1, v1

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, s2, v0

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v1, s3, v1

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: v_s_s_bitselect_i64_pat_1:

; GFX10-GISEL:       ; %bb.0:

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, s2, v0

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v1, s3, v1

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, s1, v1

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, s2, v0

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v1, s3, v1

; GFX10-GISEL-NEXT:    ; return to shader part epilog

  %xor.0 = xor i64 %a, %mask
  %xor.0 = xor i64 %a, %mask

  %and = and i64 %xor.0, %b
  %and = and i64 %xor.0, %b

  %bitselect = xor i64 %and, %mask
  %bitselect = xor i64 %and, %mask

  %cast = bitcast i64 %bitselect to <2 x float>
  %cast = bitcast i64 %bitselect to <2 x float>

  ret <2 x float> %cast
  ret <2 x float> %cast

}
}




define amdgpu_ps <2 x float> @s_s_v_bitselect_i64_pat_1(i64 inreg %a, i64 inreg %b, i64 %mask) {
define amdgpu_ps <2 x float> @s_s_v_bitselect_i64_pat_1(i64 inreg %a, i64 inreg %b, i64 %mask) {

Show All 13 Lines
; GFX8-NEXT:    v_bfi_b32 v0, s2, v2, v0
; GFX8-NEXT:    v_bfi_b32 v0, s2, v2, v0

; GFX8-NEXT:    ; return to shader part epilog
; GFX8-NEXT:    ; return to shader part epilog

;
;

; GFX10-LABEL: s_s_v_bitselect_i64_pat_1:
; GFX10-LABEL: s_s_v_bitselect_i64_pat_1:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    v_bfi_b32 v0, s2, s0, v0
; GFX10-NEXT:    v_bfi_b32 v0, s2, s0, v0

; GFX10-NEXT:    v_bfi_b32 v1, s3, s1, v1
; GFX10-NEXT:    v_bfi_b32 v1, s3, s1, v1

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: s_s_v_bitselect_i64_pat_1:

; GFX8-GISEL:       ; %bb.0:

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v2, s0, v0

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v3, s1, v1

; GFX8-GISEL-NEXT:    v_and_b32_e32 v2, s2, v2

; GFX8-GISEL-NEXT:    v_and_b32_e32 v3, s3, v3

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, v2, v0

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v1, v3, v1

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: s_s_v_bitselect_i64_pat_1:

; GFX10-GISEL:       ; %bb.0:

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v2, s0, v0

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v3, s1, v1

; GFX10-GISEL-NEXT:    v_and_b32_e32 v2, s2, v2

; GFX10-GISEL-NEXT:    v_and_b32_e32 v3, s3, v3

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, v2, v0

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v1, v3, v1

; GFX10-GISEL-NEXT:    ; return to shader part epilog

  %xor.0 = xor i64 %a, %mask
  %xor.0 = xor i64 %a, %mask

  %and = and i64 %xor.0, %b
  %and = and i64 %xor.0, %b

  %bitselect = xor i64 %and, %mask
  %bitselect = xor i64 %and, %mask

  %cast = bitcast i64 %bitselect to <2 x float>
  %cast = bitcast i64 %bitselect to <2 x float>

  ret <2 x float> %cast
  ret <2 x float> %cast

}
}




define amdgpu_ps <2 x float> @s_v_s_bitselect_i64_pat_1(i64 inreg %a, i64 %b, i64 inreg %mask) {
define amdgpu_ps <2 x float> @s_v_s_bitselect_i64_pat_1(i64 inreg %a, i64 %b, i64 inreg %mask) {

Show All 13 Lines
; GFX8-NEXT:    v_bfi_b32 v0, v0, s0, v2
; GFX8-NEXT:    v_bfi_b32 v0, v0, s0, v2

; GFX8-NEXT:    ; return to shader part epilog
; GFX8-NEXT:    ; return to shader part epilog

;
;

; GFX10-LABEL: s_v_s_bitselect_i64_pat_1:
; GFX10-LABEL: s_v_s_bitselect_i64_pat_1:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    v_bfi_b32 v0, v0, s0, s2
; GFX10-NEXT:    v_bfi_b32 v0, v0, s0, s2

; GFX10-NEXT:    v_bfi_b32 v1, v1, s1, s3
; GFX10-NEXT:    v_bfi_b32 v1, v1, s1, s3

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: s_v_s_bitselect_i64_pat_1:

; GFX8-GISEL:       ; %bb.0:

; GFX8-GISEL-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, s1, v1

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, s2, v0

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v1, s3, v1

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: s_v_s_bitselect_i64_pat_1:

; GFX10-GISEL:       ; %bb.0:

; GFX10-GISEL-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, s1, v1

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, s2, v0

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v1, s3, v1

; GFX10-GISEL-NEXT:    ; return to shader part epilog

  %xor.0 = xor i64 %a, %mask
  %xor.0 = xor i64 %a, %mask

  %and = and i64 %xor.0, %b
  %and = and i64 %xor.0, %b

  %bitselect = xor i64 %and, %mask
  %bitselect = xor i64 %and, %mask

  %cast = bitcast i64 %bitselect to <2 x float>
  %cast = bitcast i64 %bitselect to <2 x float>

  ret <2 x float> %cast
  ret <2 x float> %cast

}
}




define i64 @v_bitselect_i64_pat_2(i64 %a, i64 %b, i64 %mask) {
define i64 @v_bitselect_i64_pat_2(i64 %a, i64 %b, i64 %mask) {

Show All 13 Lines
;
;

; GFX10-LABEL: v_bitselect_i64_pat_2:
; GFX10-LABEL: v_bitselect_i64_pat_2:

; GFX10:       ; %bb.0:
; GFX10:       ; %bb.0:

; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-NEXT:    v_bfi_b32 v0, v2, v0, v4
; GFX10-NEXT:    v_bfi_b32 v0, v2, v0, v4

; GFX10-NEXT:    v_bfi_b32 v1, v3, v1, v5
; GFX10-NEXT:    v_bfi_b32 v1, v3, v1, v5

; GFX10-NEXT:    s_setpc_b64 s[30:31]
; GFX10-NEXT:    s_setpc_b64 s[30:31]

;

; GFX8-GISEL-LABEL: v_bitselect_i64_pat_2:

; GFX8-GISEL:       ; %bb.0:

; GFX8-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v4

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v1, v1, v5

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, v0, v2

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, v1, v3

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v4

; GFX8-GISEL-NEXT:    v_xor_b32_e32 v1, v1, v5

; GFX8-GISEL-NEXT:    s_setpc_b64 s[30:31]

;

; GFX10-GISEL-LABEL: v_bitselect_i64_pat_2:

; GFX10-GISEL:       ; %bb.0:

; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX10-GISEL-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v4

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v1, v1, v5

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, v0, v2

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, v1, v3

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v0, v0, v4

; GFX10-GISEL-NEXT:    v_xor_b32_e32 v1, v1, v5

; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]

  %xor.0 = xor i64 %a, %mask
  %xor.0 = xor i64 %a, %mask

  %and = and i64 %xor.0, %b
  %and = and i64 %xor.0, %b

  %bitselect = xor i64 %and, %mask
  %bitselect = xor i64 %and, %mask

  ret i64 %bitselect
  ret i64 %bitselect

}
}




define i64 @v_bfi_sha256_ma_i64(i64 %x, i64 %y, i64 %z) {
define i64 @v_bfi_sha256_ma_i64(i64 %x, i64 %y, i64 %z) {

; GFX7-LABEL: v_bfi_sha256_ma_i64:
; GFX7-LABEL: v_bfi_sha256_ma_i64:

Show All 18 Lines
; GFX10:       ; %bb.0: ; %entry
; GFX10:       ; %bb.0: ; %entry

; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0
; GFX10-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v2
; GFX10-NEXT:    v_xor_b32_e32 v0, v0, v2

; GFX10-NEXT:    v_xor_b32_e32 v1, v1, v3
; GFX10-NEXT:    v_xor_b32_e32 v1, v1, v3

; GFX10-NEXT:    v_bfi_b32 v0, v0, v4, v2
; GFX10-NEXT:    v_bfi_b32 v0, v0, v4, v2

; GFX10-NEXT:    v_bfi_b32 v1, v1, v5, v3
; GFX10-NEXT:    v_bfi_b32 v1, v1, v5, v3

; GFX10-NEXT:    s_setpc_b64 s[30:31]
; GFX10-NEXT:    s_setpc_b64 s[30:31]

;

; GFX8-GISEL-LABEL: v_bfi_sha256_ma_i64:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX8-GISEL-NEXT:    v_and_b32_e32 v6, v0, v4

; GFX8-GISEL-NEXT:    v_and_b32_e32 v7, v1, v5

; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, v0, v4

; GFX8-GISEL-NEXT:    v_or_b32_e32 v1, v1, v5

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, v2, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, v3, v1

; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, v6, v0

; GFX8-GISEL-NEXT:    v_or_b32_e32 v1, v7, v1

; GFX8-GISEL-NEXT:    s_setpc_b64 s[30:31]

;

; GFX10-GISEL-LABEL: v_bfi_sha256_ma_i64:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)

; GFX10-GISEL-NEXT:    s_waitcnt_vscnt null, 0x0

; GFX10-GISEL-NEXT:    v_or_b32_e32 v6, v0, v4

; GFX10-GISEL-NEXT:    v_or_b32_e32 v7, v1, v5

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, v0, v4

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, v1, v5

; GFX10-GISEL-NEXT:    v_and_b32_e32 v2, v2, v6

; GFX10-GISEL-NEXT:    v_and_b32_e32 v3, v3, v7

; GFX10-GISEL-NEXT:    v_or_b32_e32 v0, v0, v2

; GFX10-GISEL-NEXT:    v_or_b32_e32 v1, v1, v3

; GFX10-GISEL-NEXT:    s_setpc_b64 s[30:31]

entry:
entry:

  %and0 = and i64 %x, %z
  %and0 = and i64 %x, %z

  %or0 = or i64 %x, %z
  %or0 = or i64 %x, %z

  %and1 = and i64 %y, %or0
  %and1 = and i64 %y, %or0

  %or1 = or i64 %and0, %and1
  %or1 = or i64 %and0, %and1

  ret i64 %or1
  ret i64 %or1

}
}




Show All 20 Lines
;
;

; GFX10-LABEL: v_s_s_bfi_sha256_ma_i64:
; GFX10-LABEL: v_s_s_bfi_sha256_ma_i64:

; GFX10:       ; %bb.0: ; %entry
; GFX10:       ; %bb.0: ; %entry

; GFX10-NEXT:    v_xor_b32_e32 v0, s0, v0
; GFX10-NEXT:    v_xor_b32_e32 v0, s0, v0

; GFX10-NEXT:    v_xor_b32_e32 v1, s1, v1
; GFX10-NEXT:    v_xor_b32_e32 v1, s1, v1

; GFX10-NEXT:    v_bfi_b32 v0, v0, s2, s0
; GFX10-NEXT:    v_bfi_b32 v0, v0, s2, s0

; GFX10-NEXT:    v_bfi_b32 v1, v1, s3, s1
; GFX10-NEXT:    v_bfi_b32 v1, v1, s3, s1

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: v_s_s_bfi_sha256_ma_i64:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    v_and_b32_e32 v2, s2, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v3, s3, v1

; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, s2, v0

; GFX8-GISEL-NEXT:    v_or_b32_e32 v1, s3, v1

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, s1, v1

; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, v2, v0

; GFX8-GISEL-NEXT:    v_or_b32_e32 v1, v3, v1

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: v_s_s_bfi_sha256_ma_i64:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    v_or_b32_e32 v2, s2, v0

; GFX10-GISEL-NEXT:    v_or_b32_e32 v3, s3, v1

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, s2, v0

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, s3, v1

; GFX10-GISEL-NEXT:    v_and_b32_e32 v2, s0, v2

; GFX10-GISEL-NEXT:    v_and_b32_e32 v3, s1, v3

; GFX10-GISEL-NEXT:    v_or_b32_e32 v0, v0, v2

; GFX10-GISEL-NEXT:    v_or_b32_e32 v1, v1, v3

; GFX10-GISEL-NEXT:    ; return to shader part epilog

entry:
entry:

  %and0 = and i64 %x, %z
  %and0 = and i64 %x, %z

  %or0 = or i64 %x, %z
  %or0 = or i64 %x, %z

  %and1 = and i64 %y, %or0
  %and1 = and i64 %y, %or0

  %or1 = or i64 %and0, %and1
  %or1 = or i64 %and0, %and1

  %cast = bitcast i64 %or1 to <2 x float>
  %cast = bitcast i64 %or1 to <2 x float>

  ret <2 x float> %cast
  ret <2 x float> %cast

}
}

Show All 17 Lines
;
;

; GFX10-LABEL: s_v_s_bfi_sha256_ma_i64:
; GFX10-LABEL: s_v_s_bfi_sha256_ma_i64:

; GFX10:       ; %bb.0: ; %entry
; GFX10:       ; %bb.0: ; %entry

; GFX10-NEXT:    v_xor_b32_e32 v2, s0, v0
; GFX10-NEXT:    v_xor_b32_e32 v2, s0, v0

; GFX10-NEXT:    v_xor_b32_e32 v3, s1, v1
; GFX10-NEXT:    v_xor_b32_e32 v3, s1, v1

; GFX10-NEXT:    v_bfi_b32 v0, v2, s2, v0
; GFX10-NEXT:    v_bfi_b32 v0, v2, s2, v0

; GFX10-NEXT:    v_bfi_b32 v1, v3, s3, v1
; GFX10-NEXT:    v_bfi_b32 v1, v3, s3, v1

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: s_v_s_bfi_sha256_ma_i64:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    s_and_b64 s[4:5], s[0:1], s[2:3]

; GFX8-GISEL-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, s1, v1

; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, s4, v0

; GFX8-GISEL-NEXT:    v_or_b32_e32 v1, s5, v1

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: s_v_s_bfi_sha256_ma_i64:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    s_or_b64 s[4:5], s[0:1], s[2:3]

; GFX10-GISEL-NEXT:    s_and_b64 s[0:1], s[0:1], s[2:3]

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, s4, v0

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, s5, v1

; GFX10-GISEL-NEXT:    v_or_b32_e32 v0, s0, v0

; GFX10-GISEL-NEXT:    v_or_b32_e32 v1, s1, v1

; GFX10-GISEL-NEXT:    ; return to shader part epilog

entry:
entry:

  %and0 = and i64 %x, %z
  %and0 = and i64 %x, %z

  %or0 = or i64 %x, %z
  %or0 = or i64 %x, %z

  %and1 = and i64 %y, %or0
  %and1 = and i64 %y, %or0

  %or1 = or i64 %and0, %and1
  %or1 = or i64 %and0, %and1

  %cast = bitcast i64 %or1 to <2 x float>
  %cast = bitcast i64 %or1 to <2 x float>

  ret <2 x float> %cast
  ret <2 x float> %cast

}
}

Show All 21 Lines
;
;

; GFX10-LABEL: s_s_v_bfi_sha256_ma_i64:
; GFX10-LABEL: s_s_v_bfi_sha256_ma_i64:

; GFX10:       ; %bb.0: ; %entry
; GFX10:       ; %bb.0: ; %entry

; GFX10-NEXT:    v_xor_b32_e64 v2, s0, s2
; GFX10-NEXT:    v_xor_b32_e64 v2, s0, s2

; GFX10-NEXT:    v_xor_b32_e64 v3, s1, s3
; GFX10-NEXT:    v_xor_b32_e64 v3, s1, s3

; GFX10-NEXT:    v_bfi_b32 v0, v2, v0, s2
; GFX10-NEXT:    v_bfi_b32 v0, v2, v0, s2

; GFX10-NEXT:    v_bfi_b32 v1, v3, v1, s3
; GFX10-NEXT:    v_bfi_b32 v1, v3, v1, s3

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: s_s_v_bfi_sha256_ma_i64:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    v_and_b32_e32 v2, s0, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v3, s1, v1

; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, s0, v0

; GFX8-GISEL-NEXT:    v_or_b32_e32 v1, s1, v1

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, s2, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, s3, v1

; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, v2, v0

; GFX8-GISEL-NEXT:    v_or_b32_e32 v1, v3, v1

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: s_s_v_bfi_sha256_ma_i64:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    v_or_b32_e32 v2, s0, v0

; GFX10-GISEL-NEXT:    v_or_b32_e32 v3, s1, v1

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, s1, v1

; GFX10-GISEL-NEXT:    v_and_b32_e32 v2, s2, v2

; GFX10-GISEL-NEXT:    v_and_b32_e32 v3, s3, v3

; GFX10-GISEL-NEXT:    v_or_b32_e32 v0, v0, v2

; GFX10-GISEL-NEXT:    v_or_b32_e32 v1, v1, v3

; GFX10-GISEL-NEXT:    ; return to shader part epilog

entry:
entry:

  %and0 = and i64 %x, %z
  %and0 = and i64 %x, %z

  %or0 = or i64 %x, %z
  %or0 = or i64 %x, %z

  %and1 = and i64 %y, %or0
  %and1 = and i64 %y, %or0

  %or1 = or i64 %and0, %and1
  %or1 = or i64 %and0, %and1

  %cast = bitcast i64 %or1 to <2 x float>
  %cast = bitcast i64 %or1 to <2 x float>

  ret <2 x float> %cast
  ret <2 x float> %cast

}
}

Show All 17 Lines
;
;

; GFX10-LABEL: v_s_v_bfi_sha256_ma_i64:
; GFX10-LABEL: v_s_v_bfi_sha256_ma_i64:

; GFX10:       ; %bb.0: ; %entry
; GFX10:       ; %bb.0: ; %entry

; GFX10-NEXT:    v_xor_b32_e32 v0, s0, v0
; GFX10-NEXT:    v_xor_b32_e32 v0, s0, v0

; GFX10-NEXT:    v_xor_b32_e32 v1, s1, v1
; GFX10-NEXT:    v_xor_b32_e32 v1, s1, v1

; GFX10-NEXT:    v_bfi_b32 v0, v0, v2, s0
; GFX10-NEXT:    v_bfi_b32 v0, v0, v2, s0

; GFX10-NEXT:    v_bfi_b32 v1, v1, v3, s1
; GFX10-NEXT:    v_bfi_b32 v1, v1, v3, s1

; GFX10-NEXT:    ; return to shader part epilog
; GFX10-NEXT:    ; return to shader part epilog

;

; GFX8-GISEL-LABEL: v_s_v_bfi_sha256_ma_i64:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    v_and_b32_e32 v4, v0, v2

; GFX8-GISEL-NEXT:    v_and_b32_e32 v5, v1, v3

; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, v0, v2

; GFX8-GISEL-NEXT:    v_or_b32_e32 v1, v1, v3

; GFX8-GISEL-NEXT:    v_and_b32_e32 v0, s0, v0

; GFX8-GISEL-NEXT:    v_and_b32_e32 v1, s1, v1

; GFX8-GISEL-NEXT:    v_or_b32_e32 v0, v4, v0

; GFX8-GISEL-NEXT:    v_or_b32_e32 v1, v5, v1

; GFX8-GISEL-NEXT:    ; return to shader part epilog

;

; GFX10-GISEL-LABEL: v_s_v_bfi_sha256_ma_i64:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    v_or_b32_e32 v4, v0, v2

; GFX10-GISEL-NEXT:    v_or_b32_e32 v5, v1, v3

; GFX10-GISEL-NEXT:    v_and_b32_e32 v0, v0, v2

; GFX10-GISEL-NEXT:    v_and_b32_e32 v1, v1, v3

; GFX10-GISEL-NEXT:    v_and_b32_e32 v2, s0, v4

; GFX10-GISEL-NEXT:    v_and_b32_e32 v3, s1, v5

; GFX10-GISEL-NEXT:    v_or_b32_e32 v0, v0, v2

; GFX10-GISEL-NEXT:    v_or_b32_e32 v1, v1, v3

; GFX10-GISEL-NEXT:    ; return to shader part epilog

entry:
entry:

  %and0 = and i64 %x, %z
  %and0 = and i64 %x, %z

  %or0 = or i64 %x, %z
  %or0 = or i64 %x, %z

  %and1 = and i64 %y, %or0
  %and1 = and i64 %y, %or0

  %or1 = or i64 %and0, %and1
  %or1 = or i64 %and0, %and1

  %cast = bitcast i64 %or1 to <2 x float>
  %cast = bitcast i64 %or1 to <2 x float>

  ret <2 x float> %cast
  ret <2 x float> %cast

}
}

▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; GFX10-NEXT:    s_andn2_b64 s[0:1], s[0:1], s[4:5]
; GFX10-NEXT:    s_andn2_b64 s[0:1], s[0:1], s[4:5]

; GFX10-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]
; GFX10-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]

; GFX10-NEXT:    s_add_u32 s0, s0, 10
; GFX10-NEXT:    s_add_u32 s0, s0, 10

; GFX10-NEXT:    s_addc_u32 s1, s1, 0
; GFX10-NEXT:    s_addc_u32 s1, s1, 0

; GFX10-NEXT:    v_mov_b32_e32 v0, s0
; GFX10-NEXT:    v_mov_b32_e32 v0, s0

; GFX10-NEXT:    v_mov_b32_e32 v1, s1
; GFX10-NEXT:    v_mov_b32_e32 v1, s1

; GFX10-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off

; GFX10-NEXT:    s_endpgm
; GFX10-NEXT:    s_endpgm

;

; GFX8-GISEL-LABEL: s_bitselect_i64_pat_0:

; GFX8-GISEL:       ; %bb.0:

; GFX8-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24

; GFX8-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34

; GFX8-GISEL-NEXT:    s_waitcnt lgkmcnt(0)

; GFX8-GISEL-NEXT:    s_and_b64 s[2:3], s[4:5], s[6:7]

; GFX8-GISEL-NEXT:    s_andn2_b64 s[0:1], s[0:1], s[4:5]

; GFX8-GISEL-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]

; GFX8-GISEL-NEXT:    s_add_u32 s0, s0, 10

; GFX8-GISEL-NEXT:    s_cselect_b32 s2, 1, 0

; GFX8-GISEL-NEXT:    s_and_b32 s2, s2, 1

; GFX8-GISEL-NEXT:    s_cmp_lg_u32 s2, 0

; GFX8-GISEL-NEXT:    s_addc_u32 s1, s1, 0

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v0, s0

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v1, s1

; GFX8-GISEL-NEXT:    flat_store_dwordx2 v[0:1], v[0:1]

; GFX8-GISEL-NEXT:    s_endpgm

;

; GFX10-GISEL-LABEL: s_bitselect_i64_pat_0:

; GFX10-GISEL:       ; %bb.0:

; GFX10-GISEL-NEXT:    s_clause 0x1

; GFX10-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24

; GFX10-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34

; GFX10-GISEL-NEXT:    s_waitcnt lgkmcnt(0)

; GFX10-GISEL-NEXT:    s_and_b64 s[2:3], s[4:5], s[6:7]

; GFX10-GISEL-NEXT:    s_andn2_b64 s[0:1], s[0:1], s[4:5]

; GFX10-GISEL-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]

; GFX10-GISEL-NEXT:    s_add_u32 s0, s0, 10

; GFX10-GISEL-NEXT:    s_cselect_b32 s2, 1, 0

; GFX10-GISEL-NEXT:    s_and_b32 s2, s2, 1

; GFX10-GISEL-NEXT:    s_cmp_lg_u32 s2, 0

; GFX10-GISEL-NEXT:    s_addc_u32 s1, s1, 0

; GFX10-GISEL-NEXT:    v_mov_b32_e32 v0, s0

; GFX10-GISEL-NEXT:    v_mov_b32_e32 v1, s1

; GFX10-GISEL-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off

; GFX10-GISEL-NEXT:    s_endpgm

  %and0 = and i64 %a, %b
  %and0 = and i64 %a, %b

  %not.a = xor i64 %a, -1
  %not.a = xor i64 %a, -1

  %and1 = and i64 %not.a, %mask
  %and1 = and i64 %not.a, %mask

  %bitselect = or i64 %and0, %and1
  %bitselect = or i64 %and0, %and1

  %scalar.use = add i64 %bitselect, 10
  %scalar.use = add i64 %bitselect, 10

  store i64 %scalar.use, i64 addrspace(1)* undef
  store i64 %scalar.use, i64 addrspace(1)* undef

  ret void
  ret void

}
}

▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; GFX10-NEXT:    s_and_b64 s[2:3], s[2:3], s[6:7]
; GFX10-NEXT:    s_and_b64 s[2:3], s[2:3], s[6:7]

; GFX10-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]
; GFX10-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]

; GFX10-NEXT:    s_add_u32 s0, s0, 10
; GFX10-NEXT:    s_add_u32 s0, s0, 10

; GFX10-NEXT:    s_addc_u32 s1, s1, 0
; GFX10-NEXT:    s_addc_u32 s1, s1, 0

; GFX10-NEXT:    v_mov_b32_e32 v0, s0
; GFX10-NEXT:    v_mov_b32_e32 v0, s0

; GFX10-NEXT:    v_mov_b32_e32 v1, s1
; GFX10-NEXT:    v_mov_b32_e32 v1, s1

; GFX10-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off

; GFX10-NEXT:    s_endpgm
; GFX10-NEXT:    s_endpgm

;

; GFX8-GISEL-LABEL: s_bitselect_i64_pat_1:

; GFX8-GISEL:       ; %bb.0:

; GFX8-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24

; GFX8-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34

; GFX8-GISEL-NEXT:    s_waitcnt lgkmcnt(0)

; GFX8-GISEL-NEXT:    s_xor_b64 s[2:3], s[4:5], s[0:1]

; GFX8-GISEL-NEXT:    s_and_b64 s[2:3], s[2:3], s[6:7]

; GFX8-GISEL-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]

; GFX8-GISEL-NEXT:    s_add_u32 s0, s0, 10

; GFX8-GISEL-NEXT:    s_cselect_b32 s2, 1, 0

; GFX8-GISEL-NEXT:    s_and_b32 s2, s2, 1

; GFX8-GISEL-NEXT:    s_cmp_lg_u32 s2, 0

; GFX8-GISEL-NEXT:    s_addc_u32 s1, s1, 0

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v0, s0

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v1, s1

; GFX8-GISEL-NEXT:    flat_store_dwordx2 v[0:1], v[0:1]

; GFX8-GISEL-NEXT:    s_endpgm

;

; GFX10-GISEL-LABEL: s_bitselect_i64_pat_1:

; GFX10-GISEL:       ; %bb.0:

; GFX10-GISEL-NEXT:    s_clause 0x1

; GFX10-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24

; GFX10-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34

; GFX10-GISEL-NEXT:    s_waitcnt lgkmcnt(0)

; GFX10-GISEL-NEXT:    s_xor_b64 s[2:3], s[4:5], s[0:1]

; GFX10-GISEL-NEXT:    s_and_b64 s[2:3], s[2:3], s[6:7]

; GFX10-GISEL-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]

; GFX10-GISEL-NEXT:    s_add_u32 s0, s0, 10

; GFX10-GISEL-NEXT:    s_cselect_b32 s2, 1, 0

; GFX10-GISEL-NEXT:    s_and_b32 s2, s2, 1

; GFX10-GISEL-NEXT:    s_cmp_lg_u32 s2, 0

; GFX10-GISEL-NEXT:    s_addc_u32 s1, s1, 0

; GFX10-GISEL-NEXT:    v_mov_b32_e32 v0, s0

; GFX10-GISEL-NEXT:    v_mov_b32_e32 v1, s1

; GFX10-GISEL-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off

; GFX10-GISEL-NEXT:    s_endpgm

  %xor.0 = xor i64 %a, %mask
  %xor.0 = xor i64 %a, %mask

  %and = and i64 %xor.0, %b
  %and = and i64 %xor.0, %b

  %bitselect = xor i64 %and, %mask
  %bitselect = xor i64 %and, %mask




  %scalar.use = add i64 %bitselect, 10
  %scalar.use = add i64 %bitselect, 10

  store i64 %scalar.use, i64 addrspace(1)* undef
  store i64 %scalar.use, i64 addrspace(1)* undef

  ret void
  ret void

}
}

▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Lines
; GFX10-NEXT:    s_and_b64 s[2:3], s[2:3], s[6:7]
; GFX10-NEXT:    s_and_b64 s[2:3], s[2:3], s[6:7]

; GFX10-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]
; GFX10-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]

; GFX10-NEXT:    s_add_u32 s0, s0, 10
; GFX10-NEXT:    s_add_u32 s0, s0, 10

; GFX10-NEXT:    s_addc_u32 s1, s1, 0
; GFX10-NEXT:    s_addc_u32 s1, s1, 0

; GFX10-NEXT:    v_mov_b32_e32 v0, s0
; GFX10-NEXT:    v_mov_b32_e32 v0, s0

; GFX10-NEXT:    v_mov_b32_e32 v1, s1
; GFX10-NEXT:    v_mov_b32_e32 v1, s1

; GFX10-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off

; GFX10-NEXT:    s_endpgm
; GFX10-NEXT:    s_endpgm

;

; GFX8-GISEL-LABEL: s_bitselect_i64_pat_2:

; GFX8-GISEL:       ; %bb.0:

; GFX8-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24

; GFX8-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34

; GFX8-GISEL-NEXT:    s_waitcnt lgkmcnt(0)

; GFX8-GISEL-NEXT:    s_xor_b64 s[2:3], s[4:5], s[0:1]

; GFX8-GISEL-NEXT:    s_and_b64 s[2:3], s[2:3], s[6:7]

; GFX8-GISEL-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]

; GFX8-GISEL-NEXT:    s_add_u32 s0, s0, 10

; GFX8-GISEL-NEXT:    s_cselect_b32 s2, 1, 0

; GFX8-GISEL-NEXT:    s_and_b32 s2, s2, 1

; GFX8-GISEL-NEXT:    s_cmp_lg_u32 s2, 0

; GFX8-GISEL-NEXT:    s_addc_u32 s1, s1, 0

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v0, s0

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v1, s1

; GFX8-GISEL-NEXT:    flat_store_dwordx2 v[0:1], v[0:1]

; GFX8-GISEL-NEXT:    s_endpgm

;

; GFX10-GISEL-LABEL: s_bitselect_i64_pat_2:

; GFX10-GISEL:       ; %bb.0:

; GFX10-GISEL-NEXT:    s_clause 0x1

; GFX10-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24

; GFX10-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34

; GFX10-GISEL-NEXT:    s_waitcnt lgkmcnt(0)

; GFX10-GISEL-NEXT:    s_xor_b64 s[2:3], s[4:5], s[0:1]

; GFX10-GISEL-NEXT:    s_and_b64 s[2:3], s[2:3], s[6:7]

; GFX10-GISEL-NEXT:    s_xor_b64 s[0:1], s[2:3], s[0:1]

; GFX10-GISEL-NEXT:    s_add_u32 s0, s0, 10

; GFX10-GISEL-NEXT:    s_cselect_b32 s2, 1, 0

; GFX10-GISEL-NEXT:    s_and_b32 s2, s2, 1

; GFX10-GISEL-NEXT:    s_cmp_lg_u32 s2, 0

; GFX10-GISEL-NEXT:    s_addc_u32 s1, s1, 0

; GFX10-GISEL-NEXT:    v_mov_b32_e32 v0, s0

; GFX10-GISEL-NEXT:    v_mov_b32_e32 v1, s1

; GFX10-GISEL-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off

; GFX10-GISEL-NEXT:    s_endpgm

  %xor.0 = xor i64 %a, %mask
  %xor.0 = xor i64 %a, %mask

  %and = and i64 %xor.0, %b
  %and = and i64 %xor.0, %b

  %bitselect = xor i64 %and, %mask
  %bitselect = xor i64 %and, %mask




  %scalar.use = add i64 %bitselect, 10
  %scalar.use = add i64 %bitselect, 10

  store i64 %scalar.use, i64 addrspace(1)* undef
  store i64 %scalar.use, i64 addrspace(1)* undef

  ret void
  ret void

}
}

▲ Show 20 Lines • Show All 44 Lines • ▼ Show 20 Lines
; GFX10-NEXT:    s_and_b64 s[2:3], s[6:7], s[2:3]
; GFX10-NEXT:    s_and_b64 s[2:3], s[6:7], s[2:3]

; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]
; GFX10-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]

; GFX10-NEXT:    s_add_u32 s0, s0, 10
; GFX10-NEXT:    s_add_u32 s0, s0, 10

; GFX10-NEXT:    s_addc_u32 s1, s1, 0
; GFX10-NEXT:    s_addc_u32 s1, s1, 0

; GFX10-NEXT:    v_mov_b32_e32 v0, s0
; GFX10-NEXT:    v_mov_b32_e32 v0, s0

; GFX10-NEXT:    v_mov_b32_e32 v1, s1
; GFX10-NEXT:    v_mov_b32_e32 v1, s1

; GFX10-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off
; GFX10-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off

; GFX10-NEXT:    s_endpgm
; GFX10-NEXT:    s_endpgm

;

; GFX8-GISEL-LABEL: s_bfi_sha256_ma_i64:

; GFX8-GISEL:       ; %bb.0: ; %entry

; GFX8-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24

; GFX8-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34

; GFX8-GISEL-NEXT:    s_waitcnt lgkmcnt(0)

; GFX8-GISEL-NEXT:    s_and_b64 s[2:3], s[4:5], s[0:1]

; GFX8-GISEL-NEXT:    s_or_b64 s[0:1], s[4:5], s[0:1]

; GFX8-GISEL-NEXT:    s_and_b64 s[0:1], s[6:7], s[0:1]

; GFX8-GISEL-NEXT:    s_or_b64 s[0:1], s[2:3], s[0:1]

; GFX8-GISEL-NEXT:    s_add_u32 s0, s0, 10

; GFX8-GISEL-NEXT:    s_cselect_b32 s2, 1, 0

; GFX8-GISEL-NEXT:    s_and_b32 s2, s2, 1

; GFX8-GISEL-NEXT:    s_cmp_lg_u32 s2, 0

; GFX8-GISEL-NEXT:    s_addc_u32 s1, s1, 0

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v0, s0

; GFX8-GISEL-NEXT:    v_mov_b32_e32 v1, s1

; GFX8-GISEL-NEXT:    flat_store_dwordx2 v[0:1], v[0:1]

; GFX8-GISEL-NEXT:    s_endpgm

;

; GFX10-GISEL-LABEL: s_bfi_sha256_ma_i64:

; GFX10-GISEL:       ; %bb.0: ; %entry

; GFX10-GISEL-NEXT:    s_clause 0x1

; GFX10-GISEL-NEXT:    s_load_dwordx4 s[4:7], s[0:1], 0x24

; GFX10-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[0:1], 0x34

; GFX10-GISEL-NEXT:    s_waitcnt lgkmcnt(0)

; GFX10-GISEL-NEXT:    s_or_b64 s[2:3], s[4:5], s[0:1]

; GFX10-GISEL-NEXT:    s_and_b64 s[0:1], s[4:5], s[0:1]

; GFX10-GISEL-NEXT:    s_and_b64 s[2:3], s[6:7], s[2:3]

; GFX10-GISEL-NEXT:    s_or_b64 s[0:1], s[0:1], s[2:3]

; GFX10-GISEL-NEXT:    s_add_u32 s0, s0, 10

; GFX10-GISEL-NEXT:    s_cselect_b32 s2, 1, 0

; GFX10-GISEL-NEXT:    s_and_b32 s2, s2, 1

; GFX10-GISEL-NEXT:    s_cmp_lg_u32 s2, 0

; GFX10-GISEL-NEXT:    s_addc_u32 s1, s1, 0

; GFX10-GISEL-NEXT:    v_mov_b32_e32 v0, s0

; GFX10-GISEL-NEXT:    v_mov_b32_e32 v1, s1

; GFX10-GISEL-NEXT:    global_store_dwordx2 v[0:1], v[0:1], off

; GFX10-GISEL-NEXT:    s_endpgm

entry:
entry:

  %and0 = and i64 %x, %z
  %and0 = and i64 %x, %z

  %or0 = or i64 %x, %z
  %or0 = or i64 %x, %z

  %and1 = and i64 %y, %or0
  %and1 = and i64 %y, %or0

  %or1 = or i64 %and0, %and1
  %or1 = or i64 %and0, %and1




  %scalar.use = add i64 %or1, 10
  %scalar.use = add i64 %or1, 10

  store i64 %scalar.use, i64 addrspace(1)* undef
  store i64 %scalar.use, i64 addrspace(1)* undef

  ret void
  ret void

}
}