Move the Target way of overriding DAG Scheduler to a target hook

[mehdi_amini]

Summary

The previous way of overriding it was relying on calling "setDefault"
on the global registry, which implies global mutable state.

[atrick]

Thanks for fixing this. I don't know why it was written the way it was. Do you need to add a subtarget hook here though? The idea of this code is for the command line to override the target prefs. There's already a get/seSchedulingPreference hook in TargetLowering that comes into play when the default command line option is used.

[mehdi_amini]

It seems that the DAGLinearizer can't be selected by the get/setSchedulingPreference (see ScheduleDAGSDNodes* createDefaultScheduler).

Like if there are two levels:

1. getDefault was used to select the method to create the scheduler
2. if the default was not changed (createDefaultScheduler), then a combination of OptLevel, enableMachineScheduler(), and getSchedulingPreference() are used to select one among SourceListDAGScheduler, BURRListDAGScheduler, HybridListDAGScheduler, VLIWDAGScheduler, and ILPListDAGScheduler.

[mehdi_amini]

Update after a discussion with Andy, plays better with command line argument.

(I didn't get originally the purpose of the registry)

[atrick]

Let's see what Eric has to say about including TargetSelectionDAGInfo.h from TargetSubtargetInfo.h. I'm not sure that's the right layering.

Otherwise LGTM. Thanks.

When you push this, please send a note to llvm-dev telling people that their out of tree targets should not use the SchedulerRegistry to select a selection DAG scheduler. They should use your hook. It's not a big deal because we don't want people using SelectionDAG scheduler heuristics anyway, but it is a courtesy.

[mehdi_amini]

The out-of-tree targets that are using setDefault() right now will necessarily notice when they won't build anymore since setDefault() is deleted ;)
(but OK I'll send an email)

[mehdi_amini]

Remove useless includes (remaining from the first version of the patch)

[atrick]

LGTM. Thanks again.

[mehdi_amini]

landed r243388

[echristo]

Looks fine to me (realize you've already committed, but you mentioned my name).

-eric

include/llvm/CodeGen/SchedulerRegistry.h

public:
   // Accessors.
   //
   RegisterScheduler *getNext() const {
     return (RegisterScheduler *)MachinePassRegistryNode::getNext();
   }
   static RegisterScheduler *getList() {
     return (RegisterScheduler *)Registry.getList();
   }
-  static FunctionPassCtor getDefault() {
-    return (FunctionPassCtor)Registry.getDefault();
-  }
-  static void setDefault(FunctionPassCtor C) {
-    Registry.setDefault((MachinePassCtor)C);
-  }
   static void setListener(MachinePassRegistryListener *L) {
     Registry.setListener(L);
   }
 };
 
 /// createBURRListDAGScheduler - This creates a bottom up register usage
 /// reduction list scheduler.
 ScheduleDAGSDNodes *createBURRListDAGScheduler(SelectionDAGISel *IS,

include/llvm/Target/TargetSubtargetInfo.h

 // This file describes the subtarget options of a Target machine.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_TARGET_TARGETSUBTARGETINFO_H
 #define LLVM_TARGET_TARGETSUBTARGETINFO_H
 
 #include "llvm/CodeGen/PBQPRAConstraint.h"
+#include "llvm/CodeGen/SchedulerRegistry.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/CodeGen.h"
 
 namespace llvm {
 
 class DataLayout;
 class MachineFunction;
 class MachineInstr;
public:
   virtual const TargetInstrInfo *getInstrInfo() const { return nullptr; }
   virtual const TargetFrameLowering *getFrameLowering() const {
     return nullptr;
   }
   virtual const TargetLowering *getTargetLowering() const { return nullptr; }
   virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const {
     return nullptr;
   }
+  /// Target can subclass this hook to select a different DAG scheduler.
+  virtual RegisterScheduler::FunctionPassCtor
+      getDAGScheduler(CodeGenOpt::Level) const {
+    return nullptr;
+  }
 
   /// getRegisterInfo - If register information is available, return it.  If
   /// not, return null.  This is kept separate from RegInfo until RegInfo has
   /// details of graph coloring register allocation removed from it.
   ///
   virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
 
   /// getInstrItineraryData - Returns instruction itinerary data for the target

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

namespace llvm {
   //===--------------------------------------------------------------------===//
   /// createDefaultScheduler - This creates an instruction scheduler appropriate
   /// for the target.
   ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS,
                                              CodeGenOpt::Level OptLevel) {
     const TargetLowering *TLI = IS->TLI;
     const TargetSubtargetInfo &ST = IS->MF->getSubtarget();
 
+    // Try first to see if the Target has its own way of selecting a scheduler
+    if (auto *SchedulerCtor = ST.getDAGScheduler(OptLevel)) {
+      return SchedulerCtor(IS, OptLevel);
+    }
+
     if (OptLevel == CodeGenOpt::None ||
         (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) ||
         TLI->getSchedulingPreference() == Sched::Source)
       return createSourceListDAGScheduler(IS, OptLevel);
     if (TLI->getSchedulingPreference() == Sched::RegPressure)
       return createBURRListDAGScheduler(IS, OptLevel);
     if (TLI->getSchedulingPreference() == Sched::Hybrid)
       return createHybridListDAGScheduler(IS, OptLevel);

 }
 
 
 /// Create the scheduler. If a specific scheduler was specified
 /// via the SchedulerRegistry, use it, otherwise select the
 /// one preferred by the target.
 ///
 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() {
-  RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
-
-  if (!Ctor) {
-    Ctor = ISHeuristic;
-    RegisterScheduler::setDefault(Ctor);
-  }
-
-  return Ctor(this, OptLevel);
+  return ISHeuristic(this, OptLevel);
 }
 
 //===----------------------------------------------------------------------===//
 // Helper functions used by the generated instruction selector.
 //===----------------------------------------------------------------------===//
 // Calls to these methods are generated by tblgen.
 
 /// CheckAndMask - The isel is trying to match something like (and X, 255).  If