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[AArch64] Match float round and convert to int instructions.
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Authored by gberry on Jul 22 2015, 12:34 PM.

Details

Summary

Add patterns for doing floating point round with various rounding modes
followed by conversion to int as a single FCVT* instruction.

Diff Detail

Event Timeline

gberry updated this revision to Diff 30382.Jul 22 2015, 12:34 PM
gberry retitled this revision from to [AArch64] Match float round and convert to int instructions..
gberry updated this object.
gberry added reviewers: t.p.northover, jmolloy.
gberry added subscribers: llvm-commits, mcrosier.
mcrosier added inline comments.Jul 22 2015, 1:19 PM
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
2119

Perhaps, put an assertion at the top of the function:

assert((N->getOpcode() == ISD::FP_TO_SINT || N->getOpcode() == ISD::FP_TO_UINT) && "Unexpected opcode!");

Then this logic could be simplified to something like:
unsigned FpConVariant = N->getOpcode() == ISD::FP_TO_SINT ? 0 : 1;

2124

I don't think this will ever assert; the const string will always evaluate to true.

2131

Missing FTRUNC.

3330

Maybe a static helper function or fold the logic into the callee?

jmolloy edited edge metadata.Jul 22 2015, 1:43 PM

Hi Geoff,

Generally, what is stopping this transform being implemented in TableGen? Is it just the generation of the inexact flag?

James

James,

Yes, the FRINTX generation just seemed like a bit too much to do in TableGen (if it is even possible, I didn't try it).

-Geoff

gberry updated this revision to Diff 30397.Jul 22 2015, 2:09 PM
gberry marked 4 inline comments as done.
gberry edited edge metadata.

Updated to address Chad's comments.

LGTM, but I'll defer to James/Tim or another owner for the final approval.

jmolloy accepted this revision.Jul 27 2015, 12:36 AM
jmolloy edited edge metadata.

Hi Geoff,

Sorry for the delay getting to this. This LGTM.

Cheers,

James

This revision is now accepted and ready to land.Jul 27 2015, 12:36 AM
This revision was automatically updated to reflect the committed changes.