[AArch64] Match float round and convert to int instructions.

[gberry]

Summary

Add patterns for doing floating point round with various rounding modes
followed by conversion to int as a single FCVT* instruction.

[mcrosier]

lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

2119 ↗

(On Diff #30382)

Perhaps, put an assertion at the top of the function:

assert((N->getOpcode() == ISD::FP_TO_SINT || N->getOpcode() == ISD::FP_TO_UINT) && "Unexpected opcode!");

Then this logic could be simplified to something like:
unsigned FpConVariant = N->getOpcode() == ISD::FP_TO_SINT ? 0 : 1;

2124 ↗

(On Diff #30382)

I don't think this will ever assert; the const string will always evaluate to true.

2131 ↗

(On Diff #30382)

Missing FTRUNC.

3337 ↗

(On Diff #30382)

Maybe a static helper function or fold the logic into the callee?

[jmolloy]

Hi Geoff,

Generally, what is stopping this transform being implemented in TableGen? Is it just the generation of the inexact flag?

James

[gberry]

James,

Yes, the FRINTX generation just seemed like a bit too much to do in TableGen (if it is even possible, I didn't try it).

-Geoff

[gberry]

Updated to address Chad's comments.

[mcrosier]

LGTM, but I'll defer to James/Tim or another owner for the final approval.

[jmolloy]

Hi Geoff,

Sorry for the delay getting to this. This LGTM.

Cheers,

James

llvm/trunk/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

public:
   SDNode *SelectPostStore(SDNode *N, unsigned NumVecs, unsigned Opc);
   SDNode *SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
   SDNode *SelectPostStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
 
   SDNode *SelectBitfieldExtractOp(SDNode *N);
   SDNode *SelectBitfieldInsertOp(SDNode *N);
 
   SDNode *SelectLIBM(SDNode *N);
+  SDNode *SelectFPConvertWithRound(SDNode *N);
 
   SDNode *SelectReadRegister(SDNode *N);
   SDNode *SelectWriteRegister(SDNode *N);
 
 // Include the pieces autogenerated from the target description.
 #include "AArch64GenDAGISel.inc"
 
 private:
bool SelectExtendedSHL(SDValue N, unsigned Size, bool WantExtend,
                          SDValue &Offset, SDValue &SignExtend);
 
   template<unsigned RegWidth>
   bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos) {
     return SelectCVTFixedPosOperand(N, FixedPos, RegWidth);
   }
 
   bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos, unsigned Width);
+
+  SDNode *GenerateInexactFlagIfNeeded(const SDValue &In, unsigned InTyVariant,
+                                      SDLoc DL);
 };
 } // end anonymous namespace
 
 /// isIntImmediate - This method tests to see if the node is a constant
 /// operand. If so Imm will receive the 32-bit value.
 static bool isIntImmediate(const SDNode *N, uint64_t &Imm) {
   if (const ConstantSDNode *C = dyn_cast<const ConstantSDNode>(N)) {
     Imm = C->getZExtValue();
SDNode *AArch64DAGToDAGISel::SelectBitfieldInsertOp(SDNode *N) {
   SDLoc dl(N);
   SDValue Ops[] = { Opd0,
                     Opd1,
                     CurDAG->getTargetConstant(LSB, dl, VT),
                     CurDAG->getTargetConstant(MSB, dl, VT) };
   return CurDAG->SelectNodeTo(N, Opc, VT, Ops);
 }
 
+/// GenerateInexactFlagIfNeeded - Insert FRINTX instruction to generate inexact
+/// signal on round-to-integer operations if needed. C11 leaves it
+/// implementation-defined whether these operations trigger an inexact
+/// exception. IEEE says they don't.  Unfortunately, Darwin decided they do so
+/// we sometimes have to insert a special instruction just to set the right bit
+/// in FPSR.
+SDNode *AArch64DAGToDAGISel::GenerateInexactFlagIfNeeded(const SDValue &In,
+                                                         unsigned InTyVariant,
+                                                         SDLoc DL) {
+  if (Subtarget->isTargetDarwin() && !TM.Options.UnsafeFPMath) {
+    // Pick the right FRINTX using InTyVariant needed to set the flags.
+    // InTyVariant is 0 for 32-bit and 1 for 64-bit.
+    unsigned FRINTXOpcs[] = { AArch64::FRINTXSr, AArch64::FRINTXDr };
+    return CurDAG->getMachineNode(FRINTXOpcs[InTyVariant], DL,
+                                  In.getValueType(), MVT::Glue, In);
+  }
+  return nullptr;
+}
+
 SDNode *AArch64DAGToDAGISel::SelectLIBM(SDNode *N) {
   EVT VT = N->getValueType(0);
   unsigned Variant;
   unsigned Opc;
-  unsigned FRINTXOpcs[] = { AArch64::FRINTXSr, AArch64::FRINTXDr };
 
   if (VT == MVT::f32) {
     Variant = 0;
   } else if (VT == MVT::f64) {
     Variant = 1;
   } else
     return nullptr; // Unrecognized argument type. Fall back on default codegen.
 
-  // Pick the FRINTX variant needed to set the flags.
-  unsigned FRINTXOpc = FRINTXOpcs[Variant];
-
   switch (N->getOpcode()) {
   default:
     return nullptr; // Unrecognized libm ISD node. Fall back on default codegen.
   case ISD::FCEIL: {
     unsigned FRINTPOpcs[] = { AArch64::FRINTPSr, AArch64::FRINTPDr };
     Opc = FRINTPOpcs[Variant];
     break;
   }
SDNode *AArch64DAGToDAGISel::SelectLIBM(SDNode *N) {
   }
   }
 
   SDLoc dl(N);
   SDValue In = N->getOperand(0);
   SmallVector<SDValue, 2> Ops;
   Ops.push_back(In);
 
-  // C11 leaves it implementation-defined whether these operations trigger an
-  // inexact exception. IEEE says they don't.  Unfortunately, Darwin decided
-  // they do so we sometimes have to insert a special instruction just to set
-  // the right bit in FPSR.
-  if (Subtarget->isTargetDarwin() && !TM.Options.UnsafeFPMath) {
-    SDNode *FRINTX = CurDAG->getMachineNode(FRINTXOpc, dl, VT, MVT::Glue, In);
-    Ops.push_back(SDValue(FRINTX, 1));
-  }
+  if (SDNode *FRINTXNode = GenerateInexactFlagIfNeeded(In, Variant, dl))
+    Ops.push_back(SDValue(FRINTXNode, 1));
 
   return CurDAG->getMachineNode(Opc, dl, VT, Ops);
 }
 
+/// SelectFPConvertWithRound - Try to combine FP rounding and
+/// FP-INT conversion.
+SDNode *AArch64DAGToDAGISel::SelectFPConvertWithRound(SDNode *N) {
+  SDNode *Op0 = N->getOperand(0).getNode();
+
+  // Return if the round op is used by other nodes, as this would result in two
+  // FRINTX, one each for round and convert.
+  if (!Op0->hasOneUse())
+    return nullptr;
+
+  unsigned InTyVariant;
+  EVT InTy = Op0->getValueType(0);
+  if (InTy == MVT::f32)
+    InTyVariant = 0;
+  else if (InTy == MVT::f64)
+    InTyVariant = 1;
+  else
+    return nullptr;
+
+  unsigned OutTyVariant;
+  EVT OutTy = N->getValueType(0);
+  if (OutTy == MVT::i32)
+    OutTyVariant = 0;
+  else if (OutTy == MVT::i64)
+    OutTyVariant = 1;
+  else
+    return nullptr;
+
+  assert((N->getOpcode() == ISD::FP_TO_SINT
+          || N->getOpcode() == ISD::FP_TO_UINT) && "Unexpected opcode!");
+  unsigned FpConVariant = N->getOpcode() == ISD::FP_TO_SINT ? 0 : 1;
+
+  unsigned Opc;
+  switch (Op0->getOpcode()) {
+  default:
+    return nullptr;
+  case ISD::FCEIL: {
+    unsigned FCVTPOpcs[2][2][2] = {
+        { { AArch64::FCVTPSUWSr, AArch64::FCVTPSUXSr },
+          { AArch64::FCVTPSUWDr, AArch64::FCVTPSUXDr } },
+        { { AArch64::FCVTPUUWSr, AArch64::FCVTPUUXSr },
+          { AArch64::FCVTPUUWDr, AArch64::FCVTPUUXDr } } };
+    Opc = FCVTPOpcs[FpConVariant][InTyVariant][OutTyVariant];
+    break;
+  }
+  case ISD::FFLOOR: {
+    unsigned FCVTMOpcs[2][2][2] = {
+        { { AArch64::FCVTMSUWSr, AArch64::FCVTMSUXSr },
+          { AArch64::FCVTMSUWDr, AArch64::FCVTMSUXDr } },
+        { { AArch64::FCVTMUUWSr, AArch64::FCVTMUUXSr },
+          { AArch64::FCVTMUUWDr, AArch64::FCVTMUUXDr } } };
+    Opc = FCVTMOpcs[FpConVariant][InTyVariant][OutTyVariant];
+    break;
+  }
+  case ISD::FTRUNC: {
+    unsigned FCVTZOpcs[2][2][2] = {
+        { { AArch64::FCVTZSUWSr, AArch64::FCVTZSUXSr },
+          { AArch64::FCVTZSUWDr, AArch64::FCVTZSUXDr } },
+        { { AArch64::FCVTZUUWSr, AArch64::FCVTZUUXSr },
+          { AArch64::FCVTZUUWDr, AArch64::FCVTZUUXDr } } };
+    Opc = FCVTZOpcs[FpConVariant][InTyVariant][OutTyVariant];
+    break;
+  }
+  case ISD::FROUND: {
+    unsigned FCVTAOpcs[2][2][2] = {
+        { { AArch64::FCVTASUWSr, AArch64::FCVTASUXSr },
+          { AArch64::FCVTASUWDr, AArch64::FCVTASUXDr } },
+        { { AArch64::FCVTAUUWSr, AArch64::FCVTAUUXSr },
+          { AArch64::FCVTAUUWDr, AArch64::FCVTAUUXDr } } };
+    Opc = FCVTAOpcs[FpConVariant][InTyVariant][OutTyVariant];
+    break;
+  }
+  }
+
+  SDLoc DL(N);
+  SDValue In = Op0->getOperand(0);
+  SmallVector<SDValue, 2> Ops;
+  Ops.push_back(In);
+
+  if (SDNode *FRINTXNode = GenerateInexactFlagIfNeeded(In, InTyVariant, DL))
+    Ops.push_back(SDValue(FRINTXNode, 1));
+
+  return CurDAG->getMachineNode(Opc, DL, OutTy, Ops);
+}
+
 bool
 AArch64DAGToDAGISel::SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos,
                                               unsigned RegWidth) {
   APFloat FVal(0.0);
   if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N))
     FVal = CN->getValueAPF();
   else if (LoadSDNode *LN = dyn_cast<LoadSDNode>(N)) {
     // Some otherwise illegal constants are allowed in this case.
SDNode *AArch64DAGToDAGISel::Select(SDNode *Node) {
 
   case ISD::FCEIL:
   case ISD::FFLOOR:
   case ISD::FTRUNC:
   case ISD::FROUND:
     if (SDNode *I = SelectLIBM(Node))
       return I;
     break;
+
+  case ISD::FP_TO_SINT:
+  case ISD::FP_TO_UINT:
+    if (SDNode *I = SelectFPConvertWithRound(Node))
+      return I;
+    break;
   }
 
   // Select the default instruction
   ResNode = SelectCode(Node);
 
   DEBUG(errs() << "=> ");
   if (ResNode == nullptr || ResNode == Node)
     DEBUG(Node->dump(CurDAG));

llvm/trunk/test/CodeGen/AArch64/round-conv.ll

+; RUN: llc < %s -mtriple=arm64-apple-ios7.0 | FileCheck %s --check-prefix=CHECK-INEXACT
+; RUN: llc < %s -mtriple=arm64-apple-ios7.0 -enable-unsafe-fp-math | FileCheck %s --check-prefix=CHECK-FAST
+; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s --check-prefix=CHECK-FAST
+
+; CHECK-INEXACT-LABEL: testmsws:
+; CHECK-INEXACT: fcvtms w0, s0
+; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
+
+; CHECK-FAST-LABEL: testmsws:
+; CHECK-FAST: fcvtms w0, s0
+; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+define i32 @testmsws(float %a) {
+entry:
+  %call = call float @floorf(float %a) nounwind readnone
+  %conv = fptosi float %call to i32
+  ret i32 %conv
+}
+
+; CHECK-INEXACT-LABEL: testmsxs:
+; CHECK-INEXACT: fcvtms x0, s0
+; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
+
+; CHECK-FAST-LABEL: testmsxs:
+; CHECK-FAST: fcvtms x0, s0
+; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+define i64 @testmsxs(float %a) {
+entry:
+  %call = call float @floorf(float %a) nounwind readnone
+  %conv = fptosi float %call to i64
+  ret i64 %conv
+}
+
+; CHECK-INEXACT-LABEL: testmswd:
+; CHECK-INEXACT: fcvtms w0, d0
+; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
+
+; CHECK-FAST-LABEL: testmswd:
+; CHECK-FAST: fcvtms w0, d0
+; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+define i32 @testmswd(double %a) {
+entry:
+  %call = call double @floor(double %a) nounwind readnone
+  %conv = fptosi double %call to i32
+  ret i32 %conv
+}
+
+; CHECK-INEXACT-LABEL: testmsxd:
+; CHECK-INEXACT: fcvtms x0, d0
+; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
+
+; CHECK-FAST-LABEL: testmsxd:
+; CHECK-FAST: fcvtms x0, d0
+; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+define i64 @testmsxd(double %a) {
+entry:
+  %call = call double @floor(double %a) nounwind readnone
+  %conv = fptosi double %call to i64
+  ret i64 %conv
+}
+
+; CHECK-INEXACT-LABEL: testmuws:
+; CHECK-INEXACT: fcvtmu w0, s0
+; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
+
+; CHECK-FAST-LABEL: testmuws:
+; CHECK-FAST: fcvtmu w0, s0
+; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+define i32 @testmuws(float %a) {
+entry:
+  %call = call float @floorf(float %a) nounwind readnone
+  %conv = fptoui float %call to i32
+  ret i32 %conv
+}
+
+; CHECK-INEXACT-LABEL: testmuxs:
+; CHECK-INEXACT: fcvtmu x0, s0
+; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
+
+; CHECK-FAST-LABEL: testmuxs:
+; CHECK-FAST: fcvtmu x0, s0
+; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+define i64 @testmuxs(float %a) {
+entry:
+  %call = call float @floorf(float %a) nounwind readnone
+  %conv = fptoui float %call to i64
+  ret i64 %conv
+}
+
+; CHECK-INEXACT-LABEL: testmuwd:
+; CHECK-INEXACT: fcvtmu w0, d0
+; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
+
+; CHECK-FAST-LABEL: testmuwd:
+; CHECK-FAST: fcvtmu w0, d0
+; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+define i32 @testmuwd(double %a) {
+entry:
+  %call = call double @floor(double %a) nounwind readnone
+  %conv = fptoui double %call to i32
+  ret i32 %conv
+}
+
+; CHECK-INEXACT-LABEL: testmuxd:
+; CHECK-INEXACT: fcvtmu x0, d0
+; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
+
+; CHECK-FAST-LABEL: testmuxd:
+; CHECK-FAST: fcvtmu x0, d0
+; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+define i64 @testmuxd(double %a) {
+entry:
+  %call = call double @floor(double %a) nounwind readnone
+  %conv = fptoui double %call to i64
+  ret i64 %conv
+}
+
+; CHECK-INEXACT-LABEL: testpsws:
+; CHECK-INEXACT: fcvtps w0, s0
+; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
+
+; CHECK-FAST-LABEL: testpsws:
+; CHECK-FAST: fcvtps w0, s0
+; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+define i32 @testpsws(float %a) {
+entry:
+  %call = call float @ceilf(float %a) nounwind readnone
+  %conv = fptosi float %call to i32
+  ret i32 %conv
+}
+
+; CHECK-INEXACT-LABEL: testpsxs:
+; CHECK-INEXACT: fcvtps x0, s0
+; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
+
+; CHECK-FAST-LABEL: testpsxs:
+; CHECK-FAST: fcvtps x0, s0
+; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+define i64 @testpsxs(float %a) {
+entry:
+  %call = call float @ceilf(float %a) nounwind readnone
+  %conv = fptosi float %call to i64
+  ret i64 %conv
+}
+
+; CHECK-INEXACT-LABEL: testpswd:
+; CHECK-INEXACT: fcvtps w0, d0
+; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
+
+; CHECK-FAST-LABEL: testpswd:
+; CHECK-FAST: fcvtps w0, d0
+; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+define i32 @testpswd(double %a) {
+entry:
+  %call = call double @ceil(double %a) nounwind readnone
+  %conv = fptosi double %call to i32
+  ret i32 %conv
+}
+
+; CHECK-INEXACT-LABEL: testpsxd:
+; CHECK-INEXACT: fcvtps x0, d0
+; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
+
+; CHECK-FAST-LABEL: testpsxd:
+; CHECK-FAST: fcvtps x0, d0
+; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+define i64 @testpsxd(double %a) {
+entry:
+  %call = call double @ceil(double %a) nounwind readnone
+  %conv = fptosi double %call to i64
+  ret i64 %conv
+}
+
+; CHECK-INEXACT-LABEL: testpuws:
+; CHECK-INEXACT: fcvtpu w0, s0
+; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
+
+; CHECK-FAST-LABEL: testpuws:
+; CHECK-FAST: fcvtpu w0, s0
+; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+define i32 @testpuws(float %a) {
+entry:
+  %call = call float @ceilf(float %a) nounwind readnone
+  %conv = fptoui float %call to i32
+  ret i32 %conv
+}
+
+; CHECK-INEXACT-LABEL: testpuxs:
+; CHECK-INEXACT: fcvtpu x0, s0
+; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
+
+; CHECK-FAST-LABEL: testpuxs:
+; CHECK-FAST: fcvtpu x0, s0
+; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+define i64 @testpuxs(float %a) {
+entry:
+  %call = call float @ceilf(float %a) nounwind readnone
+  %conv = fptoui float %call to i64
+  ret i64 %conv
+}
+
+; CHECK-INEXACT-LABEL: testpuwd:
+; CHECK-INEXACT: fcvtpu w0, d0
+; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
+
+; CHECK-FAST-LABEL: testpuwd:
+; CHECK-FAST: fcvtpu w0, d0
+; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+define i32 @testpuwd(double %a) {
+entry:
+  %call = call double @ceil(double %a) nounwind readnone
+  %conv = fptoui double %call to i32
+  ret i32 %conv
+}
+
+; CHECK-INEXACT-LABEL: testpuxd:
+; CHECK-INEXACT: fcvtpu x0, d0
+; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
+
+; CHECK-FAST-LABEL: testpuxd:
+; CHECK-FAST: fcvtpu x0, d0
+; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+define i64 @testpuxd(double %a) {
+entry:
+  %call = call double @ceil(double %a) nounwind readnone
+  %conv = fptoui double %call to i64
+  ret i64 %conv
+}
+
+; CHECK-INEXACT-LABEL: testzsws:
+; CHECK-INEXACT: fcvtzs w0, s0
+; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
+
+; CHECK-FAST-LABEL: testzsws:
+; CHECK-FAST: fcvtzs w0, s0
+; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+define i32 @testzsws(float %a) {
+entry:
+  %call = call float @truncf(float %a) nounwind readnone
+  %conv = fptosi float %call to i32
+  ret i32 %conv
+}
+
+; CHECK-INEXACT-LABEL: testzsxs:
+; CHECK-INEXACT: fcvtzs x0, s0
+; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
+
+; CHECK-FAST-LABEL: testzsxs:
+; CHECK-FAST: fcvtzs x0, s0
+; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+define i64 @testzsxs(float %a) {
+entry:
+  %call = call float @truncf(float %a) nounwind readnone
+  %conv = fptosi float %call to i64
+  ret i64 %conv
+}
+
+; CHECK-INEXACT-LABEL: testzswd:
+; CHECK-INEXACT: fcvtzs w0, d0
+; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
+
+; CHECK-FAST-LABEL: testzswd:
+; CHECK-FAST: fcvtzs w0, d0
+; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+define i32 @testzswd(double %a) {
+entry:
+  %call = call double @trunc(double %a) nounwind readnone
+  %conv = fptosi double %call to i32
+  ret i32 %conv
+}
+
+; CHECK-INEXACT-LABEL: testzsxd:
+; CHECK-INEXACT: fcvtzs x0, d0
+; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
+
+; CHECK-FAST-LABEL: testzsxd:
+; CHECK-FAST: fcvtzs x0, d0
+; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+define i64 @testzsxd(double %a) {
+entry:
+  %call = call double @trunc(double %a) nounwind readnone
+  %conv = fptosi double %call to i64
+  ret i64 %conv
+}
+
+; CHECK-INEXACT-LABEL: testzuws:
+; CHECK-INEXACT: fcvtzu w0, s0
+; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
+
+; CHECK-FAST-LABEL: testzuws:
+; CHECK-FAST: fcvtzu w0, s0
+; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+define i32 @testzuws(float %a) {
+entry:
+  %call = call float @truncf(float %a) nounwind readnone
+  %conv = fptoui float %call to i32
+  ret i32 %conv
+}
+
+; CHECK-INEXACT-LABEL: testzuxs:
+; CHECK-INEXACT: fcvtzu x0, s0
+; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
+
+; CHECK-FAST-LABEL: testzuxs:
+; CHECK-FAST: fcvtzu x0, s0
+; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+define i64 @testzuxs(float %a) {
+entry:
+  %call = call float @truncf(float %a) nounwind readnone
+  %conv = fptoui float %call to i64
+  ret i64 %conv
+}
+
+; CHECK-INEXACT-LABEL: testzuwd:
+; CHECK-INEXACT: fcvtzu w0, d0
+; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
+
+; CHECK-FAST-LABEL: testzuwd:
+; CHECK-FAST: fcvtzu w0, d0
+; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+define i32 @testzuwd(double %a) {
+entry:
+  %call = call double @trunc(double %a) nounwind readnone
+  %conv = fptoui double %call to i32
+  ret i32 %conv
+}
+
+; CHECK-INEXACT-LABEL: testzuxd:
+; CHECK-INEXACT: fcvtzu x0, d0
+; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
+
+; CHECK-FAST-LABEL: testzuxd:
+; CHECK-FAST: fcvtzu x0, d0
+; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+define i64 @testzuxd(double %a) {
+entry:
+  %call = call double @trunc(double %a) nounwind readnone
+  %conv = fptoui double %call to i64
+  ret i64 %conv
+}
+
+; CHECK-INEXACT-LABEL: testasws:
+; CHECK-INEXACT: fcvtas w0, s0
+; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
+
+; CHECK-FAST-LABEL: testasws:
+; CHECK-FAST: fcvtas w0, s0
+; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+define i32 @testasws(float %a) {
+entry:
+  %call = call float @roundf(float %a) nounwind readnone
+  %conv = fptosi float %call to i32
+  ret i32 %conv
+}
+
+; CHECK-INEXACT-LABEL: testasxs:
+; CHECK-INEXACT: fcvtas x0, s0
+; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
+
+; CHECK-FAST-LABEL: testasxs:
+; CHECK-FAST: fcvtas x0, s0
+; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+define i64 @testasxs(float %a) {
+entry:
+  %call = call float @roundf(float %a) nounwind readnone
+  %conv = fptosi float %call to i64
+  ret i64 %conv
+}
+
+; CHECK-INEXACT-LABEL: testaswd:
+; CHECK-INEXACT: fcvtas w0, d0
+; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
+
+; CHECK-FAST-LABEL: testaswd:
+; CHECK-FAST: fcvtas w0, d0
+; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+define i32 @testaswd(double %a) {
+entry:
+  %call = call double @round(double %a) nounwind readnone
+  %conv = fptosi double %call to i32
+  ret i32 %conv
+}
+
+; CHECK-INEXACT-LABEL: testasxd:
+; CHECK-INEXACT: fcvtas x0, d0
+; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
+
+; CHECK-FAST-LABEL: testasxd:
+; CHECK-FAST: fcvtas x0, d0
+; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+define i64 @testasxd(double %a) {
+entry:
+  %call = call double @round(double %a) nounwind readnone
+  %conv = fptosi double %call to i64
+  ret i64 %conv
+}
+
+; CHECK-INEXACT-LABEL: testauws:
+; CHECK-INEXACT: fcvtau w0, s0
+; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
+
+; CHECK-FAST-LABEL: testauws:
+; CHECK-FAST: fcvtau w0, s0
+; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+define i32 @testauws(float %a) {
+entry:
+  %call = call float @roundf(float %a) nounwind readnone
+  %conv = fptoui float %call to i32
+  ret i32 %conv
+}
+
+; CHECK-INEXACT-LABEL: testauxs:
+; CHECK-INEXACT: fcvtau x0, s0
+; CHECK-INEXACT: frintx {{s[0-9]+}}, s0
+
+; CHECK-FAST-LABEL: testauxs:
+; CHECK-FAST: fcvtau x0, s0
+; CHECK-FAST-NOT: frintx {{s[0-9]+}}, s0
+define i64 @testauxs(float %a) {
+entry:
+  %call = call float @roundf(float %a) nounwind readnone
+  %conv = fptoui float %call to i64
+  ret i64 %conv
+}
+
+; CHECK-INEXACT-LABEL: testauwd:
+; CHECK-INEXACT: fcvtau w0, d0
+; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
+
+; CHECK-FAST-LABEL: testauwd:
+; CHECK-FAST: fcvtau w0, d0
+; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+define i32 @testauwd(double %a) {
+entry:
+  %call = call double @round(double %a) nounwind readnone
+  %conv = fptoui double %call to i32
+  ret i32 %conv
+}
+
+; CHECK-INEXACT-LABEL: testauxd:
+; CHECK-INEXACT: fcvtau x0, d0
+; CHECK-INEXACT: frintx {{d[0-9]+}}, d0
+
+; CHECK-FAST-LABEL: testauxd:
+; CHECK-FAST: fcvtau x0, d0
+; CHECK-FAST-NOT: frintx {{d[0-9]+}}, d0
+define i64 @testauxd(double %a) {
+entry:
+  %call = call double @round(double %a) nounwind readnone
+  %conv = fptoui double %call to i64
+  ret i64 %conv
+}
+
+
+declare float @floorf(float) nounwind readnone
+declare double @floor(double) nounwind readnone
+declare float @ceilf(float) nounwind readnone
+declare double @ceil(double) nounwind readnone
+declare float @truncf(float) nounwind readnone
+declare double @trunc(double) nounwind readnone
+declare float @roundf(float) nounwind readnone
+declare double @round(double) nounwind readnone