SelectionDAG: Add AssertAnd SDNode

[• tstellarAMD]

Summary

The AssertAnd node is modeled after the Assert[SZ]ext nodes and is
used to represent values that are known to have some bits equal to
zero.

The purpose of this new SDNode is to allow targets to improve the
accuracy of the computeKnownBits computation in cases where values are
known to use less bits than their types size. For example, on targets
where pointers do not use all the available bits: e.g. pointer size is
64-bit, but only 48 bits are actually used.

[escha]

If I'm understanding right, this is distinct from (for example) the concept behind the code in AARCH64 that calls simplifyDemandedBits on addresses used by loads/stores to optimize given knowledge of 56-bit addresses? That is, this node represents "the high bits must be zero", not "the high bits are ignored by the addressing operations" (also, is there some reason this can't use AssertZext -- is it because AssertZext can't take an i48?)

[• tstellarAMD]

I can achieve the same result using AssertZext.. Using AssertAnd is useful if you want to apply a mask for alignment, but I don't need that functionality at the moment.

include/llvm/CodeGen/ISDOpcodes.h

enum NodeType {
     /// EntryToken - This is the marker used to indicate the start of a region.
     EntryToken,
 
     /// TokenFactor - This node takes multiple tokens as input and produces a
     /// single token result. This is used to represent the fact that the operand
     /// operators are independent of each other.
     TokenFactor,
 
+    /// This node records if a register contains a value that has been masked
+    /// by an and with constant.  This node takes two operands. The first is
+    /// the node that has already been masked by an and operation, and the
+    /// second is the constant mask that was used.
+    AssertAnd,
+
     /// AssertSext, AssertZext - These nodes record if a register contains a
     /// value that has already been zero or sign extended from a narrower type.
     /// These nodes take two operands.  The first is the node that has already
     /// been extended, and the second is a value type node indicating the width
     /// of the extension
     AssertSext, AssertZext,
 
     /// Various leaf nodes.

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
   APInt KnownZero2, KnownOne2;
 
   switch (Op.getOpcode()) {
   case ISD::Constant:
     // We know all of the bits for a constant!
     KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
     KnownZero = ~KnownOne;
     break;
+  case ISD::AssertAnd:
   case ISD::AND:
     // If either the LHS or the RHS are Zero, the result is zero.
     computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
     computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
 
     // Output known-1 bits are only known if set in both the LHS & RHS.
     KnownOne &= KnownOne2;
     // Output known-0 are known to be clear if zero in either the LHS | RHS.
case ISD::SHL:
     if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
       // shl destroys sign bits.
       Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
       if (C->getZExtValue() >= VTBits ||      // Bad shift.
           C->getZExtValue() >= Tmp) break;    // Shifted all sign bits out.
       return Tmp - C->getZExtValue();
     }
     break;
+  case ISD::AssertAnd:
   case ISD::AND:
   case ISD::OR:
   case ISD::XOR:    // NOT is handled here.
     // Logical binary ops preserve the number of sign bits at the worst.
     Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
     if (Tmp != 1) {
       Tmp2 = ComputeNumSignBits(Op.getOperand(1), Depth+1);
       FirstAnswer = std::min(Tmp, Tmp2);
SDValue SelectionDAG::getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1,
   }
   case ISD::FP_ROUND:
     assert(VT.isFloatingPoint() &&
            N1.getValueType().isFloatingPoint() &&
            VT.bitsLE(N1.getValueType()) &&
            isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!");
     if (N1.getValueType() == VT) return N1;  // noop conversion.
     break;
+  case ISD::AssertAnd: {
+    ConstantSDNode *C2 = cast<ConstantSDNode>(N2);
+    assert(N1.getValueType() == N2.getValueType() &&
+           N1.getValueType() == VT && "Binary operator types must match!");
+    if (C2->isAllOnesValue()) return N1; // noop mask.
+    break;
+  }
   case ISD::AssertSext:
   case ISD::AssertZext: {
     EVT EVT = cast<VTSDNode>(N2)->getVT();
     assert(VT == N1.getValueType() && "Not an inreg extend!");
     assert(VT.isInteger() && EVT.isInteger() &&
            "Cannot *_EXTEND_INREG FP types");
     assert(!EVT.isVector() &&
            "AssertSExt/AssertZExt type should be the vector element type "

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

#endif
   case ISD::ATOMIC_LOAD:                return "AtomicLoad";
   case ISD::ATOMIC_STORE:               return "AtomicStore";
   case ISD::PCMARKER:                   return "PCMarker";
   case ISD::READCYCLECOUNTER:           return "ReadCycleCounter";
   case ISD::SRCVALUE:                   return "SrcValue";
   case ISD::MDNODE_SDNODE:              return "MDNode";
   case ISD::EntryToken:                 return "EntryToken";
   case ISD::TokenFactor:                return "TokenFactor";
+  case ISD::AssertAnd:                  return "AssertAnd";
   case ISD::AssertSext:                 return "AssertSext";
   case ISD::AssertZext:                 return "AssertZext";
 
   case ISD::BasicBlock:                 return "BasicBlock";
   case ISD::VALUETYPE:                  return "ValueType";
   case ISD::Register:                   return "Register";
   case ISD::RegisterMask:               return "RegisterMask";
   case ISD::Constant:

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable,
   case ISD::TokenFactor:
   case ISD::CopyFromReg:
   case ISD::CopyToReg:
   case ISD::EH_LABEL:
   case ISD::LIFETIME_START:
   case ISD::LIFETIME_END:
     NodeToMatch->setNodeId(-1); // Mark selected.
     return nullptr;
+  case ISD::AssertAnd:
   case ISD::AssertSext:
   case ISD::AssertZext:
     CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0),
                                       NodeToMatch->getOperand(0));
     return nullptr;
   case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch);
   case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch);
   case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch);