[ARM] Define subtarget feature "dont-use-movt" to disallow emitting movt/movw pairs

[ahatanak]

Summary

This patch defines a new ARM subtarget feature that replaces the cl::opt option ArmUseMOVT to disallow emitting movt/movw pairs.

The corresponding clang patch is here: http://reviews.llvm.org/D11025

[echristo]

Let's have the feature be a positive feature that just happens to be on by default in a lot of places. +/-dont-use-movt seems weird.

-eric

[ahatanak]

Do you mean I should replace ARMSubtarget::DontUseMovt with ARMSubtarget::UseMovt which is true by default? That should work.

Or do you mean we should use FeatureUseMovt : SubtargetFeature<"use-movt"> instead of FeatureDontUseMovt<"dont-use-movt">? If I understand correctly how subtarget features work, I think that would require clang (and other front-ends) to add feature "+use-movt" whenever we want to allow emitting movt/movw pairs as opposed to adding "+dont-use-movt" only when we want to disallow doing so. Assuming you would want to allow movt/movw pairs in the common case, wouldn't it be better to use a negative feature?

llvm/trunk/lib/Target/ARM/ARM.td

 // See ARMInstrInfo.td for details.
 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
                                        "NaCl trap">;
 
 def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
                                         "Generate calls via indirect call "
                                         "instructions">;
 
+def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
+                                     "Don't use movt/movw pairs for 32-bit "
+                                     "imms">;
+
 // ARM ISAs.
 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
                                    "Support ARM v4T instructions">;
 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
                                    "Support ARM v5T instructions",
                                    [HasV4TOps]>;
 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
                              "Support ARM v5TE, v5TEj, and v5TExp instructions",

llvm/trunk/lib/Target/ARM/ARMSubtarget.h

protected:
   bool HasThumb2;
 
   /// NoARM - True if subtarget does not support ARM mode execution.
   bool NoARM;
 
   /// IsR9Reserved - True if R9 is a not available as general purpose register.
   bool IsR9Reserved;
 
-  /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
-  /// imms (including global addresses).
-  bool UseMovt;
+  /// NoMovt - True if MOVT / MOVW pairs are not used for materialization of
+  /// 32-bit imms (including global addresses).
+  bool NoMovt;
 
   /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
   /// must be able to synthesize call stubs for interworking between ARM and
   /// Thumb.
   bool SupportsTailCall;
 
   /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
   /// only so far)

llvm/trunk/lib/Target/ARM/ARMSubtarget.cpp

 #define GET_SUBTARGETINFO_CTOR
 #include "ARMGenSubtargetInfo.inc"
 
 static cl::opt<bool>
 ReserveR9("arm-reserve-r9", cl::Hidden,
           cl::desc("Reserve R9, making it unavailable as GPR"));
 
 static cl::opt<bool>
-ArmUseMOVT("arm-use-movt", cl::init(true), cl::Hidden);
-
-static cl::opt<bool>
 UseFusedMulOps("arm-use-mulops",
                cl::init(true), cl::Hidden);
 
 namespace {
 enum AlignMode {
   DefaultAlign,
   StrictAlign,
   NoStrictAlign
void ARMSubtarget::initializeEnvironment() {
   SlowFPVMLx = false;
   HasVMLxForwarding = false;
   SlowFPBrcc = false;
   InThumbMode = false;
   UseSoftFloat = false;
   HasThumb2 = false;
   NoARM = false;
   IsR9Reserved = ReserveR9;
-  UseMovt = false;
+  NoMovt = false;
   SupportsTailCall = false;
   HasFP16 = false;
   HasD16 = false;
   HasHardwareDivide = false;
   HasHardwareDivideInARM = false;
   HasT2ExtractPack = false;
   HasDataBarrier = false;
   Pref32BitThumb = false;
void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
   if (isTargetWindows())
     NoARM = true;
 
   if (isAAPCS_ABI())
     stackAlignment = 8;
   if (isTargetNaCl())
     stackAlignment = 16;
 
-  UseMovt = hasV6T2Ops() && ArmUseMOVT;
-
   if (isTargetMachO()) {
     IsR9Reserved = ReserveR9 || !HasV6Ops;
     SupportsTailCall = !isTargetIOS() || !getTargetTriple().isOSVersionLT(5, 0);
   } else {
     IsR9Reserved = ReserveR9;
     SupportsTailCall = !isThumb1Only();
   }
 

 bool ARMSubtarget::enableAtomicExpand() const {
   return hasAnyDataBarrier() && !isThumb1Only();
 }
 
 bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
   // NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
   // immediates as it is inherently position independent, and may be out of
   // range otherwise.
-  return UseMovt && (isTargetWindows() ||
-                     !MF.getFunction()->hasFnAttribute(Attribute::MinSize));
+  return !NoMovt && hasV6T2Ops() &&
+         (isTargetWindows() ||
 }
 
 bool ARMSubtarget::useFastISel() const {
   // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl.
   return TM.Options.EnableFastISel &&
          ((isTargetMachO() && !isThumb1Only()) ||
           (isTargetLinux() && !isThumb()) || (isTargetNaCl() && !isThumb()));
 }

llvm/trunk/test/CodeGen/ARM/fast-isel-mvn.ll

-; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=armv7-apple-ios     < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
-; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=armv7-linux-gnueabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
-; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=false -mtriple=thumbv7-apple-ios   < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
-; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=true  -mtriple=thumbv7-apple-ios   < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB
-; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -arm-use-movt=true  -mtriple=armv7-apple-ios     < %s | FileCheck %s --check-prefix=MOVT
+; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mattr=+no-movt -mtriple=armv7-apple-ios     < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
+; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mattr=+no-movt -mtriple=armv7-linux-gnueabi < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
+; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mattr=+no-movt -mtriple=thumbv7-apple-ios   < %s | FileCheck %s --check-prefix=CHECK --check-prefix=ARM
+; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios   < %s | FileCheck %s --check-prefix=CHECK --check-prefix=THUMB
+; RUN: llc -O0 -verify-machineinstrs -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios     < %s | FileCheck %s --check-prefix=MOVT
 ; rdar://10412592
 
 define void @t1() nounwind {
 entry:
 ; CHECK-LABEL: t1
 ; CHECK:       mvn r0, #0
   call void @foo(i32 -1)
   ret void

llvm/trunk/test/CodeGen/ARM/subtarget-no-movt.ll

+; RUN: llc -march thumb -mcpu=cortex-a8 -relocation-model=static %s -o - | FileCheck -check-prefix=NO-OPTION %s
+; RUN: llc -march thumb -mcpu=cortex-a8 -relocation-model=static %s -o - -mattr=-no-movt | FileCheck -check-prefix=USE-MOVT %s
+; RUN: llc -march thumb -mcpu=cortex-a8 -relocation-model=static %s -o - -mattr=+no-movt | FileCheck -check-prefix=NO-USE-MOVT %s
+; RUN: llc -march thumb -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 | FileCheck -check-prefix=NO-OPTION %s
+; RUN: llc -march thumb -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -mattr=-no-movt | FileCheck -check-prefix=USE-MOVT %s
+; RUN: llc -march thumb -mcpu=cortex-a8 -relocation-model=static %s -o - -O0 -mattr=+no-movt | FileCheck -check-prefix=NO-USE-MOVT %s
+
+; NO-OPTION-LABEL: {{_?}}foo0
+; NO-OPTION: ldr [[R0:r[0-9]+]], [[L0:.*]]
+; NO-OPTION: [[L0]]:
+; NO-OPTION: .long 2296237089
+
+; USE-MOVT-LABEL: {{_?}}foo0
+; USE-MOVT: movw [[R0:r[0-9]+]], #52257
+; USE-MOVT: movt [[R0]], #35037
+
+; NO-USE-MOVT-LABEL: {{_?}}foo0
+; NO-USE-MOVT: ldr [[R0:r[0-9]+]], [[L0:.*]]
+; NO-USE-MOVT: [[L0]]:
+; NO-USE-MOVT: .long 2296237089
+
+define i32 @foo0(i32 %a) #0 {
+  %1 = xor i32 -1998730207, %a
+  ret i32 %1
+}
+
+; NO-OPTION-LABEL: {{_?}}foo1
+; NO-OPTION: movw [[R0:r[0-9]+]], #52257
+; NO-OPTION: movt [[R0]], #35037
+
+; USE-MOVT-LABEL: {{_?}}foo1
+; USE-MOVT: movw [[R0:r[0-9]+]], #52257
+; USE-MOVT: movt [[R0]], #35037
+
+; NO-USE-MOVT-LABEL: {{_?}}foo1
+; NO-USE-MOVT: ldr [[R0:r[0-9]+]], [[L0:.*]]
+; NO-USE-MOVT: [[L0]]:
+; NO-USE-MOVT: .long 2296237089
+
+define i32 @foo1(i32 %a) {
+  %1 = xor i32 -1998730207, %a
+  ret i32 %1
+}
+
+attributes #0 = { "target-features"="+no-movt" }