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Differential D10507

[ARM] Don't hard code metadata arguments
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Authored by rs on Jun 17 2015, 10:24 AM.

Details

Reviewers
rnk
Commits
rGe8accef8660e: [ARM] Replace hard coded metadata arguments in tests with a regex.
rC239932: [ARM] Replace hard coded metadata arguments in tests with a regex.
rL239932: [ARM] Replace hard coded metadata arguments in tests with a regex.
Summary

The metadata argument identifiers could change if more metadata is generated which would cause these tests to fail as they currently are, I've re-factored the tests so that a regex is used to identify the metadata identifier number.

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Repository
rL LLVM

Event Timeline

rs updated this revision to Diff 27841.Jun 17 2015, 10:24 AM
rs retitled this revision from to [ARM] Don't hard code metadata arguments.
rs updated this object.
rs edited the test plan for this revision. (Show Details)
rs added a subscriber: Unknown Object (MLST).
Herald added subscribers: aemerson, rengolin. · View Herald TranscriptJun 17 2015, 10:24 AM
rnk accepted this revision.Jun 17 2015, 11:41 AM
rnk added a reviewer: rnk.
rnk added a subscriber: rnk.

lgtm

This revision is now accepted and ready to land.Jun 17 2015, 11:41 AM
rs added a comment.Jun 17 2015, 12:57 PM

Thanks for the review.

Closed by commit rL239932: [ARM] Replace hard coded metadata arguments in tests with a regex. (authored by rsingh). · Explain WhyJun 17 2015, 1:01 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
cfe/
trunk/
test/
CodeGen/
34 lines
14 lines

Diff 27860

cfe/trunk/test/CodeGen/arm_acle.c

Show First 20 Lines • Show All 333 Lines • ▼ Show 20 Lines
// AArch32: call i32 @llvm.arm.crc32cw // AArch32: call i32 @llvm.arm.crc32cw
// AArch64: call i32 @llvm.aarch64.crc32cx // AArch64: call i32 @llvm.aarch64.crc32cx
uint32_t test_crc32cd(uint32_t a, uint64_t b) { uint32_t test_crc32cd(uint32_t a, uint64_t b) {
return __crc32cd(a, b); return __crc32cd(a, b);
} }
/* 10.1 Special register intrinsics */ /* 10.1 Special register intrinsics */
// ARM-LABEL: test_rsr // ARM-LABEL: test_rsr
// AArch64: call i64 @llvm.read_register.i64(metadata !1) // AArch64: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])
// AArch32: call i32 @llvm.read_register.i32(metadata !3) // AArch32: call i32 @llvm.read_register.i32(metadata ![[M2:[0-9]]])
uint32_t test_rsr() { uint32_t test_rsr() {
#ifdef __ARM_32BIT_STATE #ifdef __ARM_32BIT_STATE
return __arm_rsr("cp1:2:c3:c4:5"); return __arm_rsr("cp1:2:c3:c4:5");
#else #else
return __arm_rsr("1:2:3:4:5"); return __arm_rsr("1:2:3:4:5");
#endif #endif
} }
// ARM-LABEL: test_rsr64 // ARM-LABEL: test_rsr64
// AArch64: call i64 @llvm.read_register.i64(metadata !1) // AArch64: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])
// AArch32: call i64 @llvm.read_register.i64(metadata !4) // AArch32: call i64 @llvm.read_register.i64(metadata ![[M3:[0-9]]])
uint64_t test_rsr64() { uint64_t test_rsr64() {
#ifdef __ARM_32BIT_STATE #ifdef __ARM_32BIT_STATE
return __arm_rsr64("cp1:2:c3"); return __arm_rsr64("cp1:2:c3");
#else #else
return __arm_rsr64("1:2:3:4:5"); return __arm_rsr64("1:2:3:4:5");
#endif #endif
} }
// ARM-LABEL: test_rsrp // ARM-LABEL: test_rsrp
// AArch64: call i64 @llvm.read_register.i64(metadata !2) // AArch64: call i64 @llvm.read_register.i64(metadata ![[M1:[0-9]]])
// AArch32: call i32 @llvm.read_register.i32(metadata !5) // AArch32: call i32 @llvm.read_register.i32(metadata ![[M4:[0-9]]])
void *test_rsrp() { void *test_rsrp() {
return __arm_rsrp("sysreg"); return __arm_rsrp("sysreg");
} }
// ARM-LABEL: test_wsr // ARM-LABEL: test_wsr
// AArch64: call void @llvm.write_register.i64(metadata !1, i64 %{{.*}}) // AArch64: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %{{.*}})
// AArch32: call void @llvm.write_register.i32(metadata !3, i32 %{{.*}}) // AArch32: call void @llvm.write_register.i32(metadata ![[M2:[0-9]]], i32 %{{.*}})
void test_wsr(uint32_t v) { void test_wsr(uint32_t v) {
#ifdef __ARM_32BIT_STATE #ifdef __ARM_32BIT_STATE
__arm_wsr("cp1:2:c3:c4:5", v); __arm_wsr("cp1:2:c3:c4:5", v);
#else #else
__arm_wsr("1:2:3:4:5", v); __arm_wsr("1:2:3:4:5", v);
#endif #endif
} }
// ARM-LABEL: test_wsr64 // ARM-LABEL: test_wsr64
// AArch64: call void @llvm.write_register.i64(metadata !1, i64 %{{.*}}) // AArch64: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %{{.*}})
// AArch32: call void @llvm.write_register.i64(metadata !4, i64 %{{.*}}) // AArch32: call void @llvm.write_register.i64(metadata ![[M3:[0-9]]], i64 %{{.*}})
void test_wsr64(uint64_t v) { void test_wsr64(uint64_t v) {
#ifdef __ARM_32BIT_STATE #ifdef __ARM_32BIT_STATE
__arm_wsr64("cp1:2:c3", v); __arm_wsr64("cp1:2:c3", v);
#else #else
__arm_wsr64("1:2:3:4:5", v); __arm_wsr64("1:2:3:4:5", v);
#endif #endif
} }
// ARM-LABEL: test_wsrp // ARM-LABEL: test_wsrp
// AArch64: call void @llvm.write_register.i64(metadata !2, i64 %{{.*}}) // AArch64: call void @llvm.write_register.i64(metadata ![[M1:[0-9]]], i64 %{{.*}})
// AArch32: call void @llvm.write_register.i32(metadata !5, i32 %{{.*}}) // AArch32: call void @llvm.write_register.i32(metadata ![[M4:[0-9]]], i32 %{{.*}})
void test_wsrp(void *v) { void test_wsrp(void *v) {
__arm_wsrp("sysreg", v); __arm_wsrp("sysreg", v);
} }
// AArch32: !3 = !{!"cp1:2:c3:c4:5"} // AArch32: ![[M2]] = !{!"cp1:2:c3:c4:5"}
// AArch32: !4 = !{!"cp1:2:c3"} // AArch32: ![[M3]] = !{!"cp1:2:c3"}
// AArch32: !5 = !{!"sysreg"} // AArch32: ![[M4]] = !{!"sysreg"}
// AArch64: !1 = !{!"1:2:3:4:5"} // AArch64: ![[M0]] = !{!"1:2:3:4:5"}
// AArch64: !2 = !{!"sysreg"} // AArch64: ![[M1]] = !{!"sysreg"}

cfe/trunk/test/CodeGen/builtins-arm64.c

Show All 39 Lines// CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 0, i32 0, i32 1)
__builtin_arm_prefetch(0, 0, 0, 1, 1); // pldl1strm __builtin_arm_prefetch(0, 0, 0, 1, 1); // pldl1strm
// CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 0, i32 0, i32 1) // CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 0, i32 0, i32 1)
__builtin_arm_prefetch(0, 0, 0, 0, 0); // plil1keep __builtin_arm_prefetch(0, 0, 0, 0, 0); // plil1keep
// CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 0, i32 3, i32 0) // CHECK: call {{.*}} @llvm.prefetch(i8* null, i32 0, i32 3, i32 0)
} }
unsigned rsr() { unsigned rsr() {
// CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i64 @llvm.read_register.i64(metadata !1) // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])
// CHECK-NEXT: trunc i64 [[V0]] to i32 // CHECK-NEXT: trunc i64 [[V0]] to i32
return __builtin_arm_rsr("1:2:3:4:5"); return __builtin_arm_rsr("1:2:3:4:5");
} }
unsigned long rsr64() { unsigned long rsr64() {
// CHECK: call i64 @llvm.read_register.i64(metadata !1) // CHECK: call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])
return __builtin_arm_rsr64("1:2:3:4:5"); return __builtin_arm_rsr64("1:2:3:4:5");
} }
void *rsrp() { void *rsrp() {
// CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i64 @llvm.read_register.i64(metadata !1) // CHECK: [[V0:[%A-Za-z0-9.]+]] = {{.*}} call i64 @llvm.read_register.i64(metadata ![[M0:[0-9]]])
// CHECK-NEXT: inttoptr i64 [[V0]] to i8* // CHECK-NEXT: inttoptr i64 [[V0]] to i8*
return __builtin_arm_rsrp("1:2:3:4:5"); return __builtin_arm_rsrp("1:2:3:4:5");
} }
void wsr(unsigned v) { void wsr(unsigned v) {
// CHECK: [[V0:[%A-Za-z0-9.]+]] = zext i32 %v to i64 // CHECK: [[V0:[%A-Za-z0-9.]+]] = zext i32 %v to i64
// CHECK-NEXT: call void @llvm.write_register.i64(metadata !1, i64 [[V0]]) // CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 [[V0]])
__builtin_arm_wsr("1:2:3:4:5", v); __builtin_arm_wsr("1:2:3:4:5", v);
} }
void wsr64(unsigned long v) { void wsr64(unsigned long v) {
// CHECK: call void @llvm.write_register.i64(metadata !1, i64 %v) // CHECK: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 %v)
__builtin_arm_wsr64("1:2:3:4:5", v); __builtin_arm_wsr64("1:2:3:4:5", v);
} }
void wsrp(void *v) { void wsrp(void *v) {
// CHECK: [[V0:[%A-Za-z0-9.]+]] = ptrtoint i8* %v to i64 // CHECK: [[V0:[%A-Za-z0-9.]+]] = ptrtoint i8* %v to i64
// CHECK-NEXT: call void @llvm.write_register.i64(metadata !1, i64 [[V0]]) // CHECK-NEXT: call void @llvm.write_register.i64(metadata ![[M0:[0-9]]], i64 [[V0]])
__builtin_arm_wsrp("1:2:3:4:5", v); __builtin_arm_wsrp("1:2:3:4:5", v);
} }
// CHECK: !1 = !{!"1:2:3:4:5"} // CHECK: ![[M0]] = !{!"1:2:3:4:5"}