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Differential D10275

[ARM]: Add support for MMFR4_EL1 (memory model feature register) in assembler.
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Authored by javed.absar on Jun 5 2015, 2:28 AM.

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Reviewers
t.p.northover
Summary

This patch adds support for system register MMFR4_EL1 (memory model feature register) in the assembler. This register provides information about the implemented memory model and memory management support.

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Event Timeline

javed.absar updated this revision to Diff 27185.Jun 5 2015, 2:28 AM
javed.absar retitled this revision from to [ARM]: Add support for MMFR4_EL1 (memory model feature register) in assembler..
javed.absar updated this object.
javed.absar edited the test plan for this revision. (Show Details)
javed.absar set the repository for this revision to rL LLVM.
javed.absar added a subscriber: Unknown Object (MLST).
Herald added subscribers: aemerson, rengolin. · View Herald TranscriptJun 5 2015, 2:28 AM
t.p.northover accepted this revision.Jun 5 2015, 9:26 AM
t.p.northover added a reviewer: t.p.northover.
t.p.northover added a subscriber: t.p.northover.

This looks fine to me.

Tim.

This revision is now accepted and ready to land.Jun 5 2015, 9:26 AM
Eugene.Zelenko closed this revision.Sep 21 2016, 5:04 PM
Eugene.Zelenko added a subscriber: Eugene.Zelenko.

Committed in r239302.

Revision Contents

PathSize
lib/
Target/
AArch64/
Utils/
1 line
1 line
test/
MC/
AArch64/
4 lines
2 lines
Disassembler/
AArch64/
2 lines

Diff 27185

lib/Target/AArch64/Utils/AArch64BaseInfo.h

Show First 20 Lines • Show All 597 Lines • ▼ Show 20 Lines enum SysRegROValues {
MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001 MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010 MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001 RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001 RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001 RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
ISR_EL1 = 0xc608, // 11 000 1100 0001 000 ISR_EL1 = 0xc608, // 11 000 1100 0001 000
CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001 CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010 CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
ID_MMFR4_EL1 = 0xc016, // 11 000 0000 0010 110
// Trace registers // Trace registers
TRCSTATR = 0x8818, // 10 001 0000 0011 000 TRCSTATR = 0x8818, // 10 001 0000 0011 000
TRCIDR8 = 0x8806, // 10 001 0000 0000 110 TRCIDR8 = 0x8806, // 10 001 0000 0000 110
TRCIDR9 = 0x880e, // 10 001 0000 0001 110 TRCIDR9 = 0x880e, // 10 001 0000 0001 110
TRCIDR10 = 0x8816, // 10 001 0000 0010 110 TRCIDR10 = 0x8816, // 10 001 0000 0010 110
TRCIDR11 = 0x881e, // 10 001 0000 0011 110 TRCIDR11 = 0x881e, // 10 001 0000 0011 110
TRCIDR12 = 0x8826, // 10 001 0000 0100 110 TRCIDR12 = 0x8826, // 10 001 0000 0100 110
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lib/Target/AArch64/Utils/AArch64BaseInfo.cpp

Show First 20 Lines • Show All 169 Lines • ▼ Show 20 Linesconst AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
{"id_pfr0_el1", ID_PFR0_EL1, {}}, {"id_pfr0_el1", ID_PFR0_EL1, {}},
{"id_pfr1_el1", ID_PFR1_EL1, {}}, {"id_pfr1_el1", ID_PFR1_EL1, {}},
{"id_dfr0_el1", ID_DFR0_EL1, {}}, {"id_dfr0_el1", ID_DFR0_EL1, {}},
{"id_afr0_el1", ID_AFR0_EL1, {}}, {"id_afr0_el1", ID_AFR0_EL1, {}},
{"id_mmfr0_el1", ID_MMFR0_EL1, {}}, {"id_mmfr0_el1", ID_MMFR0_EL1, {}},
{"id_mmfr1_el1", ID_MMFR1_EL1, {}}, {"id_mmfr1_el1", ID_MMFR1_EL1, {}},
{"id_mmfr2_el1", ID_MMFR2_EL1, {}}, {"id_mmfr2_el1", ID_MMFR2_EL1, {}},
{"id_mmfr3_el1", ID_MMFR3_EL1, {}}, {"id_mmfr3_el1", ID_MMFR3_EL1, {}},
{"id_mmfr4_el1", ID_MMFR4_EL1, {}},
{"id_isar0_el1", ID_ISAR0_EL1, {}}, {"id_isar0_el1", ID_ISAR0_EL1, {}},
{"id_isar1_el1", ID_ISAR1_EL1, {}}, {"id_isar1_el1", ID_ISAR1_EL1, {}},
{"id_isar2_el1", ID_ISAR2_EL1, {}}, {"id_isar2_el1", ID_ISAR2_EL1, {}},
{"id_isar3_el1", ID_ISAR3_EL1, {}}, {"id_isar3_el1", ID_ISAR3_EL1, {}},
{"id_isar4_el1", ID_ISAR4_EL1, {}}, {"id_isar4_el1", ID_ISAR4_EL1, {}},
{"id_isar5_el1", ID_ISAR5_EL1, {}}, {"id_isar5_el1", ID_ISAR5_EL1, {}},
{"id_aa64pfr0_el1", ID_A64PFR0_EL1, {}}, {"id_aa64pfr0_el1", ID_A64PFR0_EL1, {}},
{"id_aa64pfr1_el1", ID_A64PFR1_EL1, {}}, {"id_aa64pfr1_el1", ID_A64PFR1_EL1, {}},
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test/MC/AArch64/basic-a64-diagnostics.s

Show First 20 Lines • Show All 3,488 Lines • ▼ Show 20 Lines// write-only registers actually are.
msr ID_PFR0_EL1, x12 msr ID_PFR0_EL1, x12
msr ID_PFR1_EL1, x12 msr ID_PFR1_EL1, x12
msr ID_DFR0_EL1, x12 msr ID_DFR0_EL1, x12
msr ID_AFR0_EL1, x12 msr ID_AFR0_EL1, x12
msr ID_MMFR0_EL1, x12 msr ID_MMFR0_EL1, x12
msr ID_MMFR1_EL1, x12 msr ID_MMFR1_EL1, x12
msr ID_MMFR2_EL1, x12 msr ID_MMFR2_EL1, x12
msr ID_MMFR3_EL1, x12 msr ID_MMFR3_EL1, x12
msr ID_MMFR4_EL1, x12
msr ID_ISAR0_EL1, x12 msr ID_ISAR0_EL1, x12
msr ID_ISAR1_EL1, x12 msr ID_ISAR1_EL1, x12
msr ID_ISAR2_EL1, x12 msr ID_ISAR2_EL1, x12
msr ID_ISAR3_EL1, x12 msr ID_ISAR3_EL1, x12
msr ID_ISAR4_EL1, x12 msr ID_ISAR4_EL1, x12
msr ID_ISAR5_EL1, x12 msr ID_ISAR5_EL1, x12
msr MVFR0_EL1, x12 msr MVFR0_EL1, x12
msr MVFR1_EL1, x12 msr MVFR1_EL1, x12
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// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr ID_MMFR2_EL1, x12 // CHECK-ERROR-NEXT: msr ID_MMFR2_EL1, x12
// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr ID_MMFR3_EL1, x12 // CHECK-ERROR-NEXT: msr ID_MMFR3_EL1, x12
// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr ID_MMFR4_EL1, x12
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr ID_ISAR0_EL1, x12 // CHECK-ERROR-NEXT: msr ID_ISAR0_EL1, x12
// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr ID_ISAR1_EL1, x12 // CHECK-ERROR-NEXT: msr ID_ISAR1_EL1, x12
// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: expected writable system register or pstate // CHECK-ERROR-NEXT: error: expected writable system register or pstate
// CHECK-ERROR-NEXT: msr ID_ISAR2_EL1, x12 // CHECK-ERROR-NEXT: msr ID_ISAR2_EL1, x12
// CHECK-ERROR-NEXT: ^ // CHECK-ERROR-NEXT: ^
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test/MC/AArch64/basic-a64-instructions.s

Show First 20 Lines • Show All 4,300 Lines • ▼ Show 20 Lines// CHECK: msr {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12 // encoding: [0xcc,0xef,0x1b,0xd5]
mrs x9, ID_PFR0_EL1 mrs x9, ID_PFR0_EL1
mrs x9, ID_PFR1_EL1 mrs x9, ID_PFR1_EL1
mrs x9, ID_DFR0_EL1 mrs x9, ID_DFR0_EL1
mrs x9, ID_AFR0_EL1 mrs x9, ID_AFR0_EL1
mrs x9, ID_MMFR0_EL1 mrs x9, ID_MMFR0_EL1
mrs x9, ID_MMFR1_EL1 mrs x9, ID_MMFR1_EL1
mrs x9, ID_MMFR2_EL1 mrs x9, ID_MMFR2_EL1
mrs x9, ID_MMFR3_EL1 mrs x9, ID_MMFR3_EL1
mrs x9, ID_MMFR4_EL1
mrs x9, ID_ISAR0_EL1 mrs x9, ID_ISAR0_EL1
mrs x9, ID_ISAR1_EL1 mrs x9, ID_ISAR1_EL1
mrs x9, ID_ISAR2_EL1 mrs x9, ID_ISAR2_EL1
mrs x9, ID_ISAR3_EL1 mrs x9, ID_ISAR3_EL1
mrs x9, ID_ISAR4_EL1 mrs x9, ID_ISAR4_EL1
mrs x9, ID_ISAR5_EL1 mrs x9, ID_ISAR5_EL1
mrs x9, MVFR0_EL1 mrs x9, MVFR0_EL1
mrs x9, MVFR1_EL1 mrs x9, MVFR1_EL1
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// CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}} // encoding: [0x09,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}} // encoding: [0x09,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}} // encoding: [0x29,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}} // encoding: [0x29,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}} // encoding: [0x49,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}} // encoding: [0x49,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}} // encoding: [0x69,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}} // encoding: [0x69,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}} // encoding: [0x89,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}} // encoding: [0x89,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}} // encoding: [0xa9,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}} // encoding: [0xa9,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}} // encoding: [0xc9,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}} // encoding: [0xc9,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}} // encoding: [0xe9,0x01,0x38,0xd5] // CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}} // encoding: [0xe9,0x01,0x38,0xd5]
// CHECK: mrs x9, {{id_mmfr4_el1|ID_MMFR4_EL1}} // encoding: [0xc9,0x02,0x38,0xd5]
// CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}} // encoding: [0x09,0x02,0x38,0xd5] // CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}} // encoding: [0x09,0x02,0x38,0xd5]
// CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}} // encoding: [0x29,0x02,0x38,0xd5] // CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}} // encoding: [0x29,0x02,0x38,0xd5]
// CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}} // encoding: [0x49,0x02,0x38,0xd5] // CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}} // encoding: [0x49,0x02,0x38,0xd5]
// CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}} // encoding: [0x69,0x02,0x38,0xd5] // CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}} // encoding: [0x69,0x02,0x38,0xd5]
// CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}} // encoding: [0x89,0x02,0x38,0xd5] // CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}} // encoding: [0x89,0x02,0x38,0xd5]
// CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}} // encoding: [0xa9,0x02,0x38,0xd5] // CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}} // encoding: [0xa9,0x02,0x38,0xd5]
// CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}} // encoding: [0x09,0x03,0x38,0xd5] // CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}} // encoding: [0x09,0x03,0x38,0xd5]
// CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}} // encoding: [0x29,0x03,0x38,0xd5] // CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}} // encoding: [0x29,0x03,0x38,0xd5]
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test/MC/Disassembler/AArch64/basic-a64-instructions.txt

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# CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}} # CHECK: mrs x9, {{id_pfr0_el1|ID_PFR0_EL1}}
# CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}} # CHECK: mrs x9, {{id_pfr1_el1|ID_PFR1_EL1}}
# CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}} # CHECK: mrs x9, {{id_dfr0_el1|ID_DFR0_EL1}}
# CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}} # CHECK: mrs x9, {{id_afr0_el1|ID_AFR0_EL1}}
# CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}} # CHECK: mrs x9, {{id_mmfr0_el1|ID_MMFR0_EL1}}
# CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}} # CHECK: mrs x9, {{id_mmfr1_el1|ID_MMFR1_EL1}}
# CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}} # CHECK: mrs x9, {{id_mmfr2_el1|ID_MMFR2_EL1}}
# CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}} # CHECK: mrs x9, {{id_mmfr3_el1|ID_MMFR3_EL1}}
# CHECK: mrs x9, {{id_mmfr4_el1|ID_MMFR4_EL1}}
# CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}} # CHECK: mrs x9, {{id_isar0_el1|ID_ISAR0_EL1}}
# CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}} # CHECK: mrs x9, {{id_isar1_el1|ID_ISAR1_EL1}}
# CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}} # CHECK: mrs x9, {{id_isar2_el1|ID_ISAR2_EL1}}
# CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}} # CHECK: mrs x9, {{id_isar3_el1|ID_ISAR3_EL1}}
# CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}} # CHECK: mrs x9, {{id_isar4_el1|ID_ISAR4_EL1}}
# CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}} # CHECK: mrs x9, {{id_isar5_el1|ID_ISAR5_EL1}}
# CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}} # CHECK: mrs x9, {{mvfr0_el1|MVFR0_EL1}}
# CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}} # CHECK: mrs x9, {{mvfr1_el1|MVFR1_EL1}}
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0x9 0x1 0x38 0xd5 0x9 0x1 0x38 0xd5
0x29 0x1 0x38 0xd5 0x29 0x1 0x38 0xd5
0x49 0x1 0x38 0xd5 0x49 0x1 0x38 0xd5
0x69 0x1 0x38 0xd5 0x69 0x1 0x38 0xd5
0x89 0x1 0x38 0xd5 0x89 0x1 0x38 0xd5
0xa9 0x1 0x38 0xd5 0xa9 0x1 0x38 0xd5
0xc9 0x1 0x38 0xd5 0xc9 0x1 0x38 0xd5
0xe9 0x1 0x38 0xd5 0xe9 0x1 0x38 0xd5
0xc9 0x2 0x38 0xd5
0x9 0x2 0x38 0xd5 0x9 0x2 0x38 0xd5
0x29 0x2 0x38 0xd5 0x29 0x2 0x38 0xd5
0x49 0x2 0x38 0xd5 0x49 0x2 0x38 0xd5
0x69 0x2 0x38 0xd5 0x69 0x2 0x38 0xd5
0x89 0x2 0x38 0xd5 0x89 0x2 0x38 0xd5
0xa9 0x2 0x38 0xd5 0xa9 0x2 0x38 0xd5
0x9 0x3 0x38 0xd5 0x9 0x3 0x38 0xd5
0x29 0x3 0x38 0xd5 0x29 0x3 0x38 0xd5
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