[ARM]: Add support for MMFR4_EL1 (memory model feature register) in assembler.

[javed.absar]

Summary

This patch adds support for system register MMFR4_EL1 (memory model feature register) in the assembler. This register provides information about the implemented memory model and memory management support.

[t.p.northover]

This looks fine to me. Wonder how we missed it before.

Tim.

[javed.absar]

Hi Tim :
I abandoned this review (forgot to add llvm-commits in subscribers) and instead created a new one: http://reviews.llvm.org/D10275.
Could you please LGTM that if its ok (its identical to this one except for subscribers lists).
Thanks.

lib/Target/AArch64/Utils/AArch64BaseInfo.h

enum SysRegROValues {
     MVFR1_EL1         = 0xc019, // 11  000  0000  0011  001
     MVFR2_EL1         = 0xc01a, // 11  000  0000  0011  010
     RVBAR_EL1         = 0xc601, // 11  000  1100  0000  001
     RVBAR_EL2         = 0xe601, // 11  100  1100  0000  001
     RVBAR_EL3         = 0xf601, // 11  110  1100  0000  001
     ISR_EL1           = 0xc608, // 11  000  1100  0001  000
     CNTPCT_EL0        = 0xdf01, // 11  011  1110  0000  001
     CNTVCT_EL0        = 0xdf02,  // 11  011  1110  0000  010
+    ID_MMFR4_EL1      = 0xc016,  // 11  000  0000  0010  110
 
     // Trace registers
     TRCSTATR          = 0x8818, // 10  001  0000  0011  000
     TRCIDR8           = 0x8806, // 10  001  0000  0000  110
     TRCIDR9           = 0x880e, // 10  001  0000  0001  110
     TRCIDR10          = 0x8816, // 10  001  0000  0010  110
     TRCIDR11          = 0x881e, // 10  001  0000  0011  110
     TRCIDR12          = 0x8826, // 10  001  0000  0100  110

lib/Target/AArch64/Utils/AArch64BaseInfo.cpp

const AArch64NamedImmMapper::Mapping AArch64SysReg::MRSMapper::MRSMappings[] = {
   {"id_pfr0_el1", ID_PFR0_EL1, {}},
   {"id_pfr1_el1", ID_PFR1_EL1, {}},
   {"id_dfr0_el1", ID_DFR0_EL1, {}},
   {"id_afr0_el1", ID_AFR0_EL1, {}},
   {"id_mmfr0_el1", ID_MMFR0_EL1, {}},
   {"id_mmfr1_el1", ID_MMFR1_EL1, {}},
   {"id_mmfr2_el1", ID_MMFR2_EL1, {}},
   {"id_mmfr3_el1", ID_MMFR3_EL1, {}},
+  {"id_mmfr4_el1", ID_MMFR4_EL1, {}},
   {"id_isar0_el1", ID_ISAR0_EL1, {}},
   {"id_isar1_el1", ID_ISAR1_EL1, {}},
   {"id_isar2_el1", ID_ISAR2_EL1, {}},
   {"id_isar3_el1", ID_ISAR3_EL1, {}},
   {"id_isar4_el1", ID_ISAR4_EL1, {}},
   {"id_isar5_el1", ID_ISAR5_EL1, {}},
   {"id_aa64pfr0_el1", ID_A64PFR0_EL1, {}},
   {"id_aa64pfr1_el1", ID_A64PFR1_EL1, {}},

test/MC/AArch64/basic-a64-diagnostics.s

// write-only registers actually are.
         msr ID_PFR0_EL1, x12
         msr ID_PFR1_EL1, x12
         msr ID_DFR0_EL1, x12
         msr ID_AFR0_EL1, x12
         msr ID_MMFR0_EL1, x12
         msr ID_MMFR1_EL1, x12
         msr ID_MMFR2_EL1, x12
         msr ID_MMFR3_EL1, x12
+        msr ID_MMFR4_EL1, x12
         msr ID_ISAR0_EL1, x12
         msr ID_ISAR1_EL1, x12
         msr ID_ISAR2_EL1, x12
         msr ID_ISAR3_EL1, x12
         msr ID_ISAR4_EL1, x12
         msr ID_ISAR5_EL1, x12
         msr MVFR0_EL1, x12
         msr MVFR1_EL1, x12

 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_MMFR2_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_MMFR3_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
+// CHECK-ERROR-NEXT:         msr ID_MMFR4_EL1, x12
+// CHECK-ERROR-NEXT:             ^
+// CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_ISAR0_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_ISAR1_EL1, x12
 // CHECK-ERROR-NEXT:             ^
 // CHECK-ERROR-NEXT: error: expected writable system register or pstate
 // CHECK-ERROR-NEXT:         msr ID_ISAR2_EL1, x12
 // CHECK-ERROR-NEXT:             ^

test/MC/AArch64/basic-a64-instructions.s

// CHECK: msr      {{pmevtyper30_el0|PMEVTYPER30_EL0}}, x12       // encoding: [0xcc,0xef,0x1b,0xd5]
   mrs x9, ID_PFR0_EL1
   mrs x9, ID_PFR1_EL1
   mrs x9, ID_DFR0_EL1
   mrs x9, ID_AFR0_EL1
   mrs x9, ID_MMFR0_EL1
   mrs x9, ID_MMFR1_EL1
   mrs x9, ID_MMFR2_EL1
   mrs x9, ID_MMFR3_EL1
+  mrs x9, ID_MMFR4_EL1
   mrs x9, ID_ISAR0_EL1
   mrs x9, ID_ISAR1_EL1
   mrs x9, ID_ISAR2_EL1
   mrs x9, ID_ISAR3_EL1
   mrs x9, ID_ISAR4_EL1
   mrs x9, ID_ISAR5_EL1
   mrs x9, MVFR0_EL1
   mrs x9, MVFR1_EL1

 // CHECK: mrs      x9, {{id_pfr0_el1|ID_PFR0_EL1}}            // encoding: [0x09,0x01,0x38,0xd5]
 // CHECK: mrs      x9, {{id_pfr1_el1|ID_PFR1_EL1}}            // encoding: [0x29,0x01,0x38,0xd5]
 // CHECK: mrs      x9, {{id_dfr0_el1|ID_DFR0_EL1}}            // encoding: [0x49,0x01,0x38,0xd5]
 // CHECK: mrs      x9, {{id_afr0_el1|ID_AFR0_EL1}}            // encoding: [0x69,0x01,0x38,0xd5]
 // CHECK: mrs      x9, {{id_mmfr0_el1|ID_MMFR0_EL1}}           // encoding: [0x89,0x01,0x38,0xd5]
 // CHECK: mrs      x9, {{id_mmfr1_el1|ID_MMFR1_EL1}}           // encoding: [0xa9,0x01,0x38,0xd5]
 // CHECK: mrs      x9, {{id_mmfr2_el1|ID_MMFR2_EL1}}           // encoding: [0xc9,0x01,0x38,0xd5]
 // CHECK: mrs      x9, {{id_mmfr3_el1|ID_MMFR3_EL1}}           // encoding: [0xe9,0x01,0x38,0xd5]
+// CHECK: mrs      x9, {{id_mmfr4_el1|ID_MMFR4_EL1}}           // encoding: [0xc9,0x02,0x38,0xd5]
 // CHECK: mrs      x9, {{id_isar0_el1|ID_ISAR0_EL1}}           // encoding: [0x09,0x02,0x38,0xd5]
 // CHECK: mrs      x9, {{id_isar1_el1|ID_ISAR1_EL1}}           // encoding: [0x29,0x02,0x38,0xd5]
 // CHECK: mrs      x9, {{id_isar2_el1|ID_ISAR2_EL1}}           // encoding: [0x49,0x02,0x38,0xd5]
 // CHECK: mrs      x9, {{id_isar3_el1|ID_ISAR3_EL1}}           // encoding: [0x69,0x02,0x38,0xd5]
 // CHECK: mrs      x9, {{id_isar4_el1|ID_ISAR4_EL1}}           // encoding: [0x89,0x02,0x38,0xd5]
 // CHECK: mrs      x9, {{id_isar5_el1|ID_ISAR5_EL1}}           // encoding: [0xa9,0x02,0x38,0xd5]
 // CHECK: mrs      x9, {{mvfr0_el1|MVFR0_EL1}}              // encoding: [0x09,0x03,0x38,0xd5]
 // CHECK: mrs      x9, {{mvfr1_el1|MVFR1_EL1}}              // encoding: [0x29,0x03,0x38,0xd5]

test/MC/Disassembler/AArch64/basic-a64-instructions.txt

 # CHECK: mrs      x9, {{id_pfr0_el1|ID_PFR0_EL1}}
 # CHECK: mrs      x9, {{id_pfr1_el1|ID_PFR1_EL1}}
 # CHECK: mrs      x9, {{id_dfr0_el1|ID_DFR0_EL1}}
 # CHECK: mrs      x9, {{id_afr0_el1|ID_AFR0_EL1}}
 # CHECK: mrs      x9, {{id_mmfr0_el1|ID_MMFR0_EL1}}
 # CHECK: mrs      x9, {{id_mmfr1_el1|ID_MMFR1_EL1}}
 # CHECK: mrs      x9, {{id_mmfr2_el1|ID_MMFR2_EL1}}
 # CHECK: mrs      x9, {{id_mmfr3_el1|ID_MMFR3_EL1}}
+# CHECK: mrs      x9, {{id_mmfr4_el1|ID_MMFR4_EL1}}
 # CHECK: mrs      x9, {{id_isar0_el1|ID_ISAR0_EL1}}
 # CHECK: mrs      x9, {{id_isar1_el1|ID_ISAR1_EL1}}
 # CHECK: mrs      x9, {{id_isar2_el1|ID_ISAR2_EL1}}
 # CHECK: mrs      x9, {{id_isar3_el1|ID_ISAR3_EL1}}
 # CHECK: mrs      x9, {{id_isar4_el1|ID_ISAR4_EL1}}
 # CHECK: mrs      x9, {{id_isar5_el1|ID_ISAR5_EL1}}
 # CHECK: mrs      x9, {{mvfr0_el1|MVFR0_EL1}}
 # CHECK: mrs      x9, {{mvfr1_el1|MVFR1_EL1}}

 0x9 0x1 0x38 0xd5
 0x29 0x1 0x38 0xd5
 0x49 0x1 0x38 0xd5
 0x69 0x1 0x38 0xd5
 0x89 0x1 0x38 0xd5
 0xa9 0x1 0x38 0xd5
 0xc9 0x1 0x38 0xd5
 0xe9 0x1 0x38 0xd5
+0xc9 0x2 0x38 0xd5
 0x9 0x2 0x38 0xd5
 0x29 0x2 0x38 0xd5
 0x49 0x2 0x38 0xd5
 0x69 0x2 0x38 0xd5
 0x89 0x2 0x38 0xd5
 0xa9 0x2 0x38 0xd5
 0x9 0x3 0x38 0xd5
 0x29 0x3 0x38 0xd5