This is an archive of the discontinued LLVM Phabricator instance.

Differential D9833

[Sparc] Add support for flush instruction.
ClosedPublic

Authored by jyknight on May 18 2015, 1:44 PM.

Details

Reviewers
venkatra
Commits
rG7208a12eef68: [Sparc] Add support for flush instruction.
rL241460: [Sparc] Add support for flush instruction.

Diff Detail

Event Timeline

jyknight updated this revision to Diff 26008.May 18 2015, 1:44 PM
jyknight retitled this revision from to [Sparc] Add support for flush instruction..
jyknight updated this object.
jyknight edited the test plan for this revision. (Show Details)
jyknight added subscribers: venkatra, Unknown Object (MLST).
jyknight added a comment.Jul 1 2015, 7:44 AM

Ping.

venkatra accepted this revision.Jul 2 2015, 12:38 AM
venkatra added a reviewer: venkatra.

LGTM

This revision is now accepted and ready to land.Jul 2 2015, 12:38 AM
Closed by commit rL241460: [Sparc] Add support for flush instruction. (authored by jyknight). · Explain WhyJul 6 2015, 9:01 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Sparc/
3 lines
14 lines
test/
MC/
Sparc/
10 lines

Diff 26008

lib/Target/Sparc/SparcInstrAliases.td

Show First 20 Lines • Show All 300 Lines • ▼ Show 20 Lines
def : InstAlias<"ret", (RET 8)>; def : InstAlias<"ret", (RET 8)>;
// mov reg, rd -> or %g0, reg, rd // mov reg, rd -> or %g0, reg, rd
def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>; def : InstAlias<"mov $rs2, $rd", (ORrr IntRegs:$rd, G0, IntRegs:$rs2)>;
// mov simm13, rd -> or %g0, simm13, rd // mov simm13, rd -> or %g0, simm13, rd
def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>; def : InstAlias<"mov $simm13, $rd", (ORri IntRegs:$rd, G0, i32imm:$simm13)>;
// flush -> flush %g0
def : InstAlias<"flush", (FLUSH), 0>;
// set value, rd // set value, rd
// (turns into a sequence of sethi+or, depending on the value) // (turns into a sequence of sethi+or, depending on the value)
// def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>; // def : InstAlias<"set $val, $rd", (ORri IntRegs:$rd, (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">; def SET : AsmPseudoInst<(outs IntRegs:$rd), (ins i32imm:$val), "set $val, $rd">;
// restore -> restore %g0, %g0, %g0 // restore -> restore %g0, %g0, %g0
def : InstAlias<"restore", (RESTORErr G0, G0, G0)>; def : InstAlias<"restore", (RESTORErr G0, G0, G0)>;
Show All 21 Lines

lib/Target/Sparc/SparcInstrInfo.td

Show First 20 Lines • Show All 828 Lines • ▼ Show 20 Lineslet hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in
def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>; def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
// Section B.31 - Unimplmented Instruction // Section B.31 - Unimplmented Instruction
let rd = 0 in let rd = 0 in
def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22), def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
"unimp $imm22", []>; "unimp $imm22", []>;
// Section B.32 - Flush Instruction Memory
let rd = 0 in {
def FLUSHrr : F3_1<2, 0b111011, (outs), (ins MEMrr:$addr),
"flush $addr", []>;
def FLUSHri : F3_2<2, 0b111011, (outs), (ins MEMri:$addr),
"flush $addr", []>;
// The no-arg FLUSH is only here for the benefit of the InstAlias
// "flush", which cannot seem to use FLUSHrr, due to the inability
// to construct a MEMrr with fixed G0 registers.
let rs1 = 0, rs2 = 0 in
def FLUSH : F3_1<2, 0b111011, (outs), (ins), "flush %g0", []>;
}
// Section B.33 - Floating-point Operate (FPop) Instructions // Section B.33 - Floating-point Operate (FPop) Instructions
// Convert Integer to Floating-point Instructions, p. 141 // Convert Integer to Floating-point Instructions, p. 141
def FITOS : F3_3u<2, 0b110100, 0b011000100, def FITOS : F3_3u<2, 0b110100, 0b011000100,
(outs FPRegs:$rd), (ins FPRegs:$rs2), (outs FPRegs:$rd), (ins FPRegs:$rs2),
"fitos $rs2, $rd", "fitos $rs2, $rd",
[(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>; [(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>;
def FITOD : F3_3u<2, 0b110100, 0b011001000, def FITOD : F3_3u<2, 0b110100, 0b011001000,
▲ Show 20 Lines • Show All 492 Lines • Show Last 20 Lines

test/MC/Sparc/sparc-mem-instructions.s

Show First 20 Lines • Show All 84 Lines • ▼ Show 20 Lines! RUN: llvm-mc %s -arch=sparcv9 -show-encoding | FileCheck %s
! CHECK: std %o2, [%i0+%l6] ! encoding: [0xd4,0x3e,0x00,0x16] ! CHECK: std %o2, [%i0+%l6] ! encoding: [0xd4,0x3e,0x00,0x16]
std %o2, [%i0 + %l6] std %o2, [%i0 + %l6]
! CHECK: std %o2, [%i0+32] ! encoding: [0xd4,0x3e,0x20,0x20] ! CHECK: std %o2, [%i0+32] ! encoding: [0xd4,0x3e,0x20,0x20]
std %o2, [%i0 + 32] std %o2, [%i0 + 32]
! CHECK: std %o2, [%g1] ! encoding: [0xd4,0x38,0x40,0x00] ! CHECK: std %o2, [%g1] ! encoding: [0xd4,0x38,0x40,0x00]
std %o2, [%g1] std %o2, [%g1]
! CHECK: stda %o2, [%i0+%l6] 131 ! encoding: [0xd4,0xbe,0x10,0x76] ! CHECK: stda %o2, [%i0+%l6] 131 ! encoding: [0xd4,0xbe,0x10,0x76]
stda %o2, [%i0 + %l6] 131 stda %o2, [%i0 + %l6] 131
! CHECK: flush %g1+%g2 ! encoding: [0x81,0xd8,0x40,0x02]
flush %g1 + %g2
! CHECK: flush %g1+8 ! encoding: [0x81,0xd8,0x60,0x08]
flush %g1 + 8
! CHECK: flush %g1 ! encoding: [0x81,0xd8,0x40,0x00]
flush %g1
! Not specified in manual, but accepted by gas.
! CHECK: flush %g0 ! encoding: [0x81,0xd8,0x00,0x00]
flush