[clang] Update a test-case affected by IntToPtr/PtrToInt being folded into Loads

[philip.pfaffe]

Summary

When folding IntToPtr or PtrToInt into Loads as in {D9152: [InstCombine] Fold IntToPtr and PtrToInt into preceding loads.}, the mips-varargs test-case needs to be updated.

[chandlerc]

Looks good (assuming with the LLVM change).

cfe/trunk/test/CodeGen/mips-varargs.c

 }
 
 // ALL-LABEL: define i64 @test_i64(i8*{{.*}} %fmt, ...)
 //
 // ALL:   %va = alloca i8*, align [[PTRALIGN]]
 // ALL:   [[VA1:%.+]] = bitcast i8** %va to i8*
 // ALL:   call void @llvm.va_start(i8* [[VA1]])
 //
-// O32:   [[AP_CUR:%.+]] = load i8*, i8** %va, align [[PTRALIGN]]
+// O32:   [[TMP0:%.+]] = bitcast i8** %va to i32*
+// O32:   [[AP_CUR:%.+]] = load [[INTPTR_T:i32]], i32* [[TMP0]], align [[PTRALIGN]]
 // NEW:   [[TMP0:%.+]] = bitcast i8** %va to i64**
 // NEW:   [[AP_CUR:%.+]] = load i64*, i64** [[TMP0]], align [[PTRALIGN]]
 //
 // i64 is 8-byte aligned, while this is within O32's stack alignment there's no
 // guarantee that the offset is still 8-byte aligned after earlier reads.
-// O32:   [[PTR0:%.+]] = ptrtoint i8* [[AP_CUR]] to [[INTPTR_T:i32]]
-// O32:   [[PTR1:%.+]] = add i32 [[PTR0]], 7
+// O32:   [[PTR1:%.+]] = add i32 [[AP_CUR]], 7
 // O32:   [[PTR2:%.+]] = and i32 [[PTR1]], -8
 // O32:   [[PTR3:%.+]] = inttoptr [[INTPTR_T]] [[PTR2]] to i64*
 // O32:   [[PTR4:%.+]] = inttoptr [[INTPTR_T]] [[PTR2]] to i8*
 //
 // O32:   [[AP_NEXT:%.+]] = getelementptr i8, i8* [[PTR4]], [[INTPTR_T]] 8
 // NEW:   [[AP_NEXT:%.+]] = getelementptr i64, i64* [[AP_CUR]], [[INTPTR_T:i32|i64]] 1
 //
 // O32:   store i8* [[AP_NEXT]], i8** %va, align [[PTRALIGN]]
int test_v4i32(char *fmt, ...) {
   return v[0];
 }
 
 // ALL-LABEL: define i32 @test_v4i32(i8*{{.*}} %fmt, ...)
 //
 // ALL:   %va = alloca i8*, align [[PTRALIGN]]
 // ALL:   [[VA1:%.+]] = bitcast i8** %va to i8*
 // ALL:   call void @llvm.va_start(i8* [[VA1]])
-// ALL:   [[AP_CUR:%.+]] = load i8*, i8** %va, align [[PTRALIGN]]
 //
-// O32:   [[PTR0:%.+]] = ptrtoint i8* [[AP_CUR]] to [[INTPTR_T:i32]]
-// N32:   [[PTR0:%.+]] = ptrtoint i8* [[AP_CUR]] to [[INTPTR_T:i32]]
-// N64:   [[PTR0:%.+]] = ptrtoint i8* [[AP_CUR]] to [[INTPTR_T:i64]]
+// O32:   [[TMP0:%.+]] = bitcast i8** %va to i32*
+// N32:   [[TMP0:%.+]] = bitcast i8** %va to i32*
+// N64:   [[TMP0:%.+]] = bitcast i8** %va to i64*
+//
+// O32:   [[PTR0:%.+]] = load [[INTPTR_T:i32]], i32* [[TMP0]], align [[PTRALIGN]]
+// N32:   [[PTR0:%.+]] = load [[INTPTR_T:i32]], i32* [[TMP0]], align [[PTRALIGN]]
+// N64:   [[PTR0:%.+]] = load [[INTPTR_T:i64]], i64* [[TMP0]], align [[PTRALIGN]]
 //
 // Vectors are 16-byte aligned, however the O32 ABI has a maximum alignment of
 // 8-bytes since the base of the stack is 8-byte aligned.
 // O32:   [[PTR1:%.+]] = add i32 [[PTR0]], 7
 // O32:   [[PTR2:%.+]] = and i32 [[PTR1]], -8
 //
 // NEW:   [[PTR1:%.+]] = add [[INTPTR_T]] [[PTR0]], 15
 // NEW:   [[PTR2:%.+]] = and [[INTPTR_T]] [[PTR1]], -16