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[winasan] Fix strrchr interception with vs2019 CRT
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Authored by Christopher on Apr 3 2019, 10:19 AM.

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rG955b5a633138: [winasan] Fix strrchr interception with vs2019 CRT
rCRT357725: [winasan] Fix strrchr interception with vs2019 CRT
rL357725: [winasan] Fix strrchr interception with vs2019 CRT

Summary

strrchr in vs2019 CRT begins with unrecognized instructions.

VCRUNTIME140!strrchr:
4533c9 xor r9d, r9d
4c8bc1 mov r8, rcx

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Repository: rL LLVM

Event Timeline

Christopher created this revision.Apr 3 2019, 10:19 AM

Thanks for the patch, would you like me to go ahead and land this?

This revision is now accepted and ready to land.Apr 3 2019, 1:30 PM

That would be great if it can be landed, thanks!

I finished overcoming other VS 2019 installation issues, ran into this issue, and confirmed that this patch fixes it. Thanks!

Closed by commit rL357725: [winasan] Fix strrchr interception with vs2019 CRT (authored by rnk). · Explain WhyApr 4 2019, 2:07 PM

This revision was automatically updated to reflect the committed changes.

Herald added a subscriber: delcypher. · View Herald TranscriptApr 4 2019, 2:07 PM

Revision Contents

Path

Size

compiler-rt/

trunk/

lib/

interception/

interception_win.cc

2 lines

Diff 193778

compiler-rt/trunk/lib/interception/interception_win.cc

Show First 20 Lines • Show All 506 Lines • ▼ Show 20 Lines	switch (0x00FFFFFF & (u32)address) {
case 0xc48b48: // 48 8b c4 : mov rax, rsp		case 0xc48b48: // 48 8b c4 : mov rax, rsp
case 0xd9f748: // 48 f7 d9 : neg rcx		case 0xd9f748: // 48 f7 d9 : neg rcx
case 0xd12b48: // 48 2b d1 : sub rdx, rcx		case 0xd12b48: // 48 2b d1 : sub rdx, rcx
case 0x07c1f6: // f6 c1 07 : test cl, 0x7		case 0x07c1f6: // f6 c1 07 : test cl, 0x7
case 0xc98548: // 48 85 C9 : test rcx, rcx		case 0xc98548: // 48 85 C9 : test rcx, rcx
case 0xc0854d: // 4d 85 c0 : test r8, r8		case 0xc0854d: // 4d 85 c0 : test r8, r8
case 0xc2b60f: // 0f b6 c2 : movzx eax, dl		case 0xc2b60f: // 0f b6 c2 : movzx eax, dl
case 0xc03345: // 45 33 c0 : xor r8d, r8d		case 0xc03345: // 45 33 c0 : xor r8d, r8d
		case 0xc93345: // 45 33 c9 : xor r9d, r9d
case 0xdb3345: // 45 33 DB : xor r11d, r11d		case 0xdb3345: // 45 33 DB : xor r11d, r11d
case 0xd98b4c: // 4c 8b d9 : mov r11, rcx		case 0xd98b4c: // 4c 8b d9 : mov r11, rcx
case 0xd28b4c: // 4c 8b d2 : mov r10, rdx		case 0xd28b4c: // 4c 8b d2 : mov r10, rdx
case 0xc98b4c: // 4C 8B C9 : mov r9, rcx		case 0xc98b4c: // 4C 8B C9 : mov r9, rcx
		case 0xc18b4c: // 4C 8B C1 : mov r8, rcx
case 0xd2b60f: // 0f b6 d2 : movzx edx, dl		case 0xd2b60f: // 0f b6 d2 : movzx edx, dl
case 0xca2b48: // 48 2b ca : sub rcx, rdx		case 0xca2b48: // 48 2b ca : sub rcx, rdx
case 0x10b70f: // 0f b7 10 : movzx edx, WORD PTR [rax]		case 0x10b70f: // 0f b7 10 : movzx edx, WORD PTR [rax]
case 0xc00b4d: // 3d 0b c0 : or r8, r8		case 0xc00b4d: // 3d 0b c0 : or r8, r8
case 0xd18b48: // 48 8b d1 : mov rdx, rcx		case 0xd18b48: // 48 8b d1 : mov rdx, rcx
case 0xdc8b4c: // 4c 8b dc : mov r11, rsp		case 0xdc8b4c: // 4c 8b dc : mov r11, rsp
case 0xd18b4c: // 4c 8b d1 : mov r10, rcx		case 0xd18b4c: // 4c 8b d1 : mov r10, rcx
case 0xE0E483: // 83 E4 E0 : and esp, 0xFFFFFFE0		case 0xE0E483: // 83 E4 E0 : and esp, 0xFFFFFFE0
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