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Differential D5804

R600: Fix nonsensical implementation of computeKnownBits for BFE
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Authored by arsenm on Oct 15 2014, 12:43 PM.

Details

Reviewers
arsenm
Summary

This was resulting in invalid simplifications of sdiv

Diff Detail

Event Timeline

arsenm updated this revision to Diff 14957.Oct 15 2014, 12:43 PM
arsenm retitled this revision from to R600: Fix nonsensical implementation of computeKnownBits for BFE .
arsenm updated this object.
arsenm edited the test plan for this revision. (Show Details)
arsenm added a subscriber: Unknown Object (MLST).
arsenm accepted this revision.Oct 16 2014, 1:18 PM
arsenm added a reviewer: arsenm.

r219953

This revision is now accepted and ready to land.Oct 16 2014, 1:18 PM
arsenm closed this revision.Oct 16 2014, 1:18 PM

Revision Contents

PathSize
lib/
Target/
R600/
6 lines
test/
CodeGen/
R600/
15 lines

Diff 14957

lib/Target/R600/AMDGPUISelLowering.cpp

Show First 20 Lines • Show All 991 Lines • ▼ Show 20 Lines
unsigned BitWidth = 32; unsigned BitWidth = 32;
uint32_t Width = CWidth->getZExtValue() & 0x1f; uint32_t Width = CWidth->getZExtValue() & 0x1f;
if (Width == 0) { if (Width == 0) {
KnownZero = APInt::getAllOnesValue(BitWidth); KnownZero = APInt::getAllOnesValue(BitWidth);
KnownOne = APInt::getNullValue(BitWidth); KnownOne = APInt::getNullValue(BitWidth);
return; return;
} }
// FIXME: This could do a lot more. If offset is 0, should be the same as if (Opc == AMDGPUISD::BFE_U32)
// sign_extend_inreg implementation, but that involves duplicating it.
if (Opc == AMDGPUISD::BFE_I32)
KnownOne = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
else
KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width); KnownZero = APInt::getHighBitsSet(BitWidth, BitWidth - Width);
break; break;
} }
} }
} }
unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode( unsigned AMDGPUTargetLowering::ComputeNumSignBitsForTargetNode(
Show All 28 Lines

test/CodeGen/R600/llvm.AMDGPU.bfe.i32.ll

Show First 20 Lines • Show All 418 Lines • ▼ Show 20 Lines
define void @bfe_sext_in_reg_i24(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { define void @bfe_sext_in_reg_i24(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
%x = load i32 addrspace(1)* %in, align 4 %x = load i32 addrspace(1)* %in, align 4
%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 0, i32 24) %bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %x, i32 0, i32 24)
%shl = shl i32 %bfe, 8 %shl = shl i32 %bfe, 8
%ashr = ashr i32 %shl, 8 %ashr = ashr i32 %shl, 8
store i32 %ashr, i32 addrspace(1)* %out, align 4 store i32 %ashr, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; FUNC-LABEL: @simplify_demanded_bfe_sdiv
; SI: BUFFER_LOAD_DWORD [[LOAD:v[0-9]+]]
; SI: V_BFE_I32 [[BFE:v[0-9]+]], [[LOAD]], 1, 16
; SI: V_LSHRREV_B32_e32 [[TMP0:v[0-9]+]], 31, [[BFE]]
; SI: V_ADD_I32_e32 [[TMP1:v[0-9]+]], [[TMP0]], [[BFE]]
; SI: V_ASHRREV_I32_e32 [[TMP2:v[0-9]+]], 1, [[TMP1]]
; SI: BUFFER_STORE_DWORD [[TMP2]]
define void @simplify_demanded_bfe_sdiv(i32 addrspace(1)* %out, i32 addrspace(1)* %in) nounwind {
%src = load i32 addrspace(1)* %in, align 4
%bfe = call i32 @llvm.AMDGPU.bfe.i32(i32 %src, i32 1, i32 16) nounwind readnone
%div = sdiv i32 %bfe, 2
store i32 %div, i32 addrspace(1)* %out, align 4
ret void
}