Add llvm.experimental.patchpoint.double

[kmod]

Summary

It didn't seem like there was anything special that had to be done besides
just defining the new intrinsic with the different return type.

It seems inelegant to create a new intrinsic for a new return type, but
we're running into a case where we'd like to return a double through a patchpoint
and I'm not sure of a better way to do that.

[atrick]

LGTM. I don't know of a better way to do this.

[ributzka]

If I recall correctly there should be a few places where the return type is hard-coded or assumed to be i64.

[kmod]

Ok, I took a more thorough look for any places that assume that
the return type is void or i64, and I was only able to find this one.

docs/StackMaps.rst

 ::
 
       declare void
         @llvm.experimental.patchpoint.void(i64 <id>, i32 <numBytes>,
                                            i8* <target>, i32 <numArgs>, ...)
       declare i64
         @llvm.experimental.patchpoint.i64(i64 <id>, i32 <numBytes>,
                                           i8* <target>, i32 <numArgs>, ...)
+      declare double
+        @llvm.experimental.patchpoint.double(i64 <id>, i32 <numBytes>,
+                                          i8* <target>, i32 <numArgs>, ...)
 
 Overview:
 """""""""
 
 The '``llvm.experimental.patchpoint.*``' intrinsics creates a function
 call to the specified ``<target>`` and records the location of specified
 values in the stack map.
 

include/llvm/IR/Intrinsics.td

def int_experimental_patchpoint_void : Intrinsic<[],
                                                   llvm_ptr_ty, llvm_i32_ty,
                                                   llvm_vararg_ty],
                                                   [Throws]>;
 def int_experimental_patchpoint_i64 : Intrinsic<[llvm_i64_ty],
                                                 [llvm_i64_ty, llvm_i32_ty,
                                                  llvm_ptr_ty, llvm_i32_ty,
                                                  llvm_vararg_ty],
                                                  [Throws]>;
+def int_experimental_patchpoint_double : Intrinsic<[llvm_double_ty],
+                                                [llvm_i64_ty, llvm_i32_ty,
+                                                 llvm_ptr_ty, llvm_i32_ty,
+                                                 llvm_vararg_ty],
+                                                 [Throws]>;
 
 //===-------------------------- Other Intrinsics --------------------------===//
 //
 def int_flt_rounds : Intrinsic<[llvm_i32_ty]>,
                      GCCBuiltin<"__builtin_flt_rounds">;
 def int_trap : Intrinsic<[], [], [IntrNoReturn]>,
                GCCBuiltin<"__builtin_trap">;
 def int_debugtrap : Intrinsic<[]>,

lib/CodeGen/SelectionDAG/FastISel.cpp

bool FastISel::selectPatchpoint(const CallInst *I) {
 
   assert(CLI.Call && "No call instruction specified.");
 
   SmallVector<MachineOperand, 32> Ops;
 
   // Add an explicit result reg if we use the anyreg calling convention.
   if (IsAnyRegCC && HasDef) {
     assert(CLI.NumResultRegs == 0 && "Unexpected result register.");
+    if (I->getType()->isIntegerTy(64))
       CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64));
+    else if (I->getType()->isDoubleTy())
+      CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::f64));
+    else
+      llvm_unreachable("unsupported patchpoint type");
     CLI.NumResultRegs = 1;
     Ops.push_back(MachineOperand::CreateReg(CLI.ResultReg, /*IsDef=*/true));
   }
 
   // Add the <id> and <numBytes> constants.
   assert(isa<ConstantInt>(I->getOperand(PatchPointOpers::IDPos)) &&
          "Expected a constant integer.");
   const auto *ID = cast<ConstantInt>(I->getOperand(PatchPointOpers::IDPos));
if (!ResultReg)
       return false;
     updateValueMap(II, ResultReg);
     return true;
   }
   case Intrinsic::experimental_stackmap:
     return selectStackmap(II);
   case Intrinsic::experimental_patchpoint_void:
   case Intrinsic::experimental_patchpoint_i64:
+  case Intrinsic::experimental_patchpoint_double:
     return selectPatchpoint(II);
   }
 
   return fastLowerIntrinsicCall(II);
 }
 
 bool FastISel::selectCast(const User *I, unsigned Opcode) {
   EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

if (isa<InlineAsm>(Callee)) {
     switch (Fn->getIntrinsicID()) {
       default:
         llvm_unreachable("Cannot invoke this intrinsic");
       case Intrinsic::donothing:
         // Ignore invokes to @llvm.donothing: jump directly to the next BB.
         break;
       case Intrinsic::experimental_patchpoint_void:
       case Intrinsic::experimental_patchpoint_i64:
+      case Intrinsic::experimental_patchpoint_double:
         visitPatchpoint(ImmutableCallSite(&I), LandingPad);
         break;
     }
   } else {
     LowerCallTo(&I, getValue(Callee), false, LandingPad);
   }
 
   // If the value of the invoke is used outside of its defining block, make it
SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
   case Intrinsic::donothing:
     // ignore
     return nullptr;
   case Intrinsic::experimental_stackmap: {
     visitStackmap(I);
     return nullptr;
   }
   case Intrinsic::experimental_patchpoint_void:
-  case Intrinsic::experimental_patchpoint_i64: {
+  case Intrinsic::experimental_patchpoint_i64:
+  case Intrinsic::experimental_patchpoint_double: {
     visitPatchpoint(ImmutableCallSite(&I), nullptr);
     return nullptr;
   }
   }
 }
 
 std::pair<SDValue, SDValue>
 SelectionDAGBuilder::LowerInvokable(TargetLowering::CallLoweringInfo &CLI,

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) {
       case Intrinsic::frameaddress:
         NumFastIselFailFrameaddress++; return;
       case Intrinsic::sqrt:
           NumFastIselFailSqrt++; return;
       case Intrinsic::experimental_stackmap:
         NumFastIselFailStackMap++; return;
       case Intrinsic::experimental_patchpoint_void: // fall-through
       case Intrinsic::experimental_patchpoint_i64:
+      case Intrinsic::experimental_patchpoint_double:
         NumFastIselFailPatchPoint++; return;
       }
     }
     NumFastIselFailCall++;
     return;
   }
   case Instruction::Shl:            NumFastIselFailShl++; return;
   case Instruction::LShr:           NumFastIselFailLShr++; return;

lib/IR/Verifier.cpp

if (Function *F = dyn_cast<Function>(I.getOperand(i))) {
       // Check to make sure that the "address of" an intrinsic function is never
       // taken.
       Assert1(!F->isIntrinsic() || i == (isa<CallInst>(I) ? e-1 :
                                          isa<InvokeInst>(I) ? e-3 : 0),
               "Cannot take the address of an intrinsic!", &I);
       Assert1(!F->isIntrinsic() || isa<CallInst>(I) ||
               F->getIntrinsicID() == Intrinsic::donothing ||
               F->getIntrinsicID() == Intrinsic::experimental_patchpoint_void ||
-              F->getIntrinsicID() == Intrinsic::experimental_patchpoint_i64,
+              F->getIntrinsicID() == Intrinsic::experimental_patchpoint_i64 ||
+              F->getIntrinsicID() == Intrinsic::experimental_patchpoint_double,
               "Cannot invoke an intrinsinc other than"
               " donothing or patchpoint", &I);
       Assert1(F->getParent() == M, "Referencing function in another module!",
               &I);
     } else if (BasicBlock *OpBB = dyn_cast<BasicBlock>(I.getOperand(i))) {
       Assert1(OpBB->getParent() == BB->getParent(),
               "Referring to a basic block in another function!", &I);
     } else if (Argument *OpArg = dyn_cast<Argument>(I.getOperand(i))) {

lib/Target/AArch64/AArch64TargetTransformInfo.cpp

case Intrinsic::umul_with_overflow:
     }
     break;
   case Intrinsic::experimental_stackmap:
     if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
       return TCC_Free;
     break;
   case Intrinsic::experimental_patchpoint_void:
   case Intrinsic::experimental_patchpoint_i64:
+  case Intrinsic::experimental_patchpoint_double:
     if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
       return TCC_Free;
     break;
   }
   return AArch64TTI::getIntImmCost(Imm, Ty);
 }
 
 AArch64TTI::PopcntSupportKind

lib/Target/X86/X86TargetTransformInfo.cpp

if ((Idx == 1) && Imm.getBitWidth() <= 64 && isInt<32>(Imm.getSExtValue()))
       return TCC_Free;
     break;
   case Intrinsic::experimental_stackmap:
     if ((Idx < 2) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
       return TCC_Free;
     break;
   case Intrinsic::experimental_patchpoint_void:
   case Intrinsic::experimental_patchpoint_i64:
+  case Intrinsic::experimental_patchpoint_double:
     if ((Idx < 4) || (Imm.getBitWidth() <= 64 && isInt<64>(Imm.getSExtValue())))
       return TCC_Free;
     break;
   }
   return X86TTI::getIntImmCost(Imm, Ty);
 }

test/CodeGen/X86/anyregcc.ll

 ; RUN: llc < %s -mtriple=x86_64-apple-darwin                  -disable-fp-elim | FileCheck %s
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7     -disable-fp-elim | FileCheck --check-prefix=SSE %s
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -disable-fp-elim | FileCheck --check-prefix=AVX %s
 
 
 ; Stackmap Header: no constants - 6 callsites
 ; CHECK-LABEL:  .section __LLVM_STACKMAPS,__llvm_stackmaps
 ; CHECK-NEXT:   __LLVM_StackMaps:
 ; Header
 ; CHECK-NEXT:   .byte 1
 ; CHECK-NEXT:   .byte 0
 ; CHECK-NEXT:   .short 0
 ; Num Functions
-; CHECK-NEXT:   .long 8
+; CHECK-NEXT:   .long 9
 ; Num Constants
 ; CHECK-NEXT:   .long 0
 ; Num Callsites
-; CHECK-NEXT:   .long 8
+; CHECK-NEXT:   .long 9
 
 ; Functions and stack size
 ; CHECK-NEXT:   .quad _test
 ; CHECK-NEXT:   .quad 8
 ; CHECK-NEXT:   .quad _property_access1
 ; CHECK-NEXT:   .quad 8
 ; CHECK-NEXT:   .quad _property_access2
 ; CHECK-NEXT:   .quad 24
 ; CHECK-NEXT:   .quad _property_access3
 ; CHECK-NEXT:   .quad 24
+; CHECK-NEXT:   .quad _property_access_double
+; CHECK-NEXT:   .quad 8
 ; CHECK-NEXT:   .quad _anyreg_test1
 ; CHECK-NEXT:   .quad 56
 ; CHECK-NEXT:   .quad _anyreg_test2
 ; CHECK-NEXT:   .quad 56
 ; CHECK-NEXT:   .quad _patchpoint_spilldef
 ; CHECK-NEXT:   .quad 56
 ; CHECK-NEXT:   .quad _patchpoint_spillargs
 ; CHECK-NEXT:   .quad 88

 define i64 @property_access3() nounwind ssp uwtable {
 entry:
   %obj = alloca i64, align 8
   %f = inttoptr i64 12297829382473034410 to i8*
   %ret = call anyregcc i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 3, i32 15, i8* %f, i32 0, i64* %obj)
   ret i64 %ret
 }
 
+; property access double
+; CHECK-LABEL:  .long   L{{.*}}_property_access_double
+; CHECK-NEXT:   .short  0
+; 2 locations
+; CHECK-NEXT:   .short  1
+; Loc 0: Register <-- this is the return register
+; CHECK-NEXT:   .byte 1
+; CHECK-NEXT:   .byte 16
+; CHECK-NEXT:   .short {{[0-9]+}}
+; CHECK-NEXT:   .long 0
+define double @property_access_double() nounwind ssp uwtable {
+entry:
+  %f = inttoptr i64 12297829382473034410 to i8*
+  %ret = call anyregcc double (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.double(i64 1, i32 15, i8* %f, i32 0)
+  ret double %ret
+}
+
 ; anyreg_test1
 ; CHECK-LABEL:  .long   L{{.*}}-_anyreg_test1
 ; CHECK-NEXT:   .short  0
 ; 14 locations
 ; CHECK-NEXT:   .short  14
 ; Loc 0: Register <-- this is the return register
 ; CHECK-NEXT:   .byte 1
 ; CHECK-NEXT:   .byte 8
;AVX-NOT: vmovups %ymm
   %a15 = call <2 x double> asm sideeffect "", "={xmm15}"() nounwind
   call anyregcc void @foo()
   call void asm sideeffect "", "{xmm0},{xmm1},{xmm2},{xmm3},{xmm4},{xmm5},{xmm6},{xmm7},{xmm8},{xmm9},{xmm10},{xmm11},{xmm12},{xmm13},{xmm14},{xmm15}"(<2 x double> %a0, <2 x double> %a1, <2 x double> %a2, <2 x double> %a3, <2 x double> %a4, <2 x double> %a5, <2 x double> %a6, <2 x double> %a7, <2 x double> %a8, <2 x double> %a9, <2 x double> %a10, <2 x double> %a11, <2 x double> %a12, <2 x double> %a13, <2 x double> %a14, <2 x double> %a15)
   ret void
 }
 
 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare double @llvm.experimental.patchpoint.double(i64, i32, i8*, i32, ...)

test/CodeGen/X86/patchpoint.ll

 ; CHECK:      ret
   %resolveCall2 = inttoptr i64 -559038736 to i8*
   %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %resolveCall2, i32 4, i64 %p1, i64 %p2, i64 %p3, i64 %p4)
   %resolveCall3 = inttoptr i64 -559038737 to i8*
   tail call void (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.void(i64 3, i32 15, i8* %resolveCall3, i32 2, i64 %p1, i64 %result)
   ret i64 %result
 }
 
+define double @double_patchpoint(double %p1, double %p2, double %p3, double %p4) {
+entry:
+; CHECK-LABEL: double_patchpoint:
+; CHECK:      movabsq $-559038736, %r11
+; CHECK-NEXT: callq *%r11
+; CHECK-NEXT: xchgw %ax, %ax
+; CHECK:      movsd %xmm0, [[SPILL:[^ ]+]]
+; CHECK:      callq *%r11
+; CHECK-NEXT: xchgw %ax, %ax
+; CHECK:      movsd [[SPILL]], %xmm0
+; CHECK:      ret
+  %resolveCall2 = inttoptr i64 -559038736 to i8*
+  %result = tail call double (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.double(i64 2, i32 15, i8* %resolveCall2, i32 4, double %p1, double %p2, double %p3, double %p4)
+  %result2 = tail call double (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.double(i64 2, i32 15, i8* %resolveCall2, i32 4, double %p1, double %p2, double %p3, double %p4)
+  ret double %result
+}
+
 ; Caller frame metadata with stackmaps. This should not be optimized
 ; as a leaf function.
 ;
 ; CHECK-LABEL: caller_meta_leaf
 ; CHECK: subq $32, %rsp
 ; CHECK: Ltmp
 ; CHECK: addq $32, %rsp
 ; CHECK: ret
; CHECK-NEXT: callq *%r11
   %resolveCall2 = inttoptr i64 6153737369414576827 to i8*
   %result = tail call i64 (i64, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i64 2, i32 15, i8* %resolveCall2, i32 0)
   ret i64 %result
 }
 
 declare void @llvm.experimental.stackmap(i64, i32, ...)
 declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...)
 declare i64 @llvm.experimental.patchpoint.i64(i64, i32, i8*, i32, ...)
+declare double @llvm.experimental.patchpoint.double(i64, i32, i8*, i32, ...)