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Differential D54331

AMDGPU : median3 matching incomplete or not working
ClosedPublic

Authored by aakanksha555 on Nov 9 2018, 9:49 AM.

Details

Reviewers
b-sumner
arsenm
Commits
rGa992c694c6b8: AMDGPU: Adding more median3 patterns
rL346704: AMDGPU: Adding more median3 patterns
Summary

Added the patterns for median3 matching.

Diff Detail

Event Timeline

aakanksha555 created this revision.Nov 9 2018, 9:49 AM
arsenm added inline comments.Nov 9 2018, 11:04 AM
lib/Target/AMDGPU/SIInstructions.td
582–583

Extra whitespace change

test/CodeGen/AMDGPU/umed3.ll
368

The signed version should go in smed3.ll

This could also use the helper functions like the rest of the tests. Should also have the various permutations

369

Run instnamer on this

aakanksha555 updated this revision to Diff 173415.Nov 9 2018, 12:32 PM
aakanksha555 marked 2 inline comments as done.

Added 16 test cases with the permutations of min(max(a, b), max(min(a, b), c))

aakanksha555 updated this revision to Diff 173416.Nov 9 2018, 12:35 PM

Removed a redundant test case.

arsenm accepted this revision.Nov 12 2018, 8:15 AM

LGTM

lib/Target/AMDGPU/SIInstructions.td
583

Extra whitespace change

This revision is now accepted and ready to land.Nov 12 2018, 8:15 AM
arsenm added a comment.Nov 12 2018, 9:07 AM

Also change the message before committing to be more descriptive. It sounds like something is broken as is

Closed by commit rL346704: AMDGPU: Adding more median3 patterns (authored by aakanksha555). · Explain WhyNov 12 2018, 1:06 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
24 lines
7 lines
test/
CodeGen/
AMDGPU/
205 lines
206 lines

Diff 173416

lib/Target/AMDGPU/AMDGPUInstructions.td

Show First 20 Lines • Show All 790 Lines • ▼ Show 20 Lines
} }
// rotr pattern // rotr pattern
class ROTRPattern <Instruction BIT_ALIGN> : AMDGPUPat < class ROTRPattern <Instruction BIT_ALIGN> : AMDGPUPat <
(rotr i32:$src0, i32:$src1), (rotr i32:$src0, i32:$src1),
(BIT_ALIGN $src0, $src0, $src1) (BIT_ALIGN $src0, $src0, $src1)
>; >;
// This matches 16 permutations of multiclass IntMed3Pat<Instruction med3Inst,
// max(min(x, y), min(max(x, y), z)) SDPatternOperator min,
class IntMed3Pat<Instruction med3Inst,
SDPatternOperator max, SDPatternOperator max,
SDPatternOperator max_oneuse,
SDPatternOperator min_oneuse, SDPatternOperator min_oneuse,
ValueType vt = i32> : AMDGPUPat< SDPatternOperator max_oneuse,
ValueType vt = i32> {
// This matches 16 permutations of
// min(max(a, b), max(min(a, b), c))
def : AMDGPUPat <
(min (max_oneuse vt:$src0, vt:$src1),
(max_oneuse (min_oneuse vt:$src0, vt:$src1), vt:$src2)),
(med3Inst vt:$src0, vt:$src1, vt:$src2)
>;
// This matches 16 permutations of
// max(min(x, y), min(max(x, y), z))
def : AMDGPUPat <
(max (min_oneuse vt:$src0, vt:$src1), (max (min_oneuse vt:$src0, vt:$src1),
(min_oneuse (max_oneuse vt:$src0, vt:$src1), vt:$src2)), (min_oneuse (max_oneuse vt:$src0, vt:$src1), vt:$src2)),
(med3Inst $src0, $src1, $src2) (med3Inst $src0, $src1, $src2)
>; >;
}
// Special conversion patterns // Special conversion patterns
def cvt_rpi_i32_f32 : PatFrag < def cvt_rpi_i32_f32 : PatFrag <
(ops node:$src), (ops node:$src),
(fp_to_sint (ffloor (fadd $src, FP_HALF))), (fp_to_sint (ffloor (fadd $src, FP_HALF))),
[{ (void) N; return TM.Options.NoNaNsFPMath; }] [{ (void) N; return TM.Options.NoNaNsFPMath; }]
>; >;
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lib/Target/AMDGPU/SIInstructions.td

Show First 20 Lines • Show All 573 Lines • ▼ Show 20 Linesdef : Pat <
(AMDGPUkill i32:$src), (AMDGPUkill i32:$src),
(SI_KILL_F32_COND_IMM_PSEUDO $src, 0, 3) // 3 means SETOGE (SI_KILL_F32_COND_IMM_PSEUDO $src, 0, 3) // 3 means SETOGE
>; >;
def : Pat < def : Pat <
(int_amdgcn_kill (i1 (setcc f32:$src, InlineFPImm<f32>:$imm, cond:$cond))), (int_amdgcn_kill (i1 (setcc f32:$src, InlineFPImm<f32>:$imm, cond:$cond))),
(SI_KILL_F32_COND_IMM_PSEUDO $src, (bitcast_fpimm_to_i32 $imm), (cond_as_i32imm $cond)) (SI_KILL_F32_COND_IMM_PSEUDO $src, (bitcast_fpimm_to_i32 $imm), (cond_as_i32imm $cond))
>; >;
// TODO: we could add more variants for other types of conditionals // TODO: we could add more variants for other types of conditionals
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Extra whitespace change

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Extra whitespace change

arsenm: Extra whitespace change
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// VOP1 Patterns // VOP1 Patterns
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let SubtargetPredicate = isGCN, OtherPredicates = [UnsafeFPMath] in { let SubtargetPredicate = isGCN, OtherPredicates = [UnsafeFPMath] in {
//def : RcpPat<V_RCP_F64_e32, f64>; //def : RcpPat<V_RCP_F64_e32, f64>;
▲ Show 20 Lines • Show All 1,025 Lines • ▼ Show 20 Lines
let SubtargetPredicate = isGCN in { let SubtargetPredicate = isGCN in {
defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>; defm : BFMPatterns <i32, S_BFM_B32, S_MOV_B32>;
// FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>; // FIXME: defm : BFMPatterns <i64, S_BFM_B64, S_MOV_B64>;
defm : BFEPattern <V_BFE_U32, V_BFE_I32, S_MOV_B32>; defm : BFEPattern <V_BFE_U32, V_BFE_I32, S_MOV_B32>;
defm : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64, SReg_64>; defm : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e64, SReg_64>;
def : IntMed3Pat<V_MED3_I32, smax, smax_oneuse, smin_oneuse>; defm : IntMed3Pat<V_MED3_I32, smin, smax, smin_oneuse, smax_oneuse>;
def : IntMed3Pat<V_MED3_U32, umax, umax_oneuse, umin_oneuse>; defm : IntMed3Pat<V_MED3_U32, umin, umax, umin_oneuse, umax_oneuse>;
} }
// This matches 16 permutations of // This matches 16 permutations of
// max(min(x, y), min(max(x, y), z)) // max(min(x, y), min(max(x, y), z))
class FPMed3Pat<ValueType vt, class FPMed3Pat<ValueType vt,
//SDPatternOperator max, SDPatternOperator min, //SDPatternOperator max, SDPatternOperator min,
Instruction med3Inst> : GCNPat< Instruction med3Inst> : GCNPat<
Show All 35 Lines

test/CodeGen/AMDGPU/smed3.ll

Show First 20 Lines • Show All 358 Lines • ▼ Show 20 Linesbb:
%tmp0 = call i32 @smin(i32 %y, i32 %x) %tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %y, i32 %x) %tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smin(i32 %z, i32 %tmp1) %tmp2 = call i32 @smin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0) %tmp3 = call i32 @smax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg store i32 %tmp3, i32 addrspace(1)* %arg
ret void ret void
} }
; 16 combinations
; 16: min(max(x, y), max(min(x, y), z))
; 17: min(max(x, y), max(min(y, x), z))
; 18: min(max(x, y), max(z, min(x, y)))
; 19: min(max(x, y), max(z, min(y, x)))
; 20: min(max(y, x), max(min(x, y), z))
; 21: min(max(y, x), max(min(y, x), z))
; 22: min(max(y, x), max(z, min(x, y)))
; 23: min(max(y, x), max(z, min(y, x)))
;
; + commute outermost min
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_16:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i32_pat_16(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smax(i32 %tmp0, i32 %z)
%tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_17:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i32_pat_17(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smax(i32 %tmp0, i32 %z)
%tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_18:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i32_pat_18(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smax(i32 %z, i32 %tmp0)
%tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_19:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i32_pat_19(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smax(i32 %z, i32 %tmp0)
%tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_20:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i32_pat_20(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smax(i32 %tmp0, i32 %z)
%tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_21:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i32_pat_21(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smax(i32 %tmp0, i32 %z)
%tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_22:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i32_pat_22(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smax(i32 %z, i32 %tmp0)
%tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_23:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i32_pat_23(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smax(i32 %z, i32 %tmp0)
%tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_24:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i32_pat_24(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smax(i32 %tmp0, i32 %z)
%tmp3 = call i32 @smin(i32 %tmp2, i32 %tmp1)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_25:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i32_pat_25(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smax(i32 %tmp0, i32 %z)
%tmp3 = call i32 @smin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_26:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i32_pat_26(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smax(i32 %z, i32 %tmp0)
%tmp3 = call i32 @smin(i32 %tmp2, i32 %tmp1)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_27:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i32_pat_27(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %x, i32 %y)
%tmp2 = call i32 @smax(i32 %z, i32 %tmp0)
%tmp3 = call i32 @smin(i32 %tmp2, i32 %tmp1)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_28:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i32_pat_28(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smax(i32 %tmp0, i32 %z)
%tmp3 = call i32 @smin(i32 %tmp2, i32 %tmp1)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_29:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i32_pat_29(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smax(i32 %tmp0, i32 %z)
%tmp3 = call i32 @smin(i32 %tmp2, i32 %tmp1)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_30:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i32_pat_30(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %x, i32 %y)
%tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smax(i32 %z, i32 %tmp0)
%tmp3 = call i32 @smin(i32 %tmp2, i32 %tmp1)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_smed3_i32_pat_31:
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i32_pat_31(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @smin(i32 %y, i32 %x)
%tmp1 = call i32 @smax(i32 %y, i32 %x)
%tmp2 = call i32 @smax(i32 %z, i32 %tmp0)
%tmp3 = call i32 @smin(i32 %tmp2, i32 %tmp1)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; FIXME: Should keep scalar or not promote ; FIXME: Should keep scalar or not promote
; GCN-LABEL: {{^}}s_test_smed3_i16_pat_0: ; GCN-LABEL: {{^}}s_test_smed3_i16_pat_0:
; GCN: s_sext_i32_i16 ; GCN: s_sext_i32_i16
; GCN: s_sext_i32_i16 ; GCN: s_sext_i32_i16
; GCN: s_sext_i32_i16 ; GCN: s_sext_i32_i16
; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_med3_i32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_smed3_i16_pat_0(i16 addrspace(1)* %arg, [8 x i32], i16 %x, [8 x i32], i16 %y, [8 x i32], i16 %z) #1 { define amdgpu_kernel void @s_test_smed3_i16_pat_0(i16 addrspace(1)* %arg, [8 x i32], i16 %x, [8 x i32], i16 %y, [8 x i32], i16 %z) #1 {
bb: bb:
▲ Show 20 Lines • Show All 107 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/umed3.ll

Show First 20 Lines • Show All 357 Lines • ▼ Show 20 Linesbb:
%tmp0 = call i32 @umin(i32 %y, i32 %x) %tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %y, i32 %x) %tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umin(i32 %z, i32 %tmp1) %tmp2 = call i32 @umin(i32 %z, i32 %tmp1)
%tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0) %tmp3 = call i32 @umax(i32 %tmp2, i32 %tmp0)
store i32 %tmp3, i32 addrspace(1)* %arg store i32 %tmp3, i32 addrspace(1)* %arg
ret void ret void
} }
; 16 combinations
; 16: min(max(x, y), max(min(x, y), z))
arsenmUnsubmitted
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The signed version should go in smed3.ll

This could also use the helper functions like the rest of the tests. Should also have the various permutations

arsenm: The signed version should go in smed3.ll This could also use the helper functions like the…
; 17: min(max(x, y), max(min(y, x), z))
arsenmUnsubmitted
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Run instnamer on this

arsenm: Run instnamer on this
; 18: min(max(x, y), max(z, min(x, y)))
; 19: min(max(x, y), max(z, min(y, x)))
; 20: min(max(y, x), max(min(x, y), z))
; 21: min(max(y, x), max(min(y, x), z))
; 22: min(max(y, x), max(z, min(x, y)))
; 23: min(max(y, x), max(z, min(y, x)))
;
; + commute outermost min
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_16:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i32_pat_16(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umax(i32 %tmp0, i32 %z)
%tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_17:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i32_pat_17(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umax(i32 %tmp0, i32 %z)
%tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_18:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i32_pat_18(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umax(i32 %z, i32 %tmp0)
%tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_19:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i32_pat_19(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umax(i32 %z, i32 %tmp0)
%tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_20:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i32_pat_20(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umax(i32 %tmp0, i32 %z)
%tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_21:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i32_pat_21(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umax(i32 %tmp0, i32 %z)
%tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_22:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i32_pat_22(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umax(i32 %z, i32 %tmp0)
%tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_23:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i32_pat_23(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umax(i32 %z, i32 %tmp0)
%tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_24:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i32_pat_24(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umax(i32 %tmp0, i32 %z)
%tmp3 = call i32 @umin(i32 %tmp2, i32 %tmp1)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_25:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i32_pat_25(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umax(i32 %tmp0, i32 %z)
%tmp3 = call i32 @umin(i32 %tmp1, i32 %tmp2)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_26:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i32_pat_26(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umax(i32 %z, i32 %tmp0)
%tmp3 = call i32 @umin(i32 %tmp2, i32 %tmp1)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_27:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i32_pat_27(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %x, i32 %y)
%tmp2 = call i32 @umax(i32 %z, i32 %tmp0)
%tmp3 = call i32 @umin(i32 %tmp2, i32 %tmp1)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_28:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i32_pat_28(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umax(i32 %tmp0, i32 %z)
%tmp3 = call i32 @umin(i32 %tmp2, i32 %tmp1)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_29:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i32_pat_29(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umax(i32 %tmp0, i32 %z)
%tmp3 = call i32 @umin(i32 %tmp2, i32 %tmp1)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_30:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i32_pat_30(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %x, i32 %y)
%tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umax(i32 %z, i32 %tmp0)
%tmp3 = call i32 @umin(i32 %tmp2, i32 %tmp1)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i32_pat_31:
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i32_pat_31(i32 addrspace(1)* %arg, i32 %x, i32 %y, i32 %z) #1 {
bb:
%tmp0 = call i32 @umin(i32 %y, i32 %x)
%tmp1 = call i32 @umax(i32 %y, i32 %x)
%tmp2 = call i32 @umax(i32 %z, i32 %tmp0)
%tmp3 = call i32 @umin(i32 %tmp2, i32 %tmp1)
store i32 %tmp3, i32 addrspace(1)* %arg
ret void
}
; GCN-LABEL: {{^}}s_test_umed3_i16_pat_0: ; GCN-LABEL: {{^}}s_test_umed3_i16_pat_0:
; GCN: s_and_b32 ; GCN: s_and_b32
; GCN: s_and_b32 ; GCN: s_and_b32
; GCN: s_and_b32 ; GCN: s_and_b32
; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_med3_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @s_test_umed3_i16_pat_0(i16 addrspace(1)* %arg, [8 x i32], i16 %x, [8 x i32], i16 %y, [8 x i32], i16 %z) #1 { define amdgpu_kernel void @s_test_umed3_i16_pat_0(i16 addrspace(1)* %arg, [8 x i32], i16 %x, [8 x i32], i16 %y, [8 x i32], i16 %z) #1 {
bb: bb:
%tmp0 = call i16 @umin16(i16 %x, i16 %y) %tmp0 = call i16 @umin16(i16 %x, i16 %y)
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