[X86][SLH] Regroup the instructions in isDataInvariantLoad a little. NFC

[craig.topper]

Summary

-Move BSF/BSR to the same group as TZCNT/LZCNT/POPCNT.
-Split some of the bit manipulation instructions away from TZCNT/LZCNT/POPCNT. These are things like 'x & (x - 1)' which are composed of a few simple arithmetic operations. These aren't nearly as complicated/surprising as counting bits.
-Move BEXTR/BZHI into their own group. They aren't like a simple arithmethic op or the bit manipulation instructions. They're more like a shift+and.

[chandlerc]

LGTM!

llvm/trunk/lib/Target/X86/X86SpeculativeLoadHardening.cpp

 ///
 /// FIXME: This should become part of our instruction tables.
 static bool isDataInvariantLoad(MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default:
     // By default, assume that the load will immediately leak.
     return false;
 
-    // On x86 it is believed that imul is constant time w.r.t. the loaded data.
-    // However, they set flags and are perhaps the most surprisingly constant
-    // time operations so we call them out here separately.
   case X86::IMUL16rm:
   case X86::IMUL16rmi8:
   case X86::IMUL16rmi:
   case X86::IMUL32rm:
   case X86::IMUL32rmi8:
   case X86::IMUL32rmi:
   case X86::IMUL64rm:
   case X86::IMUL64rmi32:
   case X86::IMUL64rmi8:
 
-    // Bitfield and bit scanning instructions that are somewhat surprisingly
-    // constant time as they scan across bits and do other fairly complex
-    // operations like popcnt, but are believed to be constant time on x86.
-    // However, these set flags.
+  // Bit scanning and counting instructions that are somewhat surprisingly
+  case X86::BSF16rm:
+  case X86::BSF32rm:
+  case X86::BSF64rm:
+  case X86::BSR16rm:
+  case X86::BSR32rm:
+  case X86::BSR64rm:
+  case X86::LZCNT16rm:
+  case X86::LZCNT32rm:
+  case X86::LZCNT64rm:
+  case X86::POPCNT16rm:
+  case X86::POPCNT32rm:
+  case X86::POPCNT64rm:
+  case X86::TZCNT16rm:
+  case X86::TZCNT32rm:
+  case X86::TZCNT64rm:
+
+  // Bit manipulation instructions are effectively combinations of basic
+  // arithmetic ops, and should still execute in constant time. These also
+  // set flags.
   case X86::BLCFILL32rm:
   case X86::BLCFILL64rm:
   case X86::BLCI32rm:
   case X86::BLCI64rm:
   case X86::BLCIC32rm:
   case X86::BLCIC64rm:
   case X86::BLCMSK32rm:
   case X86::BLCMSK64rm:
   case X86::BLCS32rm:
   case X86::BLCS64rm:
   case X86::BLSFILL32rm:
   case X86::BLSFILL64rm:
   case X86::BLSI32rm:
   case X86::BLSI64rm:
   case X86::BLSIC32rm:
   case X86::BLSIC64rm:
   case X86::BLSMSK32rm:
   case X86::BLSMSK64rm:
   case X86::BLSR32rm:
   case X86::BLSR64rm:
-  case X86::BZHI32rm:
-  case X86::BZHI64rm:
-  case X86::LZCNT16rm:
-  case X86::LZCNT32rm:
-  case X86::LZCNT64rm:
-  case X86::POPCNT16rm:
-  case X86::POPCNT32rm:
-  case X86::POPCNT64rm:
-  case X86::TZCNT16rm:
-  case X86::TZCNT32rm:
-  case X86::TZCNT64rm:
   case X86::TZMSK32rm:
   case X86::TZMSK64rm:
 
-    // Basic arithmetic is constant time on the input but does set flags.
+  // Bit extracting and clearing instructions should execute in constant time,
+  // and set flags.
+  case X86::BEXTR32rm:
+  case X86::BEXTR64rm:
+  case X86::BEXTRI32mi:
+  case X86::BEXTRI64mi:
+  case X86::BZHI32rm:
+  case X86::BZHI64rm:
+
   case X86::ADC8rm:
   case X86::ADC16rm:
   case X86::ADC32rm:
   case X86::ADC64rm:
   case X86::ADCX32rm:
   case X86::ADCX64rm:
   case X86::ADD8rm:
   case X86::ADD16rm:
   case X86::ADD32rm:
   case X86::ADD64rm:
   case X86::ADOX32rm:
   case X86::ADOX64rm:
   case X86::AND8rm:
   case X86::AND16rm:
   case X86::AND32rm:
   case X86::AND64rm:
   case X86::ANDN32rm:
   case X86::ANDN64rm:
-  case X86::BSF16rm:
-  case X86::BSF32rm:
-  case X86::BSF64rm:
-  case X86::BSR16rm:
-  case X86::BSR32rm:
-  case X86::BSR64rm:
   case X86::OR8rm:
   case X86::OR16rm:
   case X86::OR32rm:
   case X86::OR64rm:
   case X86::SBB8rm:
   case X86::SBB16rm:
   case X86::SBB32rm:
   case X86::SBB64rm:
   case X86::SUB8rm:
   case X86::SUB16rm:
   case X86::SUB32rm:
   case X86::SUB64rm:
   case X86::XOR8rm:
   case X86::XOR16rm:
   case X86::XOR32rm:
   case X86::XOR64rm:
-  case X86::BEXTR32rm:
-  case X86::BEXTR64rm:
-  case X86::BEXTRI32mi:
-  case X86::BEXTRI64mi:
     // Check whether the EFLAGS implicit-def is dead. We assume that this will
     // always find the implicit-def because this code should only be reached
     // for instructions that do in fact implicitly def this.
     if (!MI.findRegisterDefOperand(X86::EFLAGS)->isDead()) {
       // If we would clobber EFLAGS that are used, just bail for now.
       LLVM_DEBUG(dbgs() << "    Unable to harden post-load due to EFLAGS: ";
                  MI.dump(); dbgs() << "\n");
       return false;
     }
 
     // Otherwise, fallthrough to handle these the same as instructions that
     // don't set EFLAGS.
     LLVM_FALLTHROUGH;
 
-    // Integer multiply w/o affecting flags is still believed to be constant
-    // time on x86. Called out separately as this is among the most surprising
-    // instructions to exhibit that behavior.
   case X86::MULX32rm:
   case X86::MULX64rm:
 
-    // Arithmetic instructions that are both constant time and don't set flags.
   case X86::PDEP32rm:
   case X86::PDEP64rm:
   case X86::PEXT32rm:
   case X86::PEXT64rm:
   case X86::RORX32mi:
   case X86::RORX64mi:
   case X86::SARX32rm:
   case X86::SARX64rm:
   case X86::SHLX32rm:
   case X86::SHLX64rm:
   case X86::SHRX32rm:
   case X86::SHRX64rm:
 
-    // Conversions are believed to be constant time and don't set flags.
-    // FIXME: Add AVX versions.
   case X86::CVTSD2SI64rm_Int:
   case X86::CVTSD2SIrm_Int:
   case X86::CVTSS2SI64rm_Int:
   case X86::CVTSS2SIrm_Int:
   case X86::CVTTSD2SI64rm:
   case X86::CVTTSD2SI64rm_Int:
   case X86::CVTTSD2SIrm:
   case X86::CVTTSD2SIrm_Int:
   case X86::CVTTSS2SI64rm:
   case X86::CVTTSS2SI64rm_Int:
   case X86::CVTTSS2SIrm:
   case X86::CVTTSS2SIrm_Int:
 
-    // Loads to register don't set flags.
   case X86::MOV8rm:
   case X86::MOV8rm_NOREX:
   case X86::MOV16rm:
   case X86::MOV32rm:
   case X86::MOV64rm:
   case X86::MOVSX16rm8:
   case X86::MOVSX32rm16:
   case X86::MOVSX32rm8: