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Differential D46436

[x86] Introduce the enclv instruction
ClosedPublic

Authored by GBuella on May 4 2018, 8:51 AM.

Details

Reviewers
craig.topper
zvi
Commits
rG4a02bf945e8b: [x86] Introduce the enclv instruction
rL331742: [x86] Introduce the enclv instruction
Summary

and use the -msgx flag as a requirement
for the SGX instructions.

Diff Detail

Repository
rL LLVM

Event Timeline

GBuella created this revision.May 4 2018, 8:51 AM
Herald added a subscriber: llvm-commits. · View Herald TranscriptMay 4 2018, 8:51 AM
craig.topper added a comment.May 4 2018, 11:06 AM

Disassembler test?

GBuella updated this revision to Diff 145429.May 7 2018, 12:07 AM
craig.topper accepted this revision.May 7 2018, 10:49 AM

LGTM

This revision is now accepted and ready to land.May 7 2018, 10:49 AM
Closed by commit rL331742: [x86] Introduce the enclv instruction (authored by GBuella). · Explain WhyMay 8 2018, 12:14 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
X86/
1 line
6 lines
1 line
test/
MC/
Disassembler/
X86/
9 lines
9 lines
X86/
10 lines
10 lines
9 lines
12 lines
12 lines

Diff 145637

llvm/trunk/lib/Target/X86/X86InstrInfo.td

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def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
def NoBMI2 : Predicate<"!Subtarget->hasBMI2()">; def NoBMI2 : Predicate<"!Subtarget->hasBMI2()">;
def HasVBMI : Predicate<"Subtarget->hasVBMI()">; def HasVBMI : Predicate<"Subtarget->hasVBMI()">;
def HasVBMI2 : Predicate<"Subtarget->hasVBMI2()">; def HasVBMI2 : Predicate<"Subtarget->hasVBMI2()">;
def HasIFMA : Predicate<"Subtarget->hasIFMA()">; def HasIFMA : Predicate<"Subtarget->hasIFMA()">;
def HasRTM : Predicate<"Subtarget->hasRTM()">; def HasRTM : Predicate<"Subtarget->hasRTM()">;
def HasADX : Predicate<"Subtarget->hasADX()">; def HasADX : Predicate<"Subtarget->hasADX()">;
def HasSHA : Predicate<"Subtarget->hasSHA()">; def HasSHA : Predicate<"Subtarget->hasSHA()">;
def HasSGX : Predicate<"Subtarget->hasSGX()">;
def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">; def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">;
def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">; def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">;
def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">; def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">;
def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">; def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">; def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">;
def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">; def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">;
def HasMWAITX : Predicate<"Subtarget->hasMWAITX()">; def HasMWAITX : Predicate<"Subtarget->hasMWAITX()">;
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llvm/trunk/lib/Target/X86/X86InstrSGX.td

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// This file describes the instructions that make up the Intel SGX instruction // This file describes the instructions that make up the Intel SGX instruction
// set. // set.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SGX instructions // SGX instructions
let SchedRW = [WriteSystem] in { let SchedRW = [WriteSystem], Predicates = [HasSGX] in {
// ENCLS - Execute an Enclave System Function of Specified Leaf Number // ENCLS - Execute an Enclave System Function of Specified Leaf Number
def ENCLS : I<0x01, MRM_CF, (outs), (ins), def ENCLS : I<0x01, MRM_CF, (outs), (ins),
"encls", []>, TB; "encls", []>, TB;
// ENCLU - Execute an Enclave User Function of Specified Leaf Number // ENCLU - Execute an Enclave User Function of Specified Leaf Number
def ENCLU : I<0x01, MRM_D7, (outs), (ins), def ENCLU : I<0x01, MRM_D7, (outs), (ins),
"enclu", []>, TB; "enclu", []>, TB;
// ENCLV - Execute an Enclave VMM Function of Specified Leaf Number
def ENCLV : I<0x01, MRM_C0, (outs), (ins),
"enclv", []>, TB;
} // SchedRW } // SchedRW

llvm/trunk/lib/Target/X86/X86Subtarget.h

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bool hasSHSTK() const { return HasSHSTK; } bool hasSHSTK() const { return HasSHSTK; }
bool hasIBT() const { return HasIBT; } bool hasIBT() const { return HasIBT; }
bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; } bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
bool hasCLWB() const { return HasCLWB; } bool hasCLWB() const { return HasCLWB; }
bool hasWBNOINVD() const { return HasWBNOINVD; } bool hasWBNOINVD() const { return HasWBNOINVD; }
bool hasRDPID() const { return HasRDPID; } bool hasRDPID() const { return HasRDPID; }
bool hasWAITPKG() const { return HasWAITPKG; } bool hasWAITPKG() const { return HasWAITPKG; }
bool hasPCONFIG() const { return HasPCONFIG; } bool hasPCONFIG() const { return HasPCONFIG; }
bool hasSGX() const { return HasSGX; }
bool useRetpoline() const { return UseRetpoline; } bool useRetpoline() const { return UseRetpoline; }
bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; } bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
unsigned getPreferVectorWidth() const { return PreferVectorWidth; } unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; } unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
// Helper functions to determine when we should allow widening to 512-bit // Helper functions to determine when we should allow widening to 512-bit
// during codegen. // during codegen.
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llvm/trunk/test/MC/Disassembler/X86/x86-32.txt

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#CHECK: movdir64b (%esi), %eax #CHECK: movdir64b (%esi), %eax
0x66 0x0f 0x38 0xf8 0x06 0x66 0x0f 0x38 0xf8 0x06
#CHECK: movdir64b (%si), %ax #CHECK: movdir64b (%si), %ax
0x67 0x66 0x0f 0x38 0xf8 0x04 0x67 0x66 0x0f 0x38 0xf8 0x04
#CHECK: pconfig #CHECK: pconfig
0x0f 0x01 0xc5 0x0f 0x01 0xc5
#CHECK: encls
0x0f 0x01 0xcf
#CHECK: enclu
0x0f 0x01 0xd7
#CHECK: enclv
0x0f 0x01 0xc0

llvm/trunk/test/MC/Disassembler/X86/x86-64.txt

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#CHECK: movdir64b 485498096, %rax #CHECK: movdir64b 485498096, %rax
0x66 0x0f 0x38 0xf8 0x04 0x25 0xf0 0x1c 0xf0 0x1c 0x66 0x0f 0x38 0xf8 0x04 0x25 0xf0 0x1c 0xf0 0x1c
#CHECK: movdir64b 485498096, %eax #CHECK: movdir64b 485498096, %eax
0x67 0x66 0x0f 0x38 0xf8 0x04 0x25 0xf0 0x1c 0xf0 0x1c 0x67 0x66 0x0f 0x38 0xf8 0x04 0x25 0xf0 0x1c 0xf0 0x1c
#CHECK: pconfig #CHECK: pconfig
0x0f 0x01 0xc5 0x0f 0x01 0xc5
#CHECK: encls
0x0f 0x01 0xcf
#CHECK: enclu
0x0f 0x01 0xd7
#CHECK: enclv
0x0f 0x01 0xc0

llvm/trunk/test/MC/X86/SGX-32.s

// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
// CHECK: encls
// CHECK: encoding: [0x0f,0x01,0xcf]
encls
// CHECK: enclu
// CHECK: encoding: [0x0f,0x01,0xd7]
enclu

llvm/trunk/test/MC/X86/SGX-64.s

// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
// CHECK: encls
// CHECK: encoding: [0x0f,0x01,0xcf]
encls
// CHECK: enclu
// CHECK: encoding: [0x0f,0x01,0xd7]
enclu

llvm/trunk/test/MC/X86/sgx-encoding.s

// RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
// CHECK: encls
// CHECK: encoding: [0x0f,0x01,0xcf]
encls
// CHECK: enclu
// CHECK: encoding: [0x0f,0x01,0xd7]
enclu

llvm/trunk/test/MC/X86/x86-32-coverage.s

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
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// CHECK: movdir64b (%si), %ax // CHECK: movdir64b (%si), %ax
// CHECK: # encoding: [0x67,0x66,0x0f,0x38,0xf8,0x04] // CHECK: # encoding: [0x67,0x66,0x0f,0x38,0xf8,0x04]
movdir64b (%si), %ax movdir64b (%si), %ax
// CHECK: pconfig // CHECK: pconfig
// CHECK: # encoding: [0x0f,0x01,0xc5] // CHECK: # encoding: [0x0f,0x01,0xc5]
pconfig pconfig
// CHECK: encls
// CHECK: encoding: [0x0f,0x01,0xcf]
encls
// CHECK: enclu
// CHECK: encoding: [0x0f,0x01,0xd7]
enclu
// CHECK: enclv
// CHECK: encoding: [0x0f,0x01,0xc0]
enclv

llvm/trunk/test/MC/X86/x86-64.s

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// CHECK: movdir64b (%rdx), %r15 // CHECK: movdir64b (%rdx), %r15
// CHECK: # encoding: [0x66,0x44,0x0f,0x38,0xf8,0x3a] // CHECK: # encoding: [0x66,0x44,0x0f,0x38,0xf8,0x3a]
movdir64b (%rdx), %r15 movdir64b (%rdx), %r15
// CHECK: pconfig // CHECK: pconfig
// CHECK: # encoding: [0x0f,0x01,0xc5] // CHECK: # encoding: [0x0f,0x01,0xc5]
pconfig pconfig
// CHECK: encls
// CHECK: encoding: [0x0f,0x01,0xcf]
encls
// CHECK: enclu
// CHECK: encoding: [0x0f,0x01,0xd7]
enclu
// CHECK: enclv
// CHECK: encoding: [0x0f,0x01,0xc0]
enclv
// __asm __volatile( // __asm __volatile(
// "pushf \n\t" // "pushf \n\t"
// "popf \n\t" // "popf \n\t"
// "rep \n\t" // "rep \n\t"
// ".byte 0x0f, 0xa7, 0xd0" // ".byte 0x0f, 0xa7, 0xd0"
// ); // );
// CHECK: pushfq // CHECK: pushfq
// CHECK-NEXT: popfq // CHECK-NEXT: popfq
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llvm/trunk/test/MC/Disassembler/X86/x86-64.txt