[ARC] Add <.f> suffix for F32_GEN4_{DOP|SOP}

[yan_luo]

Summary

<.f>: writeback to status register flags

[petecoup]

Hi Yan,

Thanks for working on this!
Can you add some tests to the disassembler for variants that you added here?
Thanks!

[yan_luo]

Pete, I updated the revision, please review it again, thanks!

[petecoup]

Great, thanks!
Do you need me to commit this for you?

[yan_luo]

Yes, Pete. Please land it for me. Thanks!

[petecoup]

Committed in r329404.
Thanks!

lib/Target/ARC/ARCInstrInfo.td

 // Generic 3 operand binary instructions (i.e., add r0, r1, r2).
 multiclass ArcBinaryInst<bits<5> major, bits<6> mincode,
                        string opasm> {
   // 3 register variant.
   def _rrr : F32_DOP_RR<major, mincode, 0, (outs GPR32:$A),
                         (ins GPR32:$B, GPR32:$C),
                         !strconcat(opasm, "\t$A, $B, $C"),
                         []>;
+  def _f_rrr : F32_DOP_RR<major, mincode, 1, (outs GPR32:$A),
+                          (ins GPR32:$B, GPR32:$C),
+                          !strconcat(opasm, ".f\t$A, $B, $C"),
+                          []>
+  { let Defs = [STATUS32]; }
 
   // 2 register with unsigned 6-bit immediate variant.
   def _rru6 : F32_DOP_RU6<major, mincode, 0, (outs GPR32:$A),
                           (ins GPR32:$B, immU6:$U6),
                           !strconcat(opasm, "\t$A, $B, $U6"),
                           []>;
+  def _f_rru6 : F32_DOP_RU6<major, mincode, 1, (outs GPR32:$A),
+                            (ins GPR32:$B, immU6:$U6),
+                            !strconcat(opasm, ".f\t$A, $B, $U6"),
+                            []>
+  { let Defs = [STATUS32]; }
+
   // 2 register with 32-bit immediate variant.
   def _rrlimm : F32_DOP_RLIMM<major, mincode, 0,
                               (outs GPR32:$A),
                               (ins GPR32:$B, i32imm:$LImm),
                               !strconcat(opasm, "\t$A, $B, $LImm"),
                               []>;
+  def _f_rrlimm : F32_DOP_RLIMM<major, mincode, 1,
+                                (outs GPR32:$A),
+                                (ins GPR32:$B, i32imm:$LImm),
+                                !strconcat(opasm, ".f\t$A, $B, $LImm"),
+                                []>
+  { let Defs = [STATUS32]; }
+
   // 2 matched-register with signed 12-bit immediate variant (add r0, r0, -1).
   def _rrs12 : F32_DOP_RS12<major, mincode, 0,
                             (outs GPR32:$B),
                             (ins GPR32:$in, immS<12>:$S12),
                             !strconcat(opasm, "\t$B, $in, $S12"),
                             []>
   { let Constraints = "$B = $in"; }
+  def _f_rrs12 : F32_DOP_RS12<major, mincode, 1,
+                              (outs GPR32:$B),
+                              (ins GPR32:$in, immS<12>:$S12),
+                              !strconcat(opasm, ".f\t$B, $in, $S12"),
+                              []>
+  { let Constraints = "$B = $in"; let Defs = [STATUS32]; }
 }
 
 // Special multivariant GEN4 DOP format instruction that take 2 registers.
 // This is the class that is used for various comparison instructions.
 multiclass ArcSpecialDOPInst<bits<6> subop, string opasm, bit F> {
   def _rr : F32_DOP_RR<0b00100, subop, F, (outs), (ins GPR32:$B, GPR32:$C),
                !strconcat(opasm, "\t$B, $C"),
                []>;
 
   def _ru6 : F32_DOP_RU6<0b00100, subop, F, (outs), (ins GPR32:$B, i32imm:$U6),
                !strconcat(opasm, "\t$B, $U6"),
                []>;
 
   def _rlimm : F32_DOP_RLIMM<0b00100, subop, F, (outs),
                (ins GPR32:$B, i32imm:$LImm),
                !strconcat(opasm, "\t$B, $LImm"),
                []>;
 }
 
 // Generic 2-operand unary instructions.
 multiclass ArcUnaryInst<bits<5> major, bits<6> subop,
                         string opasm> {
   def _rr : F32_SOP_RR<major, subop, 0, (outs GPR32:$B), (ins GPR32:$C),
                        !strconcat(opasm, "\t$B, $C"), []>;
+
+  def _f_rr : F32_SOP_RR<major, subop, 1, (outs GPR32:$B), (ins GPR32:$C),
+                       !strconcat(opasm, ".f\t$B, $C"), []>
+  { let Defs = [STATUS32]; }
 }
 
 
 multiclass ArcBinaryGEN4Inst<bits<6> mincode, string opasm> :
   ArcBinaryInst<0b00100, mincode, opasm>;
 multiclass ArcBinaryEXT5Inst<bits<6> mincode, string opasm> :
   ArcBinaryInst<0b00101, mincode, opasm>;