[ARC] Add <.f> suffix for F32_GEN4_{DOP|SOP}

[yan_luo]

Summary

<.f>: writeback to status register flags

[petecoup]

Hi Yan,

Thanks for working on this!
Can you add some tests to the disassembler for variants that you added here?
Thanks!

[yan_luo]

Pete, I updated the revision, please review it again, thanks!

[petecoup]

Great, thanks!
Do you need me to commit this for you?

[yan_luo]

Yes, Pete. Please land it for me. Thanks!

[petecoup]

Committed in r329404.
Thanks!

lib/Target/ARC/ARCInstrInfo.td

 // Generic 3 operand binary instructions (i.e., add r0, r1, r2).
 multiclass ArcBinaryInst<bits<5> major, bits<6> mincode,
                        string opasm> {
   // 3 register variant.
   def _rrr : F32_DOP_RR<major, mincode, 0, (outs GPR32:$A),
                         (ins GPR32:$B, GPR32:$C),
                         !strconcat(opasm, "\t$A, $B, $C"),
                         []>;
+  def _f_rrr : F32_DOP_RR<major, mincode, 1, (outs GPR32:$A),
+                          (ins GPR32:$B, GPR32:$C),
+                          !strconcat(opasm, ".f\t$A, $B, $C"),
+                          []>
+  { let Defs = [STATUS32]; }
 
   // 2 register with unsigned 6-bit immediate variant.
   def _rru6 : F32_DOP_RU6<major, mincode, 0, (outs GPR32:$A),
                           (ins GPR32:$B, immU6:$U6),
                           !strconcat(opasm, "\t$A, $B, $U6"),
                           []>;
+  def _f_rru6 : F32_DOP_RU6<major, mincode, 1, (outs GPR32:$A),
+                            (ins GPR32:$B, immU6:$U6),
+                            !strconcat(opasm, ".f\t$A, $B, $U6"),
+                            []>
+  { let Defs = [STATUS32]; }
+
   // 2 register with 32-bit immediate variant.
   def _rrlimm : F32_DOP_RLIMM<major, mincode, 0,
                               (outs GPR32:$A),
                               (ins GPR32:$B, i32imm:$LImm),
                               !strconcat(opasm, "\t$A, $B, $LImm"),
                               []>;
+  def _f_rrlimm : F32_DOP_RLIMM<major, mincode, 1,
+                                (outs GPR32:$A),
+                                (ins GPR32:$B, i32imm:$LImm),
+                                !strconcat(opasm, ".f\t$A, $B, $LImm"),
+                                []>
+  { let Defs = [STATUS32]; }
+
   // 2 matched-register with signed 12-bit immediate variant (add r0, r0, -1).
   def _rrs12 : F32_DOP_RS12<major, mincode, 0,
                             (outs GPR32:$B),
                             (ins GPR32:$in, immS<12>:$S12),
                             !strconcat(opasm, "\t$B, $in, $S12"),
                             []>
   { let Constraints = "$B = $in"; }
+  def _f_rrs12 : F32_DOP_RS12<major, mincode, 1,
+                              (outs GPR32:$B),
+                              (ins GPR32:$in, immS<12>:$S12),
+                              !strconcat(opasm, ".f\t$B, $in, $S12"),
+                              []>
+  { let Constraints = "$B = $in"; let Defs = [STATUS32]; }
 }
 
 // Special multivariant GEN4 DOP format instruction that take 2 registers.
 // This is the class that is used for various comparison instructions.
 multiclass ArcSpecialDOPInst<bits<6> subop, string opasm, bit F> {
   def _rr : F32_DOP_RR<0b00100, subop, F, (outs), (ins GPR32:$B, GPR32:$C),
                !strconcat(opasm, "\t$B, $C"),
                []>;
 
   def _ru6 : F32_DOP_RU6<0b00100, subop, F, (outs), (ins GPR32:$B, i32imm:$U6),
                !strconcat(opasm, "\t$B, $U6"),
                []>;
 
   def _rlimm : F32_DOP_RLIMM<0b00100, subop, F, (outs),
                (ins GPR32:$B, i32imm:$LImm),
                !strconcat(opasm, "\t$B, $LImm"),
                []>;
 }
 
 // Generic 2-operand unary instructions.
 multiclass ArcUnaryInst<bits<5> major, bits<6> subop,
                         string opasm> {
   def _rr : F32_SOP_RR<major, subop, 0, (outs GPR32:$B), (ins GPR32:$C),
                        !strconcat(opasm, "\t$B, $C"), []>;
+
+  def _f_rr : F32_SOP_RR<major, subop, 1, (outs GPR32:$B), (ins GPR32:$C),
+                       !strconcat(opasm, ".f\t$B, $C"), []>
+  { let Defs = [STATUS32]; }
 }
 
 
 multiclass ArcBinaryGEN4Inst<bits<6> mincode, string opasm> :
   ArcBinaryInst<0b00100, mincode, opasm>;
 multiclass ArcBinaryEXT5Inst<bits<6> mincode, string opasm> :
   ArcBinaryInst<0b00101, mincode, opasm>;
 

test/MC/Disassembler/ARC/alu.txt

 # RUN: llvm-mc -triple=arc -disassemble %s | FileCheck %s 
 
 # CHECK: add %r0, %r0, %r0 
 0x00 0x20 0x00 0x00 
 
 # CHECK: add %r4, %r0, %r0 
 0x00 0x20 0x04 0x00 
 
+# CHECK: add.f %r4, %r0, %r0
+0x00 0x20 0x04 0x80
+
 # CHECK: add %r2, %r0, %r3 
 0x00 0x20 0xc2 0x00
 
 # CHECK: add %r2, %r0, %r4 
 0x00 0x20 0x02 0x01 
 
 # CHECK: add %r2, %r7, %r4 
 0x00 0x27 0x02 0x01 
 
 # CHECK: and %r2, %r7, %r4 
 0x04 0x27 0x02 0x01 
 
+# CHECK: and.f %r2, %r7, %r4
+0x04 0x27 0x02 0x81
+
 # CHECK: and %r2, %r7, 4 
 0x44 0x27 0x02 0x01 
 
 # CHECK: and %r1, %r1, 255
 0x84 0x21 0xc3 0x0f
 
+# CHECK: and.f %r1, %r1, 255
+0x84 0x21 0xc3 0x8f
+
 # CHECK: asl %r1, %r1, 2 
 0x40 0x29 0x81 0x00 
 
 # CHECK: asl %r0, %r0, %r0
 0x00 0x28 0x00 0x00
 
+# CHECK: asl.f %r0, %r0, %r0
+0x00 0x28 0x00 0x80
+
 # CHECK: asr %r1, %r2, 31
 0x42 0x2a 0xc1 0x07
 
+# CHECK: asr.f %r1, %r2, 31
+0x42 0x2a 0xc1 0x87
+
 # CHECK: asr %r1, %r3, 7
 0x42 0x2b 0xc1 0x01
 
 # CHECK: asr %r1, %r1, %r2
 0x02 0x29 0x81 0x00
 
 # CHECK: max %r0, %r2, %r1
 0x08 0x22 0x40 0x00
 
 # CHECK: max %r0, %r1, 15
 0x48 0x21 0xc0 0x03
 
 # CHECK: max %r0, %r2, 4000
 0x08 0x22 0x80 0x0f 0x00 0x00 0xa0 0x0f
 
 # CHECK: max %r2, %r2, 255
 0x88 0x22 0xc3 0x0f
 
 # CHECK: or %r18, %r16, 61440
 0x05 0x20 0x92 0x2f 0x00 0x00 0x00 0xf0
 
+# CHECK: or.f %r18, %r16, 61440
+0x05 0x20 0x92 0xaf 0x00 0x00 0x00 0xf0
+
 # CHECK: or %r1, %r1, %r14
 0x05 0x21 0x81 0x03
 
 # CHECK: or %r1, %r14, %r1
 0x05 0x26 0x41 0x10
 
 # CHECK: or %r1, %r1, 128
 0x85 0x21 0x02 0x00
 
 # CHECK: sub %sp, %fp, 92
 0x02 0x23 0x9c 0x3f 0x00 0x00 0x5c 0x00
 
 # CHECK: sub %r2, %r7, %r4 
 0x02 0x27 0x02 0x01 
 
+# CHECK: sub.f %r2, %r7, %r4
+0x02 0x27 0x02 0x81
+
 # CHECK: sub %r0, %r22, %r0
 0x02 0x26 0x00 0x20
 
 # CHECK: sub1 %r3, %fp, %r1
 0x17 0x23 0x43 0x30
 
 # CHECK: sub2 %r3, %fp, 17
 0x58 0x23 0x43 0x34
 
 # CHECK: sub3 %fp, %fp, -1
 0x99 0x23 0xff 0x3f
+
+# CHECK: sub3.f %fp, %fp, -1
+0x99 0x23 0xff 0xbf