Simplify more cases of logical ops of masked icmps.

[hjyamauchi]

Summary

For example,

((X & 255) != 0) && ((X & 15) == 8) -> ((X & 15) == 8).
((X & 7) != 0) && ((X & 15) == 8) -> false.

[hjyamauchi]

I found a bug in the first revision. Please hold off reviews. Will update.

[hjyamauchi]

Fixed bugs in the previous revision.

[hjyamauchi]

Ok, ready for reviews.

[davidxl]

test/Transforms/InstCombine/icmp-logical.ll

332 ↗

(On Diff #136573)

This one should be simplified to x & 15 != 9 // aka 1001

364 ↗

(On Diff #136573)

This one should be simplified to x & 15 != 8

430 ↗

(On Diff #136573)

perhaps also add a case of (x&6) == 0) || (x&15)!= 8 ==> true

[hjyamauchi]

Addressed comments.

[davidxl]

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

309 ↗

(On Diff #137265)

Update the comment since return type changes. Also document parameters LHS, RHS, PredL and PredR.

438 ↗

(On Diff #137265)

Document this method with a small example.

444 ↗

(On Diff #137265)

&& -> &

448 ↗

(On Diff #137265)

->

551 ↗

(On Diff #137265)

Add function documentation.

test/Transforms/InstCombine/icmp-logical.ll

204 ↗

(On Diff #137265)

x&&15 --> x&15

341 ↗

(On Diff #137265)

&& --> &

Similarly, || --> | in other places.

[hjyamauchi]

Addressed comments.

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

448 ↗

(On Diff #137265)

What does this comment mean?

[hjyamauchi]

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

448 ↗

(On Diff #137265)

Now I see what you meant. Done. It was formatted as a table :)

[davidxl]

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

440 ↗

(On Diff #137770)

icmp(A&B) ==/!= C

450 ↗

(On Diff #137770)

Do you have test case cover this when LSH and RHS are swapped?

(icmp eq (A &D), E) & (icmp ne (A & B, 0))

454 ↗

(On Diff #137770)

replace 0 with 'C' in the example.

462 ↗

(On Diff #137770)

Do you need to check CCst is Zero?

474 ↗

(On Diff #137770)

It seems to me, it is sufficient to do the following check:

1. check if mask B is a subset of mask D
2. check if (E & B) != 0 is true

If both 1) and 2) are satisfied, the simplification is legal.

[hjyamauchi]

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

454 ↗

(On Diff #137770)

LHS being of type Mask_NotAllZeroes means that LHS is or can be converted into the form "(icmp ne (A & B), 0)". I think 0 would be better here because the right hand side of the LHS isn't necessarily C. Note the case of Mask_NotAllZeroes where B==C and B is a power of two (see lines 216 and 269 above) where we get "(icmp eq (A & B), C)" (B==C) but interpret it as (equivalent) "(icmp ne (A & B), 0)".

462 ↗

(On Diff #137770)

Similarly, C isn't necessarily zero if Mask_NotAllZeroes is due to the case for B==C and B is a power of two. So, no.

474 ↗

(On Diff #137770)

I need a clarification on this.

I think the case you are referring to, which is an important one, is covered by lines 552-553 below. But there are several other cases of simplifications below. There are simplifications we can do even when B isn't a subset of D below, eg. (icmp ne (A & 255), 0) & (icmp eq (A & 15), 8) -> (icmp eq (A & 15), 8).

Do you mean we can drop the other cases?

[hjyamauchi]

Addressed comments.

[hjyamauchi]

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

450 ↗

(On Diff #137770)

Added swapped tests.

[davidxl]

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

499 ↗

(On Diff #138040)

This check can probably be extended:

1. B's bitset subtracts the intersection of B and D contains only one bit
2. B and D's intersection have zero values

In other words, D does not need to be power of 2

530 ↗

(On Diff #138040)

Can you introduce a small lambda here to be reused here and other places?

auto IsSubset = [](Value *V1, Value *V2) {

....

};

if (IsSubset(BCst, DCst)) ....

536 ↗

(On Diff #138040)

Can you split the comment here for case in line 548 and line 552?

[hjyamauchi]

Addressed comments.

[hjyamauchi]

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

499 ↗

(On Diff #138040)

Is there a chance that those two conditions you are referring to *are* what the current code is already checking here?

To be more specific,

Isn't the condition 1 equivalent to "(B & (B ^ D)).isPowerOf2()" that the current code checks?

(I meant "(B & (B ^ D))" as the bits that are 1 in B but 0 in D.)

For example, suppose B = 1100 and D = 0101. The condition 1 would say 1100 - (1100 & 0101) = 1100 - 0100 = 1000 while (B & (B ^ D)) = (1100 & (1100 ^ 0101)) = (1100 & 1001) = 1000.

Also, isn't the condition 2 equivalent to "((B & D) & E) == 0" that the current code checks?

(Note that in the current code, it's not D, but (B & (B ^ D)) that needs to be a power of 2.)

Do you have an example that isn't handled by the current code but is handled by the suggested extension?

[davidxl]

lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

499 ↗

(On Diff #138040)

You are right. Perhaps add a comment just before the condition to document the semantics of the check.

[hjyamauchi]

Addressed comments.

[davidxl]

lgtm

llvm/trunk/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp

if (!llvm::decomposeBitTestICmp(LHS, RHS, Pred, X, Mask))
     return false;
 
   Y = ConstantInt::get(X->getType(), Mask);
   Z = ConstantInt::get(X->getType(), 0);
   return true;
 }
 
 /// Handle (icmp(A & B) ==/!= C) &/| (icmp(A & D) ==/!= E).
-/// Return the set of pattern classes (from MaskedICmpType) that both LHS and
-/// RHS satisfy.
-static unsigned getMaskedTypeForICmpPair(Value *&A, Value *&B, Value *&C,
-                                         Value *&D, Value *&E, ICmpInst *LHS,
-                                         ICmpInst *RHS,
-                                         ICmpInst::Predicate &PredL,
-                                         ICmpInst::Predicate &PredR) {
+/// Return the pattern classes (from MaskedICmpType) for the left hand side and
+/// the right hand side as a pair.
+/// LHS and RHS are the left hand side and the right hand side ICmps and PredL
+/// and PredR are their predicates, respectively.
+static
+Optional<std::pair<unsigned, unsigned>>
+getMaskedTypeForICmpPair(Value *&A, Value *&B, Value *&C,
   // vectors are not (yet?) supported. Don't support pointers either.
   if (!LHS->getOperand(0)->getType()->isIntegerTy() ||
       !RHS->getOperand(0)->getType()->isIntegerTy())
-    return 0;
+    return None;
 
   // Here comes the tricky part:
   // LHS might be of the form L11 & L12 == X, X == L21 & L22,
   // and L11 & L12 == L21 & L22. The same goes for RHS.
   // Now we must find those components L** and R**, that are equal, so
   // that we can extract the parameters A, B, C, D, and E for the canonical
   // above.
   Value *L1 = LHS->getOperand(0);
if (decomposeBitTestICmp(L1, L2, PredL, L11, L12, L2)) {
     if (!match(L2, m_And(m_Value(L21), m_Value(L22)))) {
       L21 = L2;
       L22 = Constant::getAllOnesValue(L2->getType());
     }
   }
 
   // Bail if LHS was a icmp that can't be decomposed into an equality.
   if (!ICmpInst::isEquality(PredL))
-    return 0;
+    return None;
 
   Value *R1 = RHS->getOperand(0);
   Value *R2 = RHS->getOperand(1);
   Value *R11, *R12;
   bool Ok = false;
   if (decomposeBitTestICmp(R1, R2, PredR, R11, R12, R2)) {
     if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) {
       A = R11;
       D = R12;
     } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) {
       A = R12;
       D = R11;
     } else {
-      return 0;
+      return None;
     }
     E = R2;
     R1 = nullptr;
     Ok = true;
   } else {
     if (!match(R1, m_And(m_Value(R11), m_Value(R12)))) {
       // As before, model no mask as a trivial mask if it'll let us do an
       // optimization.
if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) {
       D = R11;
       E = R2;
       Ok = true;
     }
   }
 
   // Bail if RHS was a icmp that can't be decomposed into an equality.
   if (!ICmpInst::isEquality(PredR))
-    return 0;
+    return None;
 
   // Look for ANDs on the right side of the RHS icmp.
   if (!Ok) {
     if (!match(R2, m_And(m_Value(R11), m_Value(R12)))) {
       R11 = R2;
       R12 = Constant::getAllOnesValue(R2->getType());
     }
 
     if (R11 == L11 || R11 == L12 || R11 == L21 || R11 == L22) {
       A = R11;
       D = R12;
       E = R1;
       Ok = true;
     } else if (R12 == L11 || R12 == L12 || R12 == L21 || R12 == L22) {
       A = R12;
       D = R11;
       E = R1;
       Ok = true;
     } else {
-      return 0;
+      return None;
     }
   }
   if (!Ok)
-    return 0;
+    return None;
 
   if (L11 == A) {
     B = L12;
     C = L2;
   } else if (L12 == A) {
     B = L11;
     C = L2;
   } else if (L21 == A) {
     B = L22;
     C = L1;
   } else if (L22 == A) {
     B = L21;
     C = L1;
   }
 
   unsigned LeftType = getMaskedICmpType(A, B, C, PredL);
   unsigned RightType = getMaskedICmpType(A, D, E, PredR);
-  return LeftType & RightType;
+  return Optional<std::pair<unsigned, unsigned>>(std::make_pair(LeftType, RightType));
+}
+
+/// Try to fold (icmp(A & B) ==/!= C) &/| (icmp(A & D) ==/!= E) into a single
+/// (icmp(A & X) ==/!= Y), where the left-hand side is of type Mask_NotAllZeros
+/// and the right hand side is of type BMask_Mixed. For example,
+/// (icmp (A & 12) != 0) & (icmp (A & 15) == 8) -> (icmp (A & 15) == 8).
+static Value * foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed(
+    ICmpInst *LHS, ICmpInst *RHS, bool IsAnd,
+    Value *A, Value *B, Value *C, Value *D, Value *E,
+    ICmpInst::Predicate PredL, ICmpInst::Predicate PredR,
+    llvm::InstCombiner::BuilderTy &Builder) {
+  // We are given the canonical form:
+  //   (icmp ne (A & B), 0) & (icmp eq (A & D), E).
+  // where D & E == E.
+  //
+  // If IsAnd is false, we get it in negated form:
+  //   (icmp eq (A & B), 0) | (icmp ne (A & D), E) ->
+  //      !((icmp ne (A & B), 0) & (icmp eq (A & D), E)).
+  //
+  // We currently handle the case of B, C, D, E are constant.
+  //
+  ConstantInt *BCst = dyn_cast<ConstantInt>(B);
+  if (!BCst)
+    return nullptr;
+  ConstantInt *CCst = dyn_cast<ConstantInt>(C);
+  if (!CCst)
+    return nullptr;
+  ConstantInt *DCst = dyn_cast<ConstantInt>(D);
+  if (!DCst)
+    return nullptr;
+  ConstantInt *ECst = dyn_cast<ConstantInt>(E);
+  if (!ECst)
+    return nullptr;
+
+  ICmpInst::Predicate NewCC = IsAnd ? ICmpInst::ICMP_EQ : ICmpInst::ICMP_NE;
+
+  // Update E to the canonical form when D is a power of two and RHS is
+  // canonicalized as,
+  // (icmp ne (A & D), 0) -> (icmp eq (A & D), D) or
+  // (icmp ne (A & D), D) -> (icmp eq (A & D), 0).
+  if (PredR != NewCC)
+    ECst = cast<ConstantInt>(ConstantExpr::getXor(DCst, ECst));
+
+  // If B or D is zero, skip because if LHS or RHS can be trivially folded by
+  // other folding rules and this pattern won't apply any more.
+  if (BCst->getValue() == 0 || DCst->getValue() == 0)
+    return nullptr;
+
+  // If B and D don't intersect, ie. (B & D) == 0, no folding because we can't
+  // deduce anything from it.
+  // For example,
+  // (icmp ne (A & 12), 0) & (icmp eq (A & 3), 1) -> no folding.
+  if ((BCst->getValue() & DCst->getValue()) == 0)
+    return nullptr;
+
+  // If the following two conditions are met:
+  //
+  // 1. mask B covers only a single bit that's not covered by mask D, that is,
+  // (B & (B ^ D)) is a power of 2 (in other words, B minus the intersection of
+  // B and D has only one bit set) and,
+  //
+  // 2. RHS (and E) indicates that the rest of B's bits are zero (in other
+  // words, the intersection of B and D is zero), that is, ((B & D) & E) == 0
+  //
+  // then that single bit in B must be one and thus the whole expression can be
+  // folded to
+  //   (A & (B | D)) == (B & (B ^ D)) | E.
+  //
+  // For example,
+  // (icmp ne (A & 12), 0) & (icmp eq (A & 7), 1) -> (icmp eq (A & 15), 9)
+  // (icmp ne (A & 15), 0) & (icmp eq (A & 7), 0) -> (icmp eq (A & 15), 8)
+  if ((((BCst->getValue() & DCst->getValue()) & ECst->getValue()) == 0) &&
+      (BCst->getValue() & (BCst->getValue() ^ DCst->getValue())).isPowerOf2()) {
+    APInt BorD = BCst->getValue() | DCst->getValue();
+    APInt BandBxorDorE = (BCst->getValue() & (BCst->getValue() ^ DCst->getValue())) |
+        ECst->getValue();
+    Value *NewMask = ConstantInt::get(BCst->getType(), BorD);
+    Value *NewMaskedValue = ConstantInt::get(BCst->getType(), BandBxorDorE);
+    Value *NewAnd = Builder.CreateAnd(A, NewMask);
+    return Builder.CreateICmp(NewCC, NewAnd, NewMaskedValue);
+  }
+
+  auto IsSubSetOrEqual = [](ConstantInt *C1, ConstantInt *C2) {
+    return (C1->getValue() & C2->getValue()) == C1->getValue();
+  };
+  auto IsSuperSetOrEqual = [](ConstantInt *C1, ConstantInt *C2) {
+    return (C1->getValue() & C2->getValue()) == C2->getValue();
+  };
+
+  // In the following, we consider only the cases where B is a superset of D, B
+  // is a subset of D, or B == D because otherwise there's at least one bit
+  // covered by B but not D, in which case we can't deduce much from it, so
+  // no folding (aside from the single must-be-one bit case right above.)
+  // For example,
+  // (icmp ne (A & 14), 0) & (icmp eq (A & 3), 1) -> no folding.
+  if (!IsSubSetOrEqual(BCst, DCst) && !IsSuperSetOrEqual(BCst, DCst))
+    return nullptr;
+
+  // At this point, either B is a superset of D, B is a subset of D or B == D.
+
+  // If E is zero, if B is a subset of (or equal to) D, LHS and RHS contradict
+  // and the whole expression becomes false (or true if negated), otherwise, no
+  // folding.
+  // For example,
+  // (icmp ne (A & 3), 0) & (icmp eq (A & 7), 0) -> false.
+  // (icmp ne (A & 15), 0) & (icmp eq (A & 3), 0) -> no folding.
+  if (ECst->isZero()) {
+    if (IsSubSetOrEqual(BCst, DCst))
+      return ConstantInt::get(LHS->getType(), !IsAnd);
+    return nullptr;
+  }
+
+  // At this point, B, D, E aren't zero and (B & D) == B, (B & D) == D or B ==
+  // D. If B is a superset of (or equal to) D, since E is not zero, LHS is
+  // subsumed by RHS (RHS implies LHS.) So the whole expression becomes
+  // RHS. For example,
+  // (icmp ne (A & 255), 0) & (icmp eq (A & 15), 8) -> (icmp eq (A & 15), 8).
+  // (icmp ne (A & 15), 0) & (icmp eq (A & 15), 8) -> (icmp eq (A & 15), 8).
+  if (IsSuperSetOrEqual(BCst, DCst))
+    return RHS;
+  // Otherwise, B is a subset of D. If B and E have a common bit set,
+  // ie. (B & E) != 0, then LHS is subsumed by RHS. For example.
+  // (icmp ne (A & 12), 0) & (icmp eq (A & 15), 8) -> (icmp eq (A & 15), 8).
+  assert(IsSubSetOrEqual(BCst, DCst) && "Precondition due to above code");
+  if ((BCst->getValue() & ECst->getValue()) != 0)
+    return RHS;
+  // Otherwise, LHS and RHS contradict and the whole expression becomes false
+  // (or true if negated.) For example,
+  // (icmp ne (A & 7), 0) & (icmp eq (A & 15), 8) -> false.
+  // (icmp ne (A & 6), 0) & (icmp eq (A & 15), 8) -> false.
+  return ConstantInt::get(LHS->getType(), !IsAnd);
+}
+
+/// Try to fold (icmp(A & B) ==/!= 0) &/| (icmp(A & D) ==/!= E) into a single
+/// (icmp(A & X) ==/!= Y), where the left-hand side and the right hand side
+/// aren't of the common mask pattern type.
+static Value *foldLogOpOfMaskedICmpsAsymmetric(
+    ICmpInst *LHS, ICmpInst *RHS, bool IsAnd,
+    Value *A, Value *B, Value *C, Value *D, Value *E,
+    ICmpInst::Predicate PredL, ICmpInst::Predicate PredR,
+    unsigned LHSMask, unsigned RHSMask,
+    llvm::InstCombiner::BuilderTy &Builder) {
+  assert(ICmpInst::isEquality(PredL) && ICmpInst::isEquality(PredR) &&
+         "Expected equality predicates for masked type of icmps.");
+  // Handle Mask_NotAllZeros-BMask_Mixed cases.
+  // (icmp ne/eq (A & B), C) &/| (icmp eq/ne (A & D), E), or
+  // (icmp eq/ne (A & B), C) &/| (icmp ne/eq (A & D), E)
+  //    which gets swapped to
+  //    (icmp ne/eq (A & D), E) &/| (icmp eq/ne (A & B), C).
+  if (!IsAnd) {
+    LHSMask = conjugateICmpMask(LHSMask);
+    RHSMask = conjugateICmpMask(RHSMask);
+  }
+  if ((LHSMask & Mask_NotAllZeros) && (RHSMask & BMask_Mixed)) {
+    if (Value *V = foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed(
+            LHS, RHS, IsAnd, A, B, C, D, E,
+            PredL, PredR, Builder)) {
+      return V;
+    }
+  } else if ((LHSMask & BMask_Mixed) && (RHSMask & Mask_NotAllZeros)) {
+    if (Value *V = foldLogOpOfMaskedICmps_NotAllZeros_BMask_Mixed(
+            RHS, LHS, IsAnd, A, D, E, B, C,
+            PredR, PredL, Builder)) {
+      return V;
+    }
+  }
+  return nullptr;
 }
 
 /// Try to fold (icmp(A & B) ==/!= C) &/| (icmp(A & D) ==/!= E)
 /// into a single (icmp(A & X) ==/!= Y).
 static Value *foldLogOpOfMaskedICmps(ICmpInst *LHS, ICmpInst *RHS, bool IsAnd,
                                      llvm::InstCombiner::BuilderTy &Builder) {
   Value *A = nullptr, *B = nullptr, *C = nullptr, *D = nullptr, *E = nullptr;
   ICmpInst::Predicate PredL = LHS->getPredicate(), PredR = RHS->getPredicate();
-  unsigned Mask =
+  Optional<std::pair<unsigned, unsigned>> MaskPair =
       getMaskedTypeForICmpPair(A, B, C, D, E, LHS, RHS, PredL, PredR);
-  if (Mask == 0)
+  if (!MaskPair)
     return nullptr;
-
   assert(ICmpInst::isEquality(PredL) && ICmpInst::isEquality(PredR) &&
          "Expected equality predicates for masked type of icmps.");
+  unsigned LHSMask = MaskPair->first;
+  unsigned RHSMask = MaskPair->second;
+  unsigned Mask = LHSMask & RHSMask;
+  if (Mask == 0) {
+    // Even if the two sides don't share a common pattern, check if folding can
+    // still happen.
+    if (Value *V = foldLogOpOfMaskedICmpsAsymmetric(
+            LHS, RHS, IsAnd, A, B, C, D, E, PredL, PredR, LHSMask, RHSMask,
+            Builder))
+      return V;
+    return nullptr;
+  }
 
   // In full generality:
   //     (icmp (A & B) Op C) | (icmp (A & D) Op E)
   // ==  ![ (icmp (A & B) !Op C) & (icmp (A & D) !Op E) ]
   //
   // If the latter can be converted into (icmp (A & X) Op Y) then the former is
   // equivalent to (icmp (A & X) !Op Y).
   //

llvm/trunk/test/Transforms/InstCombine/icmp-logical.ll

 ;
   %xor1 = xor <2 x i64> %a, %b
   %xor2 = xor <2 x i64> %c, %d
   %or = or <2 x i64> %xor1, %xor2
   %cmp = icmp ne <2 x i64> %or, zeroinitializer
   ret <2 x i1> %cmp
 }
 
+; ((X & 12) != 0 & (X & 3) == 1) -> no change
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_0(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_0(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 12
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 %x, 3
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i32 [[AND2]], 1
+; CHECK-NEXT:    [[AND3:%.*]] = and i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    ret i1 [[AND3]]
+;
+  %1 = and i32 %x, 12
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 3
+  %4 = icmp eq i32 %3, 1
+  %5 = and i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 12) != 0 & (X & 7) == 1) -> (X & 15) == 9
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_1(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_1(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND1]], 9
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 12
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 7
+  %4 = icmp eq i32 %3, 1
+  %5 = and i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 14) != 0 & (X & 3) == 1) -> no change
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_1b(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_1b(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 14
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 %x, 3
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i32 [[AND2]], 1
+; CHECK-NEXT:    [[AND3:%.*]] = and i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    ret i1 [[AND3]]
+;
+  %1 = and i32 %x, 14
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 3
+  %4 = icmp eq i32 %3, 1
+  %5 = and i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 3) != 0 & (X & 7) == 0) -> false
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_2(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_2(
+; CHECK-NEXT:    ret i1 false
+;
+  %1 = and i32 %x, 3
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 7
+  %4 = icmp eq i32 %3, 0
+  %5 = and i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 15) != 0 & (X & 7) == 0) -> (X & 15) == 8
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_3(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_3(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 15
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 7
+  %4 = icmp eq i32 %3, 0
+  %5 = and i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 15) != 0 & (X & 3) == 0) -> no change
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_3b(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_3b(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 %x, 3
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i32 [[AND2]], 0
+; CHECK-NEXT:    [[AND3:%.*]] = and i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    ret i1 [[AND3]]
+;
+  %1 = and i32 %x, 15
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 3
+  %4 = icmp eq i32 %3, 0
+  %5 = and i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 255) != 0 & (X & 15) == 8) -> (X & 15) == 8
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_4(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_4(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 255
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp eq i32 %3, 8
+  %5 = and i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 15) != 0 & (X & 15) == 8) -> (X & 15) == 8
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_5(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_5(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 15
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp eq i32 %3, 8
+  %5 = and i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 12) != 0 & (X & 15) == 8) -> (X & 15) == 8
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_6(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_6(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 12
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp eq i32 %3, 8
+  %5 = and i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 7) != 0 & (X & 15) == 8) -> false
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_7(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_7(
+; CHECK-NEXT:    ret i1 false
+;
+  %1 = and i32 %x, 7
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp eq i32 %3, 8
+  %5 = and i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 6) != 0 & (X & 15) == 8) -> false
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_7b(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_7b(
+; CHECK-NEXT:    ret i1 false
+;
+  %1 = and i32 %x, 6
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp eq i32 %3, 8
+  %5 = and i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 12) == 0 | (X & 3) != 1) -> !((X & 12) != 0 & (X & 3) == 1)) ->
+; no change
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_0(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_0(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 12
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 %x, 3
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i32 [[AND2]], 1
+; CHECK-NEXT:    [[OR1:%.*]] = or i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    ret i1 [[OR1]]
+;
+  %1 = and i32 %x, 12
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 3
+  %4 = icmp ne i32 %3, 1
+  %5 = or i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 12) == 0 | (X & 7) != 1) -> !((X & 12) != 0 & (X & 7) == 1) ->
+; !((X & 15) == 9) -> (X & 15) != 9
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_1(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_1(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND1]], 9
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 12
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 7
+  %4 = icmp ne i32 %3, 1
+  %5 = or i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 14) == 0 | (X & 3) != 1) -> !((X & 14) != 0 & (X & 3) == 1) ->
+; no change.
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_1b(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_1b(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 14
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 %x, 3
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i32 [[AND2]], 1
+; CHECK-NEXT:    [[OR1:%.*]] = or i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    ret i1 [[OR1]]
+;
+  %1 = and i32 %x, 14
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 3
+  %4 = icmp ne i32 %3, 1
+  %5 = or i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 3) == 0 | (X & 7) != 0) -> !((X & 3) != 0 & (X & 7) == 0) ->
+; !(false) -> true
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_2(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_2(
+; CHECK-NEXT:    ret i1 true
+;
+  %1 = and i32 %x, 3
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 7
+  %4 = icmp ne i32 %3, 0
+  %5 = or i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 15) == 0 | (X & 7) != 0) -> !((X & 15) != 0 & (X & 7) == 0) ->
+; !((X & 15) == 8) -> (X & 15) != 8
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_3(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_3(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 15
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 7
+  %4 = icmp ne i32 %3, 0
+  %5 = or i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 15) == 0 | (X & 3) != 0) -> !((X & 15) != 0 & (X & 3) == 0) ->
+; no change.
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_3b(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_3b(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 %x, 3
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i32 [[AND2]], 0
+; CHECK-NEXT:    [[OR1:%.*]] = or i1 [[CMP1]], [[CMP2]]
+; CHECK-NEXT:    ret i1 [[OR1]]
+;
+  %1 = and i32 %x, 15
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 3
+  %4 = icmp ne i32 %3, 0
+  %5 = or i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 255) == 0 | (X & 15) != 8) -> !(((X & 255) != 0 & (X & 15) == 8)) ->
+; !((X & 15) == 8) -> ((X & 15) != 8)
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_4(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_4(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 255
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp ne i32 %3, 8
+  %5 = or i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 15) == 0 | (X & 15) != 8) -> !(((X & 15) != 0 & (X & 15) == 8)) ->
+; !((X & 15) == 8) -> ((X & 15) != 8)
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_5(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_5(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 15
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp ne i32 %3, 8
+  %5 = or i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 12) == 0 | (X & 15) != 8) -> !(((X & 12) != 0 & (X & 15) == 8)) ->
+; !((X & 15) == 8) -> ((X & 15) != 8
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_6(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_6(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 12
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp ne i32 %3, 8
+  %5 = or i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 7) == 0 | (X & 15) != 8) -> !(((X & 7) != 0 & (X & 15) == 8)) ->
+; !(false) -> true
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_7(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_7(
+; CHECK-NEXT:    ret i1 true
+;
+  %1 = and i32 %x, 7
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp ne i32 %3, 8
+  %5 = or i1 %2, %4
+  ret i1 %5
+}
+
+; ((X & 6) == 0 | (X & 15) != 8) -> !(((X & 6) != 0 & (X & 15) == 8)) ->
+; !(false) -> true
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_7b(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_7b(
+; CHECK-NEXT:    ret i1 true
+;
+  %1 = and i32 %x, 6
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp ne i32 %3, 8
+  %5 = or i1 %2, %4
+  ret i1 %5
+}
+
+
+; ((X & 12) != 0 & (X & 3) == 1) -> no change
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_0(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_0(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 12
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 %x, 3
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i32 [[AND2]], 1
+; CHECK-NEXT:    [[AND3:%.*]] = and i1 [[CMP2]], [[CMP1]]
+; CHECK-NEXT:    ret i1 [[AND3]]
+;
+  %1 = and i32 %x, 12
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 3
+  %4 = icmp eq i32 %3, 1
+  %5 = and i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 12) != 0 & (X & 7) == 1) -> (X & 15) == 9
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND1]], 9
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 12
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 7
+  %4 = icmp eq i32 %3, 1
+  %5 = and i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 14) != 0 & (X & 3) == 1) -> no change
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1b(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_1b(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 14
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 %x, 3
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i32 [[AND2]], 1
+; CHECK-NEXT:    [[AND3:%.*]] = and i1 [[CMP2]], [[CMP1]]
+; CHECK-NEXT:    ret i1 [[AND3]]
+;
+  %1 = and i32 %x, 14
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 3
+  %4 = icmp eq i32 %3, 1
+  %5 = and i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 3) != 0 & (X & 7) == 0) -> false
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_2(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_2(
+; CHECK-NEXT:    ret i1 false
+;
+  %1 = and i32 %x, 3
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 7
+  %4 = icmp eq i32 %3, 0
+  %5 = and i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 15) != 0 & (X & 7) == 0) -> (X & 15) == 8
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 15
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 7
+  %4 = icmp eq i32 %3, 0
+  %5 = and i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 15) != 0 & (X & 3) == 0) -> no change
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3b(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_3b(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND1]], 0
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 %x, 3
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp eq i32 [[AND2]], 0
+; CHECK-NEXT:    [[AND3:%.*]] = and i1 [[CMP2]], [[CMP1]]
+; CHECK-NEXT:    ret i1 [[AND3]]
+;
+  %1 = and i32 %x, 15
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 3
+  %4 = icmp eq i32 %3, 0
+  %5 = and i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 255) != 0 & (X & 15) == 8) -> (X & 15) == 8
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_4(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_4(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 255
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp eq i32 %3, 8
+  %5 = and i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 15) != 0 & (X & 15) == 8) -> (X & 15) == 8
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_5(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_5(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 15
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp eq i32 %3, 8
+  %5 = and i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 12) != 0 & (X & 15) == 8) -> (X & 15) == 8
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_6(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_6(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND1]], 8
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 12
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp eq i32 %3, 8
+  %5 = and i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 7) != 0 & (X & 15) == 8) -> false
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7(
+; CHECK-NEXT:    ret i1 false
+;
+  %1 = and i32 %x, 7
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp eq i32 %3, 8
+  %5 = and i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 6) != 0 & (X & 15) == 8) -> false
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7b(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_swapped_7b(
+; CHECK-NEXT:    ret i1 false
+;
+  %1 = and i32 %x, 6
+  %2 = icmp ne i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp eq i32 %3, 8
+  %5 = and i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 12) == 0 | (X & 3) != 1) -> !((X & 12) != 0 & (X & 3) == 1)) ->
+; no change
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_0(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_0(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 12
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 %x, 3
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i32 [[AND2]], 1
+; CHECK-NEXT:    [[OR1:%.*]] = or i1 [[CMP2]], [[CMP1]]
+; CHECK-NEXT:    ret i1 [[OR1]]
+;
+  %1 = and i32 %x, 12
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 3
+  %4 = icmp ne i32 %3, 1
+  %5 = or i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 12) == 0 | (X & 7) != 1) -> !((X & 12) != 0 & (X & 7) == 1) ->
+; !((X & 15) == 9) -> (X & 15) != 9
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND1]], 9
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 12
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 7
+  %4 = icmp ne i32 %3, 1
+  %5 = or i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 14) == 0 | (X & 3) != 1) -> !((X & 14) != 0 & (X & 3) == 1) ->
+; no change.
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1b(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_1b(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 14
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 %x, 3
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i32 [[AND2]], 1
+; CHECK-NEXT:    [[OR1:%.*]] = or i1 [[CMP2]], [[CMP1]]
+; CHECK-NEXT:    ret i1 [[OR1]]
+;
+  %1 = and i32 %x, 14
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 3
+  %4 = icmp ne i32 %3, 1
+  %5 = or i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 3) == 0 | (X & 7) != 0) -> !((X & 3) != 0 & (X & 7) == 0) ->
+; !(false) -> true
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_2(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_2(
+; CHECK-NEXT:    ret i1 true
+;
+  %1 = and i32 %x, 3
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 7
+  %4 = icmp ne i32 %3, 0
+  %5 = or i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 15) == 0 | (X & 7) != 0) -> !((X & 15) != 0 & (X & 7) == 0) ->
+; !((X & 15) == 8) -> (X & 15) != 8
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 15
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 7
+  %4 = icmp ne i32 %3, 0
+  %5 = or i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 15) == 0 | (X & 3) != 0) -> !((X & 15) != 0 & (X & 3) == 0) ->
+; no change.
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3b(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_3b(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp eq i32 [[AND1]], 0
+; CHECK-NEXT:    [[AND2:%.*]] = and i32 %x, 3
+; CHECK-NEXT:    [[CMP2:%.*]] = icmp ne i32 [[AND2]], 0
+; CHECK-NEXT:    [[OR1:%.*]] = or i1 [[CMP2]], [[CMP1]]
+; CHECK-NEXT:    ret i1 [[OR1]]
+;
+  %1 = and i32 %x, 15
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 3
+  %4 = icmp ne i32 %3, 0
+  %5 = or i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 255) == 0 | (X & 15) != 8) -> !(((X & 255) != 0 & (X & 15) == 8)) ->
+; !((X & 15) == 8) -> ((X & 15) != 8)
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_4(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_4(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 255
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp ne i32 %3, 8
+  %5 = or i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 15) == 0 | (X & 15) != 8) -> !(((X & 15) != 0 & (X & 15) == 8)) ->
+; !((X & 15) == 8) -> ((X & 15) != 8)
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_5(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_5(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 15
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp ne i32 %3, 8
+  %5 = or i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 12) == 0 | (X & 15) != 8) -> !(((X & 12) != 0 & (X & 15) == 8)) ->
+; !((X & 15) == 8) -> ((X & 15) != 8
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_6(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_6(
+; CHECK-NEXT:    [[AND1:%.*]] = and i32 %x, 15
+; CHECK-NEXT:    [[CMP1:%.*]] = icmp ne i32 [[AND1]], 8
+; CHECK-NEXT:    ret i1 [[CMP1]]
+;
+  %1 = and i32 %x, 12
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp ne i32 %3, 8
+  %5 = or i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 7) == 0 | (X & 15) != 8) -> !(((X & 7) != 0 & (X & 15) == 8)) ->
+; !(false) -> true
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7(
+; CHECK-NEXT:    ret i1 true
+;
+  %1 = and i32 %x, 7
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp ne i32 %3, 8
+  %5 = or i1 %4, %2
+  ret i1 %5
+}
+
+; ((X & 6) == 0 | (X & 15) != 8) -> !(((X & 6) != 0 & (X & 15) == 8)) ->
+; !(false) -> true
+define i1 @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7b(i32 %x) {
+; CHECK-LABEL: @masked_icmps_mask_notallzeros_bmask_mixed_negated_swapped_7b(
+; CHECK-NEXT:    ret i1 true
+;
+  %1 = and i32 %x, 6
+  %2 = icmp eq i32 %1, 0
+  %3 = and i32 %x, 15
+  %4 = icmp ne i32 %3, 8
+  %5 = or i1 %4, %2
+  ret i1 %5
+}