[MI scheduler] Fix VADD and VSUB in cortex-a57 model

[evgeny777]

Summary

The "VADD" regex incorrectly captures VADDfq and other vector floating-point adds, which have 5 cycles latency instead of 3.

[javed.absar]

test/CodeGen/ARM/cortex-a57-misched-vadd.ll

3 ↗

(On Diff #123593)

Please add CHECK-LABEL to separate the tests for the two functions below

[evgeny777]

Addressed review comments. Also added fix for VSUB, which was also broken.

[javed.absar]

Thanks for this.

llvm/trunk/lib/Target/ARM/ARMScheduleA57.td

 def A57WriteVABAL : SchedWriteRes<[A57UnitX]> { let Latency = 4; }
 def A57ReadVABAL  : SchedReadAdvance<3, [A57WriteVABAL]>;
 def : InstRW<[A57WriteVABAL, A57ReadVABAL], (instregex "VABAL(s|u)")>;
 
 // ASIMD absolute diff long: 3cyc F0/F1 for VABDL
 def : InstRW<[A57Write_3cyc_1V], (instregex "VABDL(s|u)")>;
 
 // ASIMD arith, basic
-def : InstRW<[A57Write_3cyc_1V], (instregex "VADD", "VADDL", "VADDW",
+def : InstRW<[A57Write_3cyc_1V], (instregex "VADDv", "VADDL", "VADDW",
   "VNEG(s8d|s16d|s32d|s8q|s16q|s32q|d|q)",
-  "VPADDi", "VPADDL", "VSUB", "VSUBL", "VSUBW")>;
+  "VPADDi", "VPADDL", "VSUBv", "VSUBL", "VSUBW")>;
 
 // ASIMD arith, complex
 def : InstRW<[A57Write_3cyc_1V], (instregex "VABS", "VADDHN", "VHADD", "VHSUB",
   "VQABS", "VQADD", "VQNEG", "VQSUB",
   "VRADDHN", "VRHADD", "VRSUBHN", "VSUBHN")>;
 
 // ASIMD compare
 def : InstRW<[A57Write_3cyc_1V],

llvm/trunk/test/CodeGen/ARM/cortex-a57-misched-vadd.ll

+; REQUIRES: asserts
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+
+; CHECK-LABEL:  addv_i32:BB#0
+; CHECK:        SU(8): {{.*}} VADDv4i32
+; CHECK-NEXT:   # preds left
+; CHECK-NEXT:   # succs left
+; CHECK-NEXT:   # rdefs left
+; CHECK-NEXT:   Latency : 3
+
+define <4 x i32> @addv_i32(<4 x i32>, <4 x i32>) {
+  %3 = add <4 x i32> %1, %0
+  ret <4 x i32> %3
+}
+
+; CHECK-LABEL:  addv_f32:BB#0
+; CHECK:        SU(8): {{.*}} VADDfq
+; CHECK-NEXT:   # preds left
+; CHECK-NEXT:   # succs left
+; CHECK-NEXT:   # rdefs left
+; CHECK-NEXT:   Latency : 5
+
+define <4 x float> @addv_f32(<4 x float>, <4 x float>) {
+  %3 = fadd <4 x float> %0, %1
+  ret <4 x float> %3
+}

llvm/trunk/test/CodeGen/ARM/cortex-a57-misched-vsub.ll

+; REQUIRES: asserts
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
+
+; CHECK-LABEL:  subv_i32:BB#0
+; CHECK:        SU(8): {{.*}} VSUBv4i32
+; CHECK-NEXT:   # preds left
+; CHECK-NEXT:   # succs left
+; CHECK-NEXT:   # rdefs left
+; CHECK-NEXT:   Latency : 3
+
+define <4 x i32> @subv_i32(<4 x i32>, <4 x i32>) {
+  %3 = sub <4 x i32> %1, %0
+  ret <4 x i32> %3
+}
+
+; CHECK-LABEL:  subv_f32:BB#0
+; CHECK:        SU(8): {{.*}} VSUBfq
+; CHECK-NEXT:   # preds left
+; CHECK-NEXT:   # succs left
+; CHECK-NEXT:   # rdefs left
+; CHECK-NEXT:   Latency : 5
+
+define <4 x float> @subv_f32(<4 x float>, <4 x float>) {
+  %3 = fsub <4 x float> %0, %1
+  ret <4 x float> %3
+}