[X86] Add a .def file to contain information about mapping vendor/type/subtype to -march strings

[craig.topper]

Summary

Hoping to share this with clang to allow sharing with implementation of __builtin_cpu_is

[craig.topper]

I added a CPUISVALID that you should be able to use to know if its valid for builtin_cpu_is. The name for builtin_cpu_is is the first string. Empty string if its not valid. The corresponding march names are the second string. Host.cpp needed to translate to -march names.

[erichkeane]

include/llvm/Support/X86TargetParser.def

21

One thin gthat would be incredibly useful (and remove most of the need for the table in clang) is if this also contained the 64bit-ness of the processor.

ALSO, If you cuold remove the namespace from all of these (perhaps just use a 'using' elsewhere?) I could use it to create the enum names as well.

73

Why does amdfam17h appear 2x? Should the 1st be znver1?

include/llvm/Support/TargetParser.h

 unsigned parseArchExt(StringRef ArchExt);
 ArchKind parseCPUArch(StringRef CPU);
 ARM::ISAKind parseArchISA(StringRef Arch);
 ARM::EndianKind parseArchEndian(StringRef Arch);
 ARM::ProfileKind parseArchProfile(StringRef Arch);
 unsigned parseArchVersion(StringRef Arch);
 
 } // namespace AArch64
+
+namespace X86 {
+
+// This should be kept in sync with libcc/compiler-rt as its include by clang
+// as a proxy for what's in libgcc/compiler-rt.
+enum ProcessorVendors : unsigned {
+  VENDOR_INTEL = 1,
+  VENDOR_AMD,
+  VENDOR_OTHER
+};
+
+// This should be kept in sync with libcc/compiler-rt as its include by clang
+// as a proxy for what's in libgcc/compiler-rt.
+enum ProcessorTypes : unsigned {
+  INTEL_BONNELL = 1,
+  INTEL_CORE2,
+  INTEL_COREI7,
+  AMDFAM10H,
+  AMDFAM15H,
+  INTEL_SILVERMONT,
+  INTEL_KNL,
+  AMD_BTVER1,
+  AMD_BTVER2,
+  AMDFAM17H,
+  INTEL_KNM,
+  // Entries below this are not in libgcc/compiler-rt.
+  INTEL_i386,
+  INTEL_i486,
+  INTEL_PENTIUM,
+  INTEL_PENTIUM_MMX,
+  INTEL_PENTIUM_PRO,
+  INTEL_PENTIUM_II,
+  INTEL_PENTIUM_III,
+  INTEL_PENTIUM_IV,
+  INTEL_PENTIUM_M,
+  INTEL_CORE_DUO,
+  INTEL_X86_64,
+  INTEL_NOCONA,
+  INTEL_PRESCOTT,
+  AMD_i486,
+  AMDPENTIUM,
+  AMDATHLON,
+  INTEL_GOLDMONT,
+};
+
+// This should be kept in sync with libcc/compiler-rt as its include by clang
+// as a proxy for what's in libgcc/compiler-rt.
+enum ProcessorSubtypes : unsigned {
+  INTEL_COREI7_NEHALEM = 1,
+  INTEL_COREI7_WESTMERE,
+  INTEL_COREI7_SANDYBRIDGE,
+  AMDFAM10H_BARCELONA,
+  AMDFAM10H_SHANGHAI,
+  AMDFAM10H_ISTANBUL,
+  AMDFAM15H_BDVER1,
+  AMDFAM15H_BDVER2,
+  AMDFAM15H_BDVER3,
+  AMDFAM15H_BDVER4,
+  AMDFAM17H_ZNVER1,
+  INTEL_COREI7_IVYBRIDGE,
+  INTEL_COREI7_HASWELL,
+  INTEL_COREI7_BROADWELL,
+  INTEL_COREI7_SKYLAKE,
+  INTEL_COREI7_SKYLAKE_AVX512,
+  // Entries below this are not in libgcc/compiler-rt.
+  INTEL_CORE2_65,
+  INTEL_CORE2_45,
+  AMDPENTIUM_K6,
+  AMDPENTIUM_K62,
+  AMDPENTIUM_K63,
+  AMDPENTIUM_GEODE,
+  AMDATHLON_CLASSIC,
+  AMDATHLON_XP,
+  AMDATHLON_K8,
+  AMDATHLON_K8SSE3,
+};
+
+enum ProcessorFeatures {
+  FEATURE_CMOV = 0,
+  FEATURE_MMX,
+  FEATURE_POPCNT,
+  FEATURE_SSE,
+  FEATURE_SSE2,
+  FEATURE_SSE3,
+  FEATURE_SSSE3,
+  FEATURE_SSE4_1,
+  FEATURE_SSE4_2,
+  FEATURE_AVX,
+  FEATURE_AVX2,
+  FEATURE_SSE4_A,
+  FEATURE_FMA4,
+  FEATURE_XOP,
+  FEATURE_FMA,
+  FEATURE_AVX512F,
+  FEATURE_BMI,
+  FEATURE_BMI2,
+  FEATURE_AES,
+  FEATURE_PCLMUL,
+  FEATURE_AVX512VL,
+  FEATURE_AVX512BW,
+  FEATURE_AVX512DQ,
+  FEATURE_AVX512CD,
+  FEATURE_AVX512ER,
+  FEATURE_AVX512PF,
+  FEATURE_AVX512VBMI,
+  FEATURE_AVX512IFMA,
+  FEATURE_AVX5124VNNIW,
+  FEATURE_AVX5124FMAPS,
+  FEATURE_AVX512VPOPCNTDQ,
+  // Only one bit free left in the first 32 features.
+  FEATURE2_MOVBE = 0,
+  FEATURE2_ADX,
+  FEATURE2_EM64T,
+  FEATURE2_CLFLUSHOPT,
+  FEATURE2_SHA,
+};
+
+} // namespace X86
+
 } // namespace llvm
 
 #endif

include/llvm/Support/X86TargetParser.def

+//===- X86TargetParser.def - X86 target parsing defines ---------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file provides defines to build up the X86 target parser's logic.
+//
+//===----------------------------------------------------------------------===//
+
+// NOTE: NO INCLUDE GUARD DESIRED!
+
+// Vendor, type and subtype system used by Host.cpp and compiler-rt. This is
+// to share with clang.
+#ifndef X86_VENDOR_TYPE_SUBTYPE
+#define X86_VENDOR_TYPE_SUBTYPE(CPUISNAME, ARCHNAME, CPUISVALID, VENDOR, TYPE, SUBTYPE)
+#endif
+X86_VENDOR_TYPE_SUBTYPE("", "i386", false, X86::VENDOR_INTEL, X86::INTEL_i386, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "i486", false, X86::VENDOR_INTEL, X86::INTEL_i486, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "pentium", false, X86::VENDOR_INTEL, X86::INTEL_PENTIUM, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "pentium-mmx", false, X86::VENDOR_INTEL, X86::INTEL_PENTIUM_MMX, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "pentiumpro", false, X86::VENDOR_INTEL, X86::INTEL_PENTIUM_PRO, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "pentium2", false, X86::VENDOR_INTEL, X86::INTEL_PENTIUM_II, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "pentium3", false, X86::VENDOR_INTEL, X86::INTEL_PENTIUM_III, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "pentium4", false, X86::VENDOR_INTEL, X86::INTEL_PENTIUM_IV, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "pentium-m", false, X86::VENDOR_INTEL, X86::INTEL_PENTIUM_M, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "pentium-m", false, X86::VENDOR_INTEL, X86::INTEL_CORE_DUO, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "nocona", false, X86::VENDOR_INTEL, X86::INTEL_NOCONA, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "prescott", false, X86::VENDOR_INTEL, X86::INTEL_PRESCOTT, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "x86-64", false, X86::VENDOR_INTEL, X86::INTEL_X86_64, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "core2", false, X86::VENDOR_INTEL, X86::INTEL_CORE2, X86::INTEL_CORE2_65)
+X86_VENDOR_TYPE_SUBTYPE("", "penryn", false, X86::VENDOR_INTEL, X86::INTEL_CORE2, X86::INTEL_CORE2_45)
+X86_VENDOR_TYPE_SUBTYPE("core2", "core2", true, X86::VENDOR_INTEL, X86::INTEL_CORE2, 0)
+X86_VENDOR_TYPE_SUBTYPE("nehalem", "nehalem", true, X86::VENDOR_INTEL, X86::INTEL_COREI7, X86::INTEL_COREI7_NEHALEM)
+X86_VENDOR_TYPE_SUBTYPE("westmere", "westmere", true, X86::VENDOR_INTEL, X86::INTEL_COREI7, X86::INTEL_COREI7_WESTMERE)
+X86_VENDOR_TYPE_SUBTYPE("sandybridge", "sandybridge", true, X86::VENDOR_INTEL, X86::INTEL_COREI7, X86::INTEL_COREI7_SANDYBRIDGE)
+X86_VENDOR_TYPE_SUBTYPE("ivybridge", "ivybridge", true, X86::VENDOR_INTEL, X86::INTEL_COREI7, X86::INTEL_COREI7_IVYBRIDGE)
+X86_VENDOR_TYPE_SUBTYPE("haswell", "haswell", true, X86::VENDOR_INTEL, X86::INTEL_COREI7, X86::INTEL_COREI7_HASWELL)
+X86_VENDOR_TYPE_SUBTYPE("broadwell", "broadwell", true, X86::VENDOR_INTEL, X86::INTEL_COREI7, X86::INTEL_COREI7_BROADWELL)
+X86_VENDOR_TYPE_SUBTYPE("skylake", "skylake", true, X86::VENDOR_INTEL, X86::INTEL_COREI7, X86::INTEL_COREI7_SKYLAKE)
+X86_VENDOR_TYPE_SUBTYPE("skylake-avx512", "skylake-avx512", true, X86::VENDOR_INTEL, X86::INTEL_COREI7, X86::INTEL_COREI7_SKYLAKE_AVX512)
+X86_VENDOR_TYPE_SUBTYPE("corei7", "nehalem", true, X86::VENDOR_INTEL, X86::INTEL_COREI7, 0)
+X86_VENDOR_TYPE_SUBTYPE("bonnell", "bonnell", true, X86::VENDOR_INTEL, X86::INTEL_BONNELL, 0)
+X86_VENDOR_TYPE_SUBTYPE("silvermont", "silvermont", true, X86::VENDOR_INTEL, X86::INTEL_SILVERMONT, 0)
+X86_VENDOR_TYPE_SUBTYPE("goldmont", "goldmont", true, X86::VENDOR_INTEL, X86::INTEL_GOLDMONT, 0)
+X86_VENDOR_TYPE_SUBTYPE("knl", "knl", true, X86::VENDOR_INTEL, X86::INTEL_KNL, 0)
+X86_VENDOR_TYPE_SUBTYPE("knm", "knm", true, X86::VENDOR_INTEL, X86::INTEL_KNM, 0)
+X86_VENDOR_TYPE_SUBTYPE("intel", "generic", true, X86::VENDOR_INTEL, 0, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "i486", false, X86::VENDOR_AMD, X86::AMD_i486, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "k6", false, X86::VENDOR_AMD, X86::AMDPENTIUM, X86::AMDPENTIUM_K6)
+X86_VENDOR_TYPE_SUBTYPE("", "k6-2", false, X86::VENDOR_AMD, X86::AMDPENTIUM, X86::AMDPENTIUM_K62)
+X86_VENDOR_TYPE_SUBTYPE("", "k6-3", false, X86::VENDOR_AMD, X86::AMDPENTIUM, X86::AMDPENTIUM_K63)
+X86_VENDOR_TYPE_SUBTYPE("", "geode", false, X86::VENDOR_AMD, X86::AMDPENTIUM, X86::AMDPENTIUM_GEODE)
+X86_VENDOR_TYPE_SUBTYPE("", "pentium", false, X86::VENDOR_AMD, X86::AMDPENTIUM, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "athlon", false, X86::VENDOR_AMD, X86::AMDATHLON_CLASSIC, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "athlon-xp", false, X86::VENDOR_AMD, X86::AMDATHLON_XP, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "k8", false, X86::VENDOR_AMD, X86::AMDATHLON_K8, 0)
+X86_VENDOR_TYPE_SUBTYPE("", "k8-sse3", false, X86::VENDOR_AMD, X86::AMDATHLON_K8SSE3, 0)
+X86_VENDOR_TYPE_SUBTYPE("barcelona", "amdfam10", true, X86::VENDOR_AMD, X86::AMDFAM10H, X86::AMDFAM10H_BARCELONA)
+X86_VENDOR_TYPE_SUBTYPE("shanghai", "amdfam10", true, X86::VENDOR_AMD, X86::AMDFAM10H, X86::AMDFAM10H_SHANGHAI)
+X86_VENDOR_TYPE_SUBTYPE("istanbul", "amdfam10", true, X86::VENDOR_AMD, X86::AMDFAM10H, X86::AMDFAM10H_ISTANBUL)
+X86_VENDOR_TYPE_SUBTYPE("amdfam10h", "amdfam10", true, X86::VENDOR_AMD, X86::AMDFAM10H, 0)
+X86_VENDOR_TYPE_SUBTYPE("btver1", "btver1", true, X86::VENDOR_AMD, X86::AMD_BTVER1, 0)
+X86_VENDOR_TYPE_SUBTYPE("btver2", "btver2", true, X86::VENDOR_AMD, X86::AMD_BTVER2, 0)
+X86_VENDOR_TYPE_SUBTYPE("bdver1", "bdver1", true, X86::VENDOR_AMD, X86::AMDFAM15H, X86::AMDFAM15H_BDVER1)
+X86_VENDOR_TYPE_SUBTYPE("bdver2", "bdver2", true, X86::VENDOR_AMD, X86::AMDFAM15H, X86::AMDFAM15H_BDVER2)
+X86_VENDOR_TYPE_SUBTYPE("bdver3", "bdver3", true, X86::VENDOR_AMD, X86::AMDFAM15H, X86::AMDFAM15H_BDVER3)
+X86_VENDOR_TYPE_SUBTYPE("bdver4", "bdver4", true, X86::VENDOR_AMD, X86::AMDFAM15H, X86::AMDFAM15H_BDVER4)
+X86_VENDOR_TYPE_SUBTYPE("amdfam15h", "bdver1", true, X86::VENDOR_AMD, X86::AMDFAM15H, 0)
+X86_VENDOR_TYPE_SUBTYPE("amdfam17h", "znver1", true, X86::VENDOR_AMD, X86::AMDFAM17H, X86::AMDFAM17H_ZNVER1)
+X86_VENDOR_TYPE_SUBTYPE("amdfam17h", "znver1", true, X86::VENDOR_AMD, X86::AMDFAM17H, 0)
+X86_VENDOR_TYPE_SUBTYPE("amd", "generic", true, X86::VENDOR_AMD, 0, 0)
+#undef X86_VENDOR_TYPE_SUBTYPE

lib/Support/Host.cpp

 //===-- Host.cpp - Implement OS Host Concept --------------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 //  This file implements the operating system Host concept.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Support/Host.h"
+#include "llvm/Support/TargetParser.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/Config/config.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/FileSystem.h"
#else
   }
   return "v1";
 #endif
 }
 
 #if defined(__i386__) || defined(_M_IX86) || \
     defined(__x86_64__) || defined(_M_X64)
 
-enum VendorSignatures {
+enum VendorSignatures : unsigned {
   SIG_INTEL = 0x756e6547 /* Genu */,
   SIG_AMD = 0x68747541 /* Auth */
 };
 
-enum ProcessorVendors {
-  VENDOR_INTEL = 1,
-  VENDOR_AMD,
-  VENDOR_OTHER,
-  VENDOR_MAX
-};
-
-enum ProcessorTypes {
-  INTEL_BONNELL = 1,
-  INTEL_CORE2,
-  INTEL_COREI7,
-  AMDFAM10H,
-  AMDFAM15H,
-  INTEL_SILVERMONT,
-  INTEL_KNL,
-  AMD_BTVER1,
-  AMD_BTVER2,
-  AMDFAM17H,
-  INTEL_KNM,
-  // Entries below this are not in libgcc/compiler-rt.
-  INTEL_i386,
-  INTEL_i486,
-  INTEL_PENTIUM,
-  INTEL_PENTIUM_MMX,
-  INTEL_PENTIUM_PRO,
-  INTEL_PENTIUM_II,
-  INTEL_PENTIUM_III,
-  INTEL_PENTIUM_IV,
-  INTEL_PENTIUM_M,
-  INTEL_CORE_DUO,
-  INTEL_X86_64,
-  INTEL_NOCONA,
-  INTEL_PRESCOTT,
-  AMD_i486,
-  AMDPENTIUM,
-  AMDATHLON,
-  INTEL_GOLDMONT,
-  CPU_TYPE_MAX
-};
-
-enum ProcessorSubtypes {
-  INTEL_COREI7_NEHALEM = 1,
-  INTEL_COREI7_WESTMERE,
-  INTEL_COREI7_SANDYBRIDGE,
-  AMDFAM10H_BARCELONA,
-  AMDFAM10H_SHANGHAI,
-  AMDFAM10H_ISTANBUL,
-  AMDFAM15H_BDVER1,
-  AMDFAM15H_BDVER2,
-  AMDFAM15H_BDVER3,
-  AMDFAM15H_BDVER4,
-  AMDFAM17H_ZNVER1,
-  INTEL_COREI7_IVYBRIDGE,
-  INTEL_COREI7_HASWELL,
-  INTEL_COREI7_BROADWELL,
-  INTEL_COREI7_SKYLAKE,
-  INTEL_COREI7_SKYLAKE_AVX512,
-  // Entries below this are not in libgcc/compiler-rt.
-  INTEL_CORE2_65,
-  INTEL_CORE2_45,
-  AMDPENTIUM_K6,
-  AMDPENTIUM_K62,
-  AMDPENTIUM_K63,
-  AMDPENTIUM_GEODE,
-  AMDATHLON_CLASSIC,
-  AMDATHLON_XP,
-  AMDATHLON_K8,
-  AMDATHLON_K8SSE3,
-  CPU_SUBTYPE_MAX
-};
-
-enum ProcessorFeatures {
-  FEATURE_CMOV = 0,
-  FEATURE_MMX,
-  FEATURE_POPCNT,
-  FEATURE_SSE,
-  FEATURE_SSE2,
-  FEATURE_SSE3,
-  FEATURE_SSSE3,
-  FEATURE_SSE4_1,
-  FEATURE_SSE4_2,
-  FEATURE_AVX,
-  FEATURE_AVX2,
-  FEATURE_SSE4_A,
-  FEATURE_FMA4,
-  FEATURE_XOP,
-  FEATURE_FMA,
-  FEATURE_AVX512F,
-  FEATURE_BMI,
-  FEATURE_BMI2,
-  FEATURE_AES,
-  FEATURE_PCLMUL,
-  FEATURE_AVX512VL,
-  FEATURE_AVX512BW,
-  FEATURE_AVX512DQ,
-  FEATURE_AVX512CD,
-  FEATURE_AVX512ER,
-  FEATURE_AVX512PF,
-  FEATURE_AVX512VBMI,
-  FEATURE_AVX512IFMA,
-  FEATURE_AVX5124VNNIW,
-  FEATURE_AVX5124FMAPS,
-  FEATURE_AVX512VPOPCNTDQ,
-  // Only one bit free left in the first 32 features.
-  FEATURE_MOVBE = 32,
-  FEATURE_ADX,
-  FEATURE_EM64T,
-  FEATURE_CLFLUSHOPT,
-  FEATURE_SHA,
-};
-
 // The check below for i386 was copied from clang's cpuid.h (__get_cpuid_max).
 // Check motivated by bug reports for OpenSSL crashing on CPUs without CPUID
 // support. Consequently, for i386, the presence of CPUID is checked first
 // via the corresponding eflags bit.
 // Removal of cpuid.h header motivated by PR30384
 // Header cpuid.h and method __get_cpuid_max are not used in llvm, clang, openmp
 // or test-suite, but are used in external projects e.g. libstdcxx
 static bool isCpuIdSupported() {

 getIntelProcessorTypeAndSubtype(unsigned Family, unsigned Model,
                                 unsigned Brand_id, unsigned Features,
                                 unsigned Features2, unsigned *Type,
                                 unsigned *Subtype) {
   if (Brand_id != 0)
     return;
   switch (Family) {
   case 3:
-    *Type = INTEL_i386;
+    *Type = X86::INTEL_i386;
     break;
   case 4:
-    *Type = INTEL_i486;
+    *Type = X86::INTEL_i486;
     break;
   case 5:
-    if (Features & (1 << FEATURE_MMX)) {
-      *Type = INTEL_PENTIUM_MMX;
+    if (Features & (1 << X86::FEATURE_MMX)) {
+      *Type = X86::INTEL_PENTIUM_MMX;
       break;
     }
-    *Type = INTEL_PENTIUM;
+    *Type = X86::INTEL_PENTIUM;
     break;
   case 6:
     switch (Model) {
     case 0x01: // Pentium Pro processor
-      *Type = INTEL_PENTIUM_PRO;
+      *Type = X86::INTEL_PENTIUM_PRO;
       break;
     case 0x03: // Intel Pentium II OverDrive processor, Pentium II processor,
                // model 03
     case 0x05: // Pentium II processor, model 05, Pentium II Xeon processor,
                // model 05, and Intel Celeron processor, model 05
     case 0x06: // Celeron processor, model 06
-      *Type = INTEL_PENTIUM_II;
+      *Type = X86::INTEL_PENTIUM_II;
       break;
     case 0x07: // Pentium III processor, model 07, and Pentium III Xeon
                // processor, model 07
     case 0x08: // Pentium III processor, model 08, Pentium III Xeon processor,
                // model 08, and Celeron processor, model 08
     case 0x0a: // Pentium III Xeon processor, model 0Ah
     case 0x0b: // Pentium III processor, model 0Bh
-      *Type = INTEL_PENTIUM_III;
+      *Type = X86::INTEL_PENTIUM_III;
       break;
     case 0x09: // Intel Pentium M processor, Intel Celeron M processor model 09.
     case 0x0d: // Intel Pentium M processor, Intel Celeron M processor, model
                // 0Dh. All processors are manufactured using the 90 nm process.
     case 0x15: // Intel EP80579 Integrated Processor and Intel EP80579
                // Integrated Processor with Intel QuickAssist Technology
-      *Type = INTEL_PENTIUM_M;
+      *Type = X86::INTEL_PENTIUM_M;
       break;
     case 0x0e: // Intel Core Duo processor, Intel Core Solo processor, model
                // 0Eh. All processors are manufactured using the 65 nm process.
-      *Type = INTEL_CORE_DUO;
+      *Type = X86::INTEL_CORE_DUO;
       break;   // yonah
     case 0x0f: // Intel Core 2 Duo processor, Intel Core 2 Duo mobile
                // processor, Intel Core 2 Quad processor, Intel Core 2 Quad
                // mobile processor, Intel Core 2 Extreme processor, Intel
                // Pentium Dual-Core processor, Intel Xeon processor, model
                // 0Fh. All processors are manufactured using the 65 nm process.
     case 0x16: // Intel Celeron processor model 16h. All processors are
                // manufactured using the 65 nm process
-      *Type = INTEL_CORE2; // "core2"
-      *Subtype = INTEL_CORE2_65;
+      *Type = X86::INTEL_CORE2; // "core2"
+      *Subtype = X86::INTEL_CORE2_65;
       break;
     case 0x17: // Intel Core 2 Extreme processor, Intel Xeon processor, model
                // 17h. All processors are manufactured using the 45 nm process.
                //
                // 45nm: Penryn , Wolfdale, Yorkfield (XE)
     case 0x1d: // Intel Xeon processor MP. All processors are manufactured using
                // the 45 nm process.
-      *Type = INTEL_CORE2; // "penryn"
-      *Subtype = INTEL_CORE2_45;
+      *Type = X86::INTEL_CORE2; // "penryn"
+      *Subtype = X86::INTEL_CORE2_45;
       break;
     case 0x1a: // Intel Core i7 processor and Intel Xeon processor. All
                // processors are manufactured using the 45 nm process.
     case 0x1e: // Intel(R) Core(TM) i7 CPU         870  @ 2.93GHz.
                // As found in a Summer 2010 model iMac.
     case 0x1f:
     case 0x2e:             // Nehalem EX
-      *Type = INTEL_COREI7; // "nehalem"
-      *Subtype = INTEL_COREI7_NEHALEM;
+      *Type = X86::INTEL_COREI7; // "nehalem"
+      *Subtype = X86::INTEL_COREI7_NEHALEM;
       break;
     case 0x25: // Intel Core i7, laptop version.
     case 0x2c: // Intel Core i7 processor and Intel Xeon processor. All
                // processors are manufactured using the 32 nm process.
     case 0x2f: // Westmere EX
-      *Type = INTEL_COREI7; // "westmere"
-      *Subtype = INTEL_COREI7_WESTMERE;
+      *Type = X86::INTEL_COREI7; // "westmere"
+      *Subtype = X86::INTEL_COREI7_WESTMERE;
       break;
     case 0x2a: // Intel Core i7 processor. All processors are manufactured
                // using the 32 nm process.
     case 0x2d:
-      *Type = INTEL_COREI7; //"sandybridge"
-      *Subtype = INTEL_COREI7_SANDYBRIDGE;
+      *Type = X86::INTEL_COREI7; //"sandybridge"
+      *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
       break;
     case 0x3a:
     case 0x3e:             // Ivy Bridge EP
-      *Type = INTEL_COREI7; // "ivybridge"
-      *Subtype = INTEL_COREI7_IVYBRIDGE;
+      *Type = X86::INTEL_COREI7; // "ivybridge"
+      *Subtype = X86::INTEL_COREI7_IVYBRIDGE;
       break;
 
     // Haswell:
     case 0x3c:
     case 0x3f:
     case 0x45:
     case 0x46:
-      *Type = INTEL_COREI7; // "haswell"
-      *Subtype = INTEL_COREI7_HASWELL;
+      *Type = X86::INTEL_COREI7; // "haswell"
+      *Subtype = X86::INTEL_COREI7_HASWELL;
       break;
 
     // Broadwell:
     case 0x3d:
     case 0x47:
     case 0x4f:
     case 0x56:
-      *Type = INTEL_COREI7; // "broadwell"
-      *Subtype = INTEL_COREI7_BROADWELL;
+      *Type = X86::INTEL_COREI7; // "broadwell"
+      *Subtype = X86::INTEL_COREI7_BROADWELL;
       break;
 
     // Skylake:
     case 0x4e: // Skylake mobile
     case 0x5e: // Skylake desktop
     case 0x8e: // Kaby Lake mobile
     case 0x9e: // Kaby Lake desktop
-      *Type = INTEL_COREI7; // "skylake"
-      *Subtype = INTEL_COREI7_SKYLAKE;
+      *Type = X86::INTEL_COREI7; // "skylake"
+      *Subtype = X86::INTEL_COREI7_SKYLAKE;
       break;
 
     // Skylake Xeon:
     case 0x55:
-      *Type = INTEL_COREI7;
-      *Subtype = INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512"
+      *Type = X86::INTEL_COREI7;
+      *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512; // "skylake-avx512"
       break;
 
     case 0x1c: // Most 45 nm Intel Atom processors
     case 0x26: // 45 nm Atom Lincroft
     case 0x27: // 32 nm Atom Medfield
     case 0x35: // 32 nm Atom Midview
     case 0x36: // 32 nm Atom Midview
-      *Type = INTEL_BONNELL;
+      *Type = X86::INTEL_BONNELL;
       break; // "bonnell"
 
     // Atom Silvermont codes from the Intel software optimization guide.
     case 0x37:
     case 0x4a:
     case 0x4d:
     case 0x5a:
     case 0x5d:
     case 0x4c: // really airmont
-      *Type = INTEL_SILVERMONT;
+      *Type = X86::INTEL_SILVERMONT;
       break; // "silvermont"
     // Goldmont:
     case 0x5c:
     case 0x5f:
-      *Type = INTEL_GOLDMONT;
+      *Type = X86::INTEL_GOLDMONT;
       break; // "goldmont"
     case 0x57:
-      *Type = INTEL_KNL; // knl
+      *Type = X86::INTEL_KNL; // knl
       break;
     case 0x85:
-      *Type = INTEL_KNM; // knm
+      *Type = X86::INTEL_KNM; // knm
       break;
 
     default: // Unknown family 6 CPU, try to guess.
-      if (Features & (1 << FEATURE_AVX512F)) {
-        if (Features & (1 << FEATURE_AVX512VL)) {
-          *Type = INTEL_COREI7;
-          *Subtype = INTEL_COREI7_SKYLAKE_AVX512;
+      if (Features & (1 << X86::FEATURE_AVX512F)) {
+        if (Features & (1 << X86::FEATURE_AVX512VL)) {
+          *Type = X86::INTEL_COREI7;
+          *Subtype = X86::INTEL_COREI7_SKYLAKE_AVX512;
         } else {
-          *Type = INTEL_KNL; // knl
+          *Type = X86::INTEL_KNL; // knl
         }
         break;
       }
-      if (Features2 & (1 << (FEATURE_CLFLUSHOPT - 32))) {
-        if (Features2 & (1 << (FEATURE_SHA - 32))) {
-          *Type = INTEL_GOLDMONT;
+      if (Features2 & (1 << X86::FEATURE2_CLFLUSHOPT)) {
+        if (Features2 & (1 << X86::FEATURE2_SHA)) {
+          *Type = X86::INTEL_GOLDMONT;
         } else {
-          *Type = INTEL_COREI7;
-          *Subtype = INTEL_COREI7_SKYLAKE;
+          *Type = X86::INTEL_COREI7;
+          *Subtype = X86::INTEL_COREI7_SKYLAKE;
         }
         break;
       }
-      if (Features2 & (1 << (FEATURE_ADX - 32))) {
-        *Type = INTEL_COREI7;
-        *Subtype = INTEL_COREI7_BROADWELL;
+      if (Features2 & (1 << X86::FEATURE2_ADX)) {
+        *Type = X86::INTEL_COREI7;
+        *Subtype = X86::INTEL_COREI7_BROADWELL;
         break;
       }
-      if (Features & (1 << FEATURE_AVX2)) {
-        *Type = INTEL_COREI7;
-        *Subtype = INTEL_COREI7_HASWELL;
+      if (Features & (1 << X86::FEATURE_AVX2)) {
+        *Type = X86::INTEL_COREI7;
+        *Subtype = X86::INTEL_COREI7_HASWELL;
         break;
       }
-      if (Features & (1 << FEATURE_AVX)) {
-        *Type = INTEL_COREI7;
-        *Subtype = INTEL_COREI7_SANDYBRIDGE;
+      if (Features & (1 << X86::FEATURE_AVX)) {
+        *Type = X86::INTEL_COREI7;
+        *Subtype = X86::INTEL_COREI7_SANDYBRIDGE;
         break;
       }
-      if (Features & (1 << FEATURE_SSE4_2)) {
-        if (Features2 & (1 << (FEATURE_MOVBE - 32))) {
-          *Type = INTEL_SILVERMONT;
+      if (Features & (1 << X86::FEATURE_SSE4_2)) {
+        if (Features2 & (1 << X86::FEATURE2_MOVBE)) {
+          *Type = X86::INTEL_SILVERMONT;
         } else {
-          *Type = INTEL_COREI7;
-          *Subtype = INTEL_COREI7_NEHALEM;
+          *Type = X86::INTEL_COREI7;
+          *Subtype = X86::INTEL_COREI7_NEHALEM;
         }
         break;
       }
-      if (Features & (1 << FEATURE_SSE4_1)) {
-        *Type = INTEL_CORE2; // "penryn"
-        *Subtype = INTEL_CORE2_45;
+      if (Features & (1 << X86::FEATURE_SSE4_1)) {
+        *Type = X86::INTEL_CORE2; // "penryn"
+        *Subtype = X86::INTEL_CORE2_45;
         break;
       }
-      if (Features & (1 << FEATURE_SSSE3)) {
-        if (Features2 & (1 << (FEATURE_MOVBE - 32))) {
-          *Type = INTEL_BONNELL; // "bonnell"
+      if (Features & (1 << X86::FEATURE_SSSE3)) {
+        if (Features2 & (1 << X86::FEATURE2_MOVBE)) {
+          *Type = X86::INTEL_BONNELL; // "bonnell"
         } else {
-          *Type = INTEL_CORE2; // "core2"
-          *Subtype = INTEL_CORE2_65;
+          *Type = X86::INTEL_CORE2; // "core2"
+          *Subtype = X86::INTEL_CORE2_65;
         }
         break;
       }
-      if (Features2 & (1 << (FEATURE_EM64T - 32))) {
-        *Type = INTEL_X86_64;
+      if (Features2 & (1 << X86::FEATURE2_EM64T)) {
+        *Type = X86::INTEL_X86_64;
         break; // x86-64
       }
-      if (Features & (1 << FEATURE_SSE2)) {
-        *Type = INTEL_PENTIUM_M;
+      if (Features & (1 << X86::FEATURE_SSE2)) {
+        *Type = X86::INTEL_PENTIUM_M;
         break;
       }
-      if (Features & (1 << FEATURE_SSE)) {
-        *Type = INTEL_PENTIUM_III;
+      if (Features & (1 << X86::FEATURE_SSE)) {
+        *Type = X86::INTEL_PENTIUM_III;
         break;
       }
-      if (Features & (1 << FEATURE_MMX)) {
-        *Type = INTEL_PENTIUM_II;
+      if (Features & (1 << X86::FEATURE_MMX)) {
+        *Type = X86::INTEL_PENTIUM_II;
         break;
       }
-      *Type = INTEL_PENTIUM_PRO;
+      *Type = X86::INTEL_PENTIUM_PRO;
       break;
     }
     break;
   case 15: {
     switch (Model) {
     case 0: // Pentium 4 processor, Intel Xeon processor. All processors are
             // model 00h and manufactured using the 0.18 micron process.
     case 1: // Pentium 4 processor, Intel Xeon processor, Intel Xeon
             // processor MP, and Intel Celeron processor. All processors are
             // model 01h and manufactured using the 0.18 micron process.
     case 2: // Pentium 4 processor, Mobile Intel Pentium 4 processor - M,
             // Intel Xeon processor, Intel Xeon processor MP, Intel Celeron
             // processor, and Mobile Intel Celeron processor. All processors
             // are model 02h and manufactured using the 0.13 micron process.
-      *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_X86_64
-                                                         : INTEL_PENTIUM_IV);
+      *Type = ((Features2 & (1 << X86::FEATURE2_EM64T)) ? X86::INTEL_X86_64
+                                                        : X86::INTEL_PENTIUM_IV);
       break;
 
     case 3: // Pentium 4 processor, Intel Xeon processor, Intel Celeron D
             // processor. All processors are model 03h and manufactured using
             // the 90 nm process.
     case 4: // Pentium 4 processor, Pentium 4 processor Extreme Edition,
             // Pentium D processor, Intel Xeon processor, Intel Xeon
             // processor MP, Intel Celeron D processor. All processors are
             // model 04h and manufactured using the 90 nm process.
     case 6: // Pentium 4 processor, Pentium D processor, Pentium processor
             // Extreme Edition, Intel Xeon processor, Intel Xeon processor
             // MP, Intel Celeron D processor. All processors are model 06h
             // and manufactured using the 65 nm process.
-      *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_NOCONA
-                                                         : INTEL_PRESCOTT);
+      *Type = ((Features2 & (1 << X86::FEATURE2_EM64T)) ? X86::INTEL_NOCONA
+                                                        : X86::INTEL_PRESCOTT);
       break;
 
     default:
-      *Type = ((Features2 & (1 << (FEATURE_EM64T - 32))) ? INTEL_X86_64
-                                                         : INTEL_PENTIUM_IV);
+      *Type = ((Features2 & 1 << (X86::FEATURE2_EM64T)) ? X86::INTEL_X86_64
+                                                        : X86::INTEL_PENTIUM_IV);
       break;
     }
     break;
   }
   default:
     break; /*"generic"*/
   }
 }
 
 static void getAMDProcessorTypeAndSubtype(unsigned Family, unsigned Model,
                                           unsigned Features, unsigned *Type,
                                           unsigned *Subtype) {
   // FIXME: this poorly matches the generated SubtargetFeatureKV table.  There
   // appears to be no way to generate the wide variety of AMD-specific targets
   // from the information returned from CPUID.
   switch (Family) {
   case 4:
-    *Type = AMD_i486;
+    *Type = X86::AMD_i486;
     break;
   case 5:
-    *Type = AMDPENTIUM;
+    *Type = X86::AMDPENTIUM;
     switch (Model) {
     case 6:
     case 7:
-      *Subtype = AMDPENTIUM_K6;
+      *Subtype = X86::AMDPENTIUM_K6;
       break; // "k6"
     case 8:
-      *Subtype = AMDPENTIUM_K62;
+      *Subtype = X86::AMDPENTIUM_K62;
       break; // "k6-2"
     case 9:
     case 13:
-      *Subtype = AMDPENTIUM_K63;
+      *Subtype = X86::AMDPENTIUM_K63;
       break; // "k6-3"
     case 10:
-      *Subtype = AMDPENTIUM_GEODE;
+      *Subtype = X86::AMDPENTIUM_GEODE;
       break; // "geode"
     }
     break;
   case 6:
-    *Type = AMDATHLON;
-    if (Features & (1 << FEATURE_SSE)) {
-      *Subtype = AMDATHLON_XP;
+    *Type = X86::AMDATHLON;
+    if (Features & (1 << X86::FEATURE_SSE)) {
+      *Subtype = X86::AMDATHLON_XP;
       break; // "athlon-xp"
     }
-    *Subtype = AMDATHLON_CLASSIC;
+    *Subtype = X86::AMDATHLON_CLASSIC;
     break; // "athlon"
   case 15:
-    *Type = AMDATHLON;
-    if (Features & (1 << FEATURE_SSE3)) {
-      *Subtype = AMDATHLON_K8SSE3;
+    *Type = X86::AMDATHLON;
+    if (Features & (1 << X86::FEATURE_SSE3)) {
+      *Subtype = X86::AMDATHLON_K8SSE3;
       break; // "k8-sse3"
     }
-    *Subtype = AMDATHLON_K8;
+    *Subtype = X86::AMDATHLON_K8;
     break; // "k8"
   case 16:
-    *Type = AMDFAM10H; // "amdfam10"
+    *Type = X86::AMDFAM10H; // "amdfam10"
     switch (Model) {
     case 2:
-      *Subtype = AMDFAM10H_BARCELONA;
+      *Subtype = X86::AMDFAM10H_BARCELONA;
       break;
     case 4:
-      *Subtype = AMDFAM10H_SHANGHAI;
+      *Subtype = X86::AMDFAM10H_SHANGHAI;
       break;
     case 8:
-      *Subtype = AMDFAM10H_ISTANBUL;
+      *Subtype = X86::AMDFAM10H_ISTANBUL;
       break;
     }
     break;
   case 20:
-    *Type = AMD_BTVER1;
+    *Type = X86::AMD_BTVER1;
     break; // "btver1";
   case 21:
-    *Type = AMDFAM15H;
+    *Type = X86::AMDFAM15H;
     if (Model >= 0x60 && Model <= 0x7f) {
-      *Subtype = AMDFAM15H_BDVER4;
+      *Subtype = X86::AMDFAM15H_BDVER4;
       break; // "bdver4"; 60h-7Fh: Excavator
     }
     if (Model >= 0x30 && Model <= 0x3f) {
-      *Subtype = AMDFAM15H_BDVER3;
+      *Subtype = X86::AMDFAM15H_BDVER3;
       break; // "bdver3"; 30h-3Fh: Steamroller
     }
     if (Model >= 0x10 && Model <= 0x1f) {
-      *Subtype = AMDFAM15H_BDVER2;
+      *Subtype = X86::AMDFAM15H_BDVER2;
       break; // "bdver2"; 10h-1Fh: Piledriver
     }
     if (Model <= 0x0f) {
-      *Subtype = AMDFAM15H_BDVER1;
+      *Subtype = X86::AMDFAM15H_BDVER1;
       break; // "bdver1"; 00h-0Fh: Bulldozer
     }
     break;
   case 22:
-    *Type = AMD_BTVER2;
+    *Type = X86::AMD_BTVER2;
     break; // "btver2"
   case 23:
-    *Type = AMDFAM17H;
-    *Subtype = AMDFAM17H_ZNVER1;
+    *Type = X86::AMDFAM17H;
+    *Subtype = X86::AMDFAM17H_ZNVER1;
     break;
   default:
     break; // "generic"
   }
 }
 
 static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
                                  unsigned *FeaturesOut,
                                  unsigned *Features2Out) {
   unsigned Features = 0;
   unsigned Features2 = 0;
   unsigned EAX, EBX;
 
   if ((EDX >> 15) & 1)
-    Features |= 1 << FEATURE_CMOV;
+    Features |= 1 << X86::FEATURE_CMOV;
   if ((EDX >> 23) & 1)
-    Features |= 1 << FEATURE_MMX;
+    Features |= 1 << X86::FEATURE_MMX;
   if ((EDX >> 25) & 1)
-    Features |= 1 << FEATURE_SSE;
+    Features |= 1 << X86::FEATURE_SSE;
   if ((EDX >> 26) & 1)
-    Features |= 1 << FEATURE_SSE2;
+    Features |= 1 << X86::FEATURE_SSE2;
 
   if ((ECX >> 0) & 1)
-    Features |= 1 << FEATURE_SSE3;
+    Features |= 1 << X86::FEATURE_SSE3;
   if ((ECX >> 1) & 1)
-    Features |= 1 << FEATURE_PCLMUL;
+    Features |= 1 << X86::FEATURE_PCLMUL;
   if ((ECX >> 9) & 1)
-    Features |= 1 << FEATURE_SSSE3;
+    Features |= 1 << X86::FEATURE_SSSE3;
   if ((ECX >> 12) & 1)
-    Features |= 1 << FEATURE_FMA;
+    Features |= 1 << X86::FEATURE_FMA;
   if ((ECX >> 19) & 1)
-    Features |= 1 << FEATURE_SSE4_1;
+    Features |= 1 << X86::FEATURE_SSE4_1;
   if ((ECX >> 20) & 1)
-    Features |= 1 << FEATURE_SSE4_2;
+    Features |= 1 << X86::FEATURE_SSE4_2;
   if ((ECX >> 23) & 1)
-    Features |= 1 << FEATURE_POPCNT;
+    Features |= 1 << X86::FEATURE_POPCNT;
   if ((ECX >> 25) & 1)
-    Features |= 1 << FEATURE_AES;
+    Features |= 1 << X86::FEATURE_AES;
 
   if ((ECX >> 22) & 1)
-    Features2 |= 1 << (FEATURE_MOVBE - 32);
+    Features2 |= 1 << X86::FEATURE2_MOVBE;
 
   // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV
   // indicates that the AVX registers will be saved and restored on context
   // switch, then we have full AVX support.
   const unsigned AVXBits = (1 << 27) | (1 << 28);
   bool HasAVX = ((ECX & AVXBits) == AVXBits) && !getX86XCR0(&EAX, &EDX) &&
                 ((EAX & 0x6) == 0x6);
   bool HasAVX512Save = HasAVX && ((EAX & 0xe0) == 0xe0);
 
   if (HasAVX)
-    Features |= 1 << FEATURE_AVX;
+    Features |= 1 << X86::FEATURE_AVX;
 
   bool HasLeaf7 =
       MaxLeaf >= 0x7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);
 
   if (HasLeaf7 && ((EBX >> 3) & 1))
-    Features |= 1 << FEATURE_BMI;
+    Features |= 1 << X86::FEATURE_BMI;
   if (HasLeaf7 && ((EBX >> 5) & 1) && HasAVX)
-    Features |= 1 << FEATURE_AVX2;
+    Features |= 1 << X86::FEATURE_AVX2;
   if (HasLeaf7 && ((EBX >> 9) & 1))
-    Features |= 1 << FEATURE_BMI2;
+    Features |= 1 << X86::FEATURE_BMI2;
   if (HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512F;
+    Features |= 1 << X86::FEATURE_AVX512F;
   if (HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512DQ;
+    Features |= 1 << X86::FEATURE_AVX512DQ;
   if (HasLeaf7 && ((EBX >> 19) & 1))
-    Features2 |= 1 << (FEATURE_ADX - 32);
+    Features2 |= 1 << X86::FEATURE2_ADX;
   if (HasLeaf7 && ((EBX >> 21) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512IFMA;
+    Features |= 1 << X86::FEATURE_AVX512IFMA;
   if (HasLeaf7 && ((EBX >> 23) & 1))
-    Features2 |= 1 << (FEATURE_CLFLUSHOPT - 32);
+    Features2 |= 1 << X86::FEATURE2_CLFLUSHOPT;
   if (HasLeaf7 && ((EBX >> 26) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512PF;
+    Features |= 1 << X86::FEATURE_AVX512PF;
   if (HasLeaf7 && ((EBX >> 27) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512ER;
+    Features |= 1 << X86::FEATURE_AVX512ER;
   if (HasLeaf7 && ((EBX >> 28) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512CD;
+    Features |= 1 << X86::FEATURE_AVX512CD;
   if (HasLeaf7 && ((EBX >> 29) & 1))
-    Features2 |= 1 << (FEATURE_SHA - 32);
+    Features2 |= 1 << X86::FEATURE2_SHA;
   if (HasLeaf7 && ((EBX >> 30) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512BW;
+    Features |= 1 << X86::FEATURE_AVX512BW;
   if (HasLeaf7 && ((EBX >> 31) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512VL;
+    Features |= 1 << X86::FEATURE_AVX512VL;
 
   if (HasLeaf7 && ((ECX >> 1) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512VBMI;
+    Features |= 1 << X86::FEATURE_AVX512VBMI;
   if (HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX512VPOPCNTDQ;
+    Features |= 1 << X86::FEATURE_AVX512VPOPCNTDQ;
 
   if (HasLeaf7 && ((EDX >> 2) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX5124VNNIW;
+    Features |= 1 << X86::FEATURE_AVX5124VNNIW;
   if (HasLeaf7 && ((EDX >> 3) & 1) && HasAVX512Save)
-    Features |= 1 << FEATURE_AVX5124FMAPS;
+    Features |= 1 << X86::FEATURE_AVX5124FMAPS;
 
   unsigned MaxExtLevel;
   getX86CpuIDAndInfo(0x80000000, &MaxExtLevel, &EBX, &ECX, &EDX);
 
   bool HasExtLeaf1 = MaxExtLevel >= 0x80000001 &&
                      !getX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX);
   if (HasExtLeaf1 && ((ECX >> 6) & 1))
-    Features |= 1 << FEATURE_SSE4_A;
+    Features |= 1 << X86::FEATURE_SSE4_A;
   if (HasExtLeaf1 && ((ECX >> 11) & 1))
-    Features |= 1 << FEATURE_XOP;
+    Features |= 1 << X86::FEATURE_XOP;
   if (HasExtLeaf1 && ((ECX >> 16) & 1))
-    Features |= 1 << FEATURE_FMA4;
+    Features |= 1 << X86::FEATURE_FMA4;
 
   if (HasExtLeaf1 && ((EDX >> 29) & 1))
-    Features2 |= 1 << (FEATURE_EM64T - 32);
+    Features2 |= 1 << X86::FEATURE2_EM64T;
 
   *FeaturesOut  = Features;
   *Features2Out = Features2;
 }
 
 StringRef sys::getHostCPUName() {
   unsigned EAX = 0, EBX = 0, ECX = 0, EDX = 0;
-  unsigned MaxLeaf, Vendor;
+  unsigned MaxLeaf, Signature;
 
 #if defined(__GNUC__) || defined(__clang__)
   //FIXME: include cpuid.h from clang or copy __get_cpuid_max here
   // and simplify it to not invoke __cpuid (like cpu_model.c in
   // compiler-rt/lib/builtins/cpu_model.c?
   // Opting for the second option.
   if(!isCpuIdSupported())
     return "generic";
 #endif
-  if (getX86CpuIDAndInfo(0, &MaxLeaf, &Vendor, &ECX, &EDX) || MaxLeaf < 1)
+  if (getX86CpuIDAndInfo(0, &MaxLeaf, &Signature, &ECX, &EDX) || MaxLeaf < 1)
     return "generic";
   getX86CpuIDAndInfo(0x1, &EAX, &EBX, &ECX, &EDX);
 
   unsigned Brand_id = EBX & 0xff;
   unsigned Family = 0, Model = 0;
   unsigned Features = 0, Features2 = 0;
   detectX86FamilyModel(EAX, &Family, &Model);
   getAvailableFeatures(ECX, EDX, MaxLeaf, &Features, &Features2);
 
-  unsigned Type;
-  unsigned Subtype;
-
-  if (Vendor == SIG_INTEL) {
+  unsigned Vendor = 0;
+  unsigned Type = 0;
+  unsigned Subtype = 0;
+  if (Signature == SIG_INTEL) {
+    Vendor = X86::VENDOR_INTEL;
     getIntelProcessorTypeAndSubtype(Family, Model, Brand_id, Features,
                                     Features2, &Type, &Subtype);
-    switch (Type) {
-    case INTEL_i386:
-      return "i386";
-    case INTEL_i486:
-      return "i486";
-    case INTEL_PENTIUM:
-      return "pentium";
-    case INTEL_PENTIUM_MMX:
-      return "pentium-mmx";
-    case INTEL_PENTIUM_PRO:
-      return "pentiumpro";
-    case INTEL_PENTIUM_II:
-      return "pentium2";
-    case INTEL_PENTIUM_III:
-      return "pentium3";
-    case INTEL_PENTIUM_IV:
-      return "pentium4";
-    case INTEL_PENTIUM_M:
-      return "pentium-m";
-    case INTEL_CORE_DUO:
-      return "yonah";
-    case INTEL_CORE2:
-      switch (Subtype) {
-      case INTEL_CORE2_65:
-        return "core2";
-      case INTEL_CORE2_45:
-        return "penryn";
-      default:
-        llvm_unreachable("Unexpected subtype!");
-      }
-    case INTEL_COREI7:
-      switch (Subtype) {
-      case INTEL_COREI7_NEHALEM:
-        return "nehalem";
-      case INTEL_COREI7_WESTMERE:
-        return "westmere";
-      case INTEL_COREI7_SANDYBRIDGE:
-        return "sandybridge";
-      case INTEL_COREI7_IVYBRIDGE:
-        return "ivybridge";
-      case INTEL_COREI7_HASWELL:
-        return "haswell";
-      case INTEL_COREI7_BROADWELL:
-        return "broadwell";
-      case INTEL_COREI7_SKYLAKE:
-        return "skylake";
-      case INTEL_COREI7_SKYLAKE_AVX512:
-        return "skylake-avx512";
-      default:
-        llvm_unreachable("Unexpected subtype!");
-      }
-    case INTEL_BONNELL:
-      return "bonnell";
-    case INTEL_SILVERMONT:
-      return "silvermont";
-    case INTEL_GOLDMONT:
-      return "goldmont";
-    case INTEL_KNL:
-      return "knl";
-    case INTEL_KNM:
-      return "knm";
-    case INTEL_X86_64:
-      return "x86-64";
-    case INTEL_NOCONA:
-      return "nocona";
-    case INTEL_PRESCOTT:
-      return "prescott";
-    default:
-      break;
-    }
   } else if (Vendor == SIG_AMD) {
+    Vendor = X86::VENDOR_AMD;
     getAMDProcessorTypeAndSubtype(Family, Model, Features, &Type, &Subtype);
-    switch (Type) {
-    case AMD_i486:
-      return "i486";
-    case AMDPENTIUM:
-      switch (Subtype) {
-      case AMDPENTIUM_K6:
-        return "k6";
-      case AMDPENTIUM_K62:
-        return "k6-2";
-      case AMDPENTIUM_K63:
-        return "k6-3";
-      case AMDPENTIUM_GEODE:
-        return "geode";
-      default:
-        return "pentium";
-      }
-    case AMDATHLON:
-      switch (Subtype) {
-      case AMDATHLON_CLASSIC:
-        return "athlon";
-      case AMDATHLON_XP:
-        return "athlon-xp";
-      case AMDATHLON_K8:
-        return "k8";
-      case AMDATHLON_K8SSE3:
-        return "k8-sse3";
-      default:
-        llvm_unreachable("Unexpected subtype!");
-      }
-    case AMDFAM10H:
-      return "amdfam10";
-    case AMD_BTVER1:
-      return "btver1";
-    case AMDFAM15H:
-      switch (Subtype) {
-      default: // There are gaps in the subtype detection.
-      case AMDFAM15H_BDVER1:
-        return "bdver1";
-      case AMDFAM15H_BDVER2:
-        return "bdver2";
-      case AMDFAM15H_BDVER3:
-        return "bdver3";
-      case AMDFAM15H_BDVER4:
-        return "bdver4";
-      }
-    case AMD_BTVER2:
-      return "btver2";
-    case AMDFAM17H:
-      return "znver1";
-    default:
-      break;
-    }
   }
+
+#define X86_VENDOR_TYPE_SUBTYPE(CPUISNAME, ARCHNAME, CPUISVALID, VENDOR, TYPE, SUBTYPE) \
+  if (Vendor == VENDOR && Type == TYPE && Subtype == SUBTYPE) \
+    return ARCHNAME;
+#include "llvm/Support/X86TargetParser.def"
+
   return "generic";
 }
 
 #elif defined(__APPLE__) && (defined(__ppc__) || defined(__powerpc__))
 StringRef sys::getHostCPUName() {
   host_basic_info_data_t hostInfo;
   mach_msg_type_number_t infoCount;