[X86][NFC] Add X86CmovConverterPass to the pass registry

[aaboud]

Summary

When use -print-after-all, the pass X86CmovConverterPass was not printing the function, make it harder to debug the pass.
The reason, was that it is was not registered as a pass.
This patch is solving that problem.

Notice, that I did not see any other target specific pass that is registered.
Please, let me know if that is intended and we should not register this pass as well.

[craig.topper]

lib/Target/X86/X86CmovConversion.cpp

88

Maybe do this in LLVMInitializeX86Target in X86TargetMachine.cpp? That's where we're doing the other passes that are registered.

[craig.topper]

lib/Target/X86/X86CmovConversion.cpp

88

Or maybe we need to do it in both places?

[aaboud]

lib/Target/X86/X86CmovConversion.cpp

88

Cannot do in both places, you can register a pass only once.
I moved the registration to the LLVMInitializeX86Target as you suggested.

[aaboud]

Addressed Craig comment.

[aaboud]

Called "initializeX86CmovConverterPassPass" also from the pass constructor.

[aaboud]

lib/Target/X86/X86CmovConversion.cpp

88

Sorry, my mistake, we can call it twice.
Uploaded a new patch.

[craig.topper]

LGTM

lib/Target/X86/X86CmovConversion.cpp

 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetSchedule.h"
 #include "llvm/IR/InstIterator.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
 using namespace llvm;
 
-#define DEBUG_TYPE "x86-cmov-converter"
+#define DEBUG_TYPE "x86-cmov-conversion"
 
 STATISTIC(NumOfSkippedCmovGroups, "Number of unsupported CMOV-groups");
 STATISTIC(NumOfCmovGroupCandidate, "Number of CMOV-group candidates");
 STATISTIC(NumOfLoopCandidate, "Number of CMOV-conversion profitable loops");
 STATISTIC(NumOfOptimizedCmovGroups, "Number of optimized CMOV-groups");
 
+namespace llvm {
+  void initializeX86CmovConverterPassPass(PassRegistry &);
+}
+
 namespace {
 // This internal switch can be used to turn off the cmov/branch optimization.
 static cl::opt<bool>
     EnableCmovConverter("x86-cmov-converter",
                         cl::desc("Enable the X86 cmov-to-branch optimization."),
                         cl::init(true), cl::Hidden);
 
 static cl::opt<unsigned>
     GainCycleThreshold("x86-cmov-converter-threshold",
                        cl::desc("Minimum gain per loop (in cycles) threshold."),
                        cl::init(4), cl::Hidden);
 
 static cl::opt<bool> ForceMemOperand(
     "x86-cmov-converter-force-mem-operand",
     cl::desc("Convert cmovs to branches whenever they have memory operands."),
     cl::init(true), cl::Hidden);
 
 /// Converts X86 cmov instructions into branches when profitable.
 class X86CmovConverterPass : public MachineFunctionPass {
 public:
   X86CmovConverterPass() : MachineFunctionPass(ID) {}
   ~X86CmovConverterPass() {}
 
   StringRef getPassName() const override { return "X86 cmov Conversion"; }
   bool runOnMachineFunction(MachineFunction &MF) override;
   void getAnalysisUsage(AnalysisUsage &AU) const override;
 
-private:
   /// Pass identification, replacement for typeid.
   static char ID;
 
+private:
+
   MachineRegisterInfo *MRI;
   const TargetInstrInfo *TII;
   const TargetRegisterInfo *TRI;
   TargetSchedModel TSchedModel;
 
   /// List of consecutive CMOV instructions.
   typedef SmallVector<MachineInstr *, 2> CmovGroup;
   typedef SmallVector<CmovGroup, 2> CmovGroups;
bool checkForProfitableCmovCandidates(ArrayRef<MachineBasicBlock *> Blocks,
                                         CmovGroups &CmovInstGroups);
 
   /// Convert the given list of consecutive CMOV instructions into a branch.
   ///
   /// \param Group Consecutive CMOV instructions to be converted into branch.
   void convertCmovInstsToBranches(SmallVectorImpl<MachineInstr *> &Group) const;
 };
 
-char X86CmovConverterPass::ID = 0;
-
 void X86CmovConverterPass::getAnalysisUsage(AnalysisUsage &AU) const {
   MachineFunctionPass::getAnalysisUsage(AU);
   AU.addRequired<MachineLoopInfo>();
 }
 
 bool X86CmovConverterPass::runOnMachineFunction(MachineFunction &MF) {
   if (skipFunction(*MF.getFunction()))
     return false;
void X86CmovConverterPass::convertCmovInstsToBranches(
   }
 
   // Now remove the CMOV(s).
   MBB->erase(MIItBegin, MIItEnd);
 }
 
 } // End anonymous namespace.
 
+char X86CmovConverterPass::ID = 0;
+
+INITIALIZE_PASS_BEGIN(X86CmovConverterPass, DEBUG_TYPE, "X86 cmov Conversion",
+                      false, false)
+INITIALIZE_PASS_DEPENDENCY(MachineLoopInfo)
+INITIALIZE_PASS_END(X86CmovConverterPass, DEBUG_TYPE, "X86 cmov Conversion",
+                    false, false)
+
 FunctionPass *llvm::createX86CmovConverterPass() {
   return new X86CmovConverterPass();
 }

lib/Target/X86/X86TargetMachine.cpp

 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
                                cl::desc("Enable the machine combiner pass"),
                                cl::init(true), cl::Hidden);
 
 namespace llvm {
 
 void initializeWinEHStatePassPass(PassRegistry &);
 void initializeFixupLEAPassPass(PassRegistry &);
+void initializeX86CmovConverterPassPass(PassRegistry &);
 void initializeX86ExecutionDepsFixPass(PassRegistry &);
 
 } // end namespace llvm
 
 extern "C" void LLVMInitializeX86Target() {
   // Register the target.
   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
 
   PassRegistry &PR = *PassRegistry::getPassRegistry();
   initializeGlobalISel(PR);
   initializeWinEHStatePassPass(PR);
   initializeFixupBWInstPassPass(PR);
   initializeEvexToVexInstPassPass(PR);
   initializeFixupLEAPassPass(PR);
+  initializeX86CmovConverterPassPass(PR);
   initializeX86ExecutionDepsFixPass(PR);
 }
 
 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
   if (TT.isOSBinFormatMachO()) {
     if (TT.getArch() == Triple::x86_64)
       return llvm::make_unique<X86_64MachoTargetObjectFile>();
     return llvm::make_unique<TargetLoweringObjectFileMachO>();