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[instCombine] Handle (X & C2) < C1 --> (X & C2) == 0
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Authored by craig.topper on Sep 19 2017, 5:47 PM.

Details

Summary

We already did (X & C2) > C1 --> (X & C2) != 0, if any bit set in (X & C2) will produce a result greater than C1. But there is an equivalent inverse condition with <= C1 (which will be canonicalized to < C1+1)

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Repository
rL LLVM

Event Timeline

craig.topper created this revision.Sep 19 2017, 5:47 PM
spatel accepted this revision.Sep 20 2017, 9:51 AM
spatel added a subscriber: nlopes.

LGTM. The bit-logic looks right to me - but I miss Alive. :)
cc @nlopes

See inline for some nits.

lib/Transforms/InstCombine/InstCombineCompares.cpp
1720 ↗(On Diff #115937)

Is this is a weird way of asking: !C2->isNullValue() ?

1722 ↗(On Diff #115937)

The change to use getActiveBits() could be an NFC commit before this patch.

test/Transforms/InstCombine/icmp.ll
1141 ↗(On Diff #115937)

Would be nice to have a test that uses constants at/near the limits. Something like:
define i1 @test67inverse(i8 %x) {

%and = and i8 %x, -128
%cmp = icmp ult i8 %and, 126
ret i1 %cmp

}

Could use vectors to add more testing diversity...assuming that works.

This revision is now accepted and ready to land.Sep 20 2017, 9:51 AM
This revision was automatically updated to reflect the committed changes.